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under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 1 about m32c/83 group the m32c/83 group of single-chip microcomputers are built using a high-performance silicon gate cmos process uses a m32c/80 series cpu core and are packaged in a 144-pin and 100-pin plastic molded qfp. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc- tion efficiency. with 16m bytes of address space, they are capable of executing instructions at high speed. they also feature a built-in multiplier and dmac, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications. applications audio, cameras, office equipment, communications equipment, portable equipment, etc. index specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition. about m32c/83 group .......................................... 1 central processing unit (cpu) ........................... 20 reset ................................................................... 24 sfr ..................................................................... 37 software reset ................................................... 48 processor mode .................................................. 48 bus settings ........................................................ 52 bus control ......................................................... 55 system clock ...................................................... 65 power saving ...................................................... 76 protection ............................................................ 81 interrupt outline .................................................. 83 ______ int interrupts ...................................................... 98 ______ nmi interrupt ....................................................... 99 key input interrupt .............................................. 99 address match interrupt .................................... 100 intelligent i/o and can interrupt ....................... 101 precautions for interrupts .................................. 104 watchdog timer ................................................ 106 dmac ............................................................... 109 dmac ii ............................................................ 121 timer ................................................................. 129 timer a .............................................................. 131 timer b .............................................................. 147 three-phase motor control timers functions ..... 155 serial i/o ........................................................... 168 can module ...................................................... 198 intelligent i/o ..................................................... 235 base timer (group 0 to 3) .................................. 240 time measurement (group 0 and 1) .................. 247 wg function (group 0 to 3) ................................ 252 serial i/o (group 0 to 2) .................................... 264 a-d converter ................................................... 281 d-a converter ................................................... 296 crc calculation circuit .................................... 298 x-y converter ................................................... 300 dram controller ............................................... 303 programmable i/o ports ................................... 310 vdc .................................................................. 334 usage precaution ............................................. 335 electrical characteristics ................................... 344 outline performance ......................................... 381 flash memory ................................................... 383 cpu rewrite mode ........................................... 384 outline performance of cpu rewrite mode ..... 384 inhibit rewriting flash memory version ............ 397 parallel i/o mode .............................................. 399 standard serial i/o mode .................................. 400
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 2 performance outline table 1.1.1 and 1.1.2 are performance outline of m32c/83 group. table 1.1.1. performance outline of m32c/83 group (144-pin version) (1/2) item performance cpu number of basic instructions 108 instructions shortest instruction execution time 33 ns(f(x in )=30mhz) operation mode single-chip, memory expansion and microprocessor modes memory space 16 m bytes memory capacity see rom/ram expansion figure. peripheral function i/o port 123 pins (p0 to p15 except p8 5 ) input port 1 pin (p8 5 ) multifunction timer output 16 bits x 5 (ta0, ta1, ta2, ta3, ta4) input 16 bits x 6 (tb0, tb1, tb2, tb3, tb4, tb5) intelligent i/o 4 groups time measurement 8 channels (group 0) + 4 channels (group 1) waveform generation 4 channels (group 0) + 8 channels x 3 (group 1, 2 and 3) bit-modulation pwm 8 channels x 2 (group 2 and 3) real time port 8 channels x 2 (group 2 and 3) communication function ? clock synchronous serial i/o, uart (group 0 and 1) ? hdlc data process (group 0 and 1) ? clock synchronous variable length serial i/o (group 2) ? ie bus (note 1) (group 2) serial i/o 5 channels (uart0 to uart4) ie bus (note 1, 3) , i 2 c bus (note 2, 3) can module 1 channel, 2.0b specification a-d converter 10-bit a-d x 2 circuits, standard 18 inputs, max 34 inputs d-a converter 8-bit d-a x 2 circuits dmac 4 channels dmac ii start by all variable vector interrupt factor immediate transfer, operation transfer and chain transfer function dram controller cas before ras refresh, self-refresh, edo, fp crc calculation circuit crc-ccitt x-y converter 16 bits x 16 bits watchdog timer 15 bits x 1 (with prescaler) interrupt 42 internal and 8 external sources, 5 software sources, interrupt priority level 7 levels clock generating circuit 3 built-in clock generation circuits ? main/sub-clock generating circuit :built-in feedback resistance, and external ceramic or quartz oscillator ? ring oscillator for detecting main clock oscillation stop
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 3 table 1.1.1. performance outline of m32c/83 group (144-pin version) (2/2) electric characteristics supply voltage 4.2 to 5.5v (f(x in )=30mhz without wait), 3.0 to 3.6v (f(x in )=20mhz without wait) power consumption 26ma (f(x in )=20mhz without software wait,vcc=5v) 38ma (f(x in )=30mhz without software wait,vcc=5v) i/o characteristics i/o withstand voltage :5v i/o current :5ma operating ambient temperature C 40 to 85 o c device configuration cmos high performance silicon gate package 144-pin plastic mold qfp note 1 :ie bus is a trademark of nec corporation. note 2 :i 2 c bus is a registered trademark of philips. note 3 :this function is executed by using software and hardware. table 1.1.2. performance outline of m32c/83 group (100-pin version) (1/2) item performance cpu number of basic instructions 108 instructions shortest instruction execution time 33 ns (f(x in )=30mhz) operation mode single-chip, memory expansion and microprocessor modes memory space 16 m bytes memory capacity see rom/ram expansion figure. peripheral function i/o port 87 pins (p0 to p10 except p8 5 ) input port 1 pin (p8 5 ) multifunction timer output 16 bits x 5 (ta0, ta1, ta2, ta3, ta4) input 16 bits x 6 (tb0, tb1, tb2, tb3, tb4, tb5) intelligent i/o 4 groups time measurement 3 channels (group 0) + 2 channels (group 1) waveform generation 2 channels x 2 (group 0 and 3) + 3 channels x 2 (group 1 and 2) bit-modulation pwm 3 channels (group 2) + 2 channels (group 3) real time port 3 channels (group 2) + 2 channels (group 3) communication function ? clock synchronous serial i/o, uart (group 0 and 1) ? hdlc data process (group 0 and 1) ? clock synchronous variable length serial i/o (group 2) ? ie bus (note 1) (group 2) serial i/o 5 channels (uart0 to uart4) ie bus (note 1, 3) , i 2 c bus (note 2, 3) can module 1 channel, 2.0b specification a-d converter 10 bits a-dx 2 circuits, standard 10 inputs, max 26 inputs d-a converter 8 bits d-a x 2 circuits dmac 4 channels dmac ii start by all variable vector interrupt factor immediate transfer, operation function and chain transfer function dram controller cas before ras refresh, self-refresh, edo, fp crc calculation circuit crc-ccitt
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 4 table 1.1.2. performance outline of m32c/83 group (100-pin version) (2/2) x-y converter 16 bits x 16 bits watchdog timer 15 bits x 1 (with prescaler) interrupt 42 internal and 8 external sources, 5 software sources, interrupt priority level 7 levels clock generating circuit 3 built-in clock generation circuits ? main/sub-clock generating circuit :built-in feedback resistance, and external ceramic or quartz oscillator ? ring oscillator for detecting main clock oscillation stop electric characteristics supply voltage 4.2 to 5.5v (f(x in )=30mhz without wait), 3.0 to 3.6v (f(x in )=20mhz without wait) power consumption 26ma (f(x in )=20mhz without software wait,vcc=5v) 38ma (f(x in )=30mhz without software wait,vcc=5v) i/o characteristics i/o withstand voltage :5v i/o current :5ma operating ambient temperature C 40 to 85 o c device configuration cmos high performance silicon gate package 100-pin plastic mold qfp note 1 :ie bus is a trademark of nec corporation. note 2 :i 2 c bus is a registered trademark of philips. note 3 :this function is executed by using software and hardware. mitsubishi plans to release the following products in the m32c/83 group: (1) support for mask rom version and flash memory version (2) rom capacity (3) package 100p6s-a : plastic molded qfp (mask rom version and flash memory version) 100p6q-a : plastic molded qfp (mask rom version and flash memory version) 144p6q-a : plastic molded qfp (mask rom version and flash memory version) ram size (byte) m30835fjgp m30835mjgp 31k m30833fjgp m30833mjgp m30833fjfp m30833mjfp 20k 10k 128k 192k 256k 512k rom size (byte) figure 1.1.1. rom expansion
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 5 the m32c/83 group products currently supported are listed in table 1.1.3. table 1.1.3. m32c/83 group as of nov. 2001 type no rom capacity ram capacity package type remarks m30835mjgp *** 144p6q-a m30833mjgp *** 100p6q-a mask rom version m30833mjfp *** 100p6s-a 512k 31k m30835fjgp ** 144p6q-a m30833fjgp ** 100p6q-a flash memory version m30833fjfp ** 100p6s-a ** :under development *** :under planning figure 1.1.2. type no., memory size, and package package type: fp : package 100p6s-a gp : package 100p6q-a, 144p6q-a rom capacity: j : 512k bytes memory type: m : mask rom version f : flash memory version type no. m 3 0 8 3 5 f j C (x x x ) g p m32c/83 group m16c family shows ram capacity, pin count, etc (the value itself has no specific meaning)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 6 pin configuration and pin description figure 1.1.3 to 1.1.5 show the pin configurations (top view), table 1.1.3 list pin names, and table 1.1.4 list pin description. figure 1.1.3. 144-pin version pin configuration (top view) srxd4 / sda4 / txd4 / anex1 / p9 6 clk4 / anex0 / p9 5 ss4 / rts4 / cts4 / tb4 in / da1 / p9 4 ss3 / rts3 / cts3 / tb3 in / da0 / p9 3 ie out / outc2 0 / srxd3 / sda3 / txd3 / tb2 in / p9 2 ie in / stxd3 / scl3 / rxd3 / tb1 in / p9 1 clk3 / tb0 in / p9 0 p14 6 p14 5 p14 4 outc1 7 / inpc1 7 / p14 3 outc1 6 / inpc1 6 / p14 2 outc1 5 / p14 1 outc1 4 / p14 0 byte cnvss v cont / x cin / p8 7 x cout / p8 6 reset x out vss x in vcc nmi / p8 5 int2 / p8 4 can in / int1 / p8 3 can out / outc3 2 / int0 / p8 2 outc3 0 / u / ta4 in / p8 1 be0 in / isrxd0 / inpc0 2 / u / ta4 out / p8 0 can in / isclk0 / outc0 1 / inpc0 1 / ta3 in / p7 7 can out / be0 out / istxd0 / outc0 0 / inpc0 0 / ta3 out / p7 6 be1 in / isrxd1 / outc1 2 / inpc1 2 / w / ta2 in / p7 5 isclk1 / outc1 1 / inpc1 1 / w / ta2 out / p7 4 be1 out / istxd1 / outc1 0 / ss2 / rts2 / cts2 / v / ta1 in / p7 3 clk2 / v / ta1 out / p7 2 ie in / isrxd2 / outc2 2 / stxd2 / scl2 / rxd2 / ta0 in / tb5 in / p7 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 50 49 48 47 46 45 44 43 42 41 40 39 38 37 56 55 54 53 52 51 62 61 60 59 58 57 68 67 66 65 64 63 72 71 70 69 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 131 132 133 134 135 136 137 138 139 140 141 142 143 144 125 126 127 128 129 130 119 120 121 122 123 124 113 114 115 116 117 118 109 110 111 112 m32c/83 (144p6q-a) p1 1 / d 9 p1 2 / d 10 p1 3 / d 11 p1 4 / d 12 p1 5 / d 13 / int3 p1 6 / d 14 / int4 p1 7 / d 15 / int5 p2 0 / a 0 ( / d 0 ) / an2 0 p2 1 / a 1 ( / d 1 ) / an2 1 p2 2 / a 2 ( / d 2 ) / an2 2 p2 3 / a 3 ( / d 3 ) / an2 3 p2 4 / a 4 ( / d 4 ) / an2 4 p2 5 / a 5 ( / d 5 ) / an2 5 p2 6 / a 6 ( / d 6 ) / an2 6 p2 7 / a 7 ( / d 7 ) / an2 7 vss p3 0 / a 8 ( ma 0 ) ( / d 8 ) vcc p12 0 / outc3 0 p12 1 / outc3 1 p12 2 / outc3 2 p12 3 / outc3 3 p12 4 / outc3 4 p3 1 / a 9 ( ma 1 ) ( / d 9 ) p3 2 / a 10 ( ma 2 ) ( / d 10 ) p3 3 / a 11 ( ma 3 ) ( / d 11 ) p3 4 / a 12 ( ma 4 ) ( / d 12 ) p3 5 / a 13 ( ma 5 ) ( / d 13 ) p3 6 / a 14 ( ma 6 ) ( / d 14 ) p3 7 / a 15 ( ma 7 ) ( / d 15 ) p4 0 / a 16 ( ma 8 ) p4 1 / a 17 ( ma 9 ) vss p4 2 / a 18 ( ma 10 ) vcc p4 3 / a 19 ( ma 11 ) d 8 / p1 0 an0 7 / d 7 / p0 7 an0 6 / d 6 / p0 6 an0 5 / d 5 / p0 5 an0 4 / d 4 / p0 4 p11 4 outc1 3 / p11 3 be1 in / isrxd 1 / outc1 2 / inpc1 2 / p11 2 isclk1 / outc1 1 / inpc1 1 / p11 1 be1 out / istxd1 / outc1 0 / p11 0 an0 3 / d 3 / p0 3 an0 2 / d 2 / p0 2 an0 1 / d 1 / p0 1 an0 0 / d 0 / p0 0 inpc0 7 / an15 7 / p15 7 inpc0 6 / an15 6 / p15 6 outc0 5 / inpc0 5 / an15 5 / p15 5 outc0 4 / inpc0 4 / an15 4 / p15 4 inpc0 3 / an15 3 / p15 3 be0 in / isrxd0 / inpc0 2 / an15 2 / p15 2 isclk0 / outc0 1 / inpc0 1 / an15 1 / p15 1 vss be0 out / istxd0 / outc0 0 / inpc0 0 / an15 0 / p15 0 vcc ki 3 / an 7 / p10 7 ki 2 / an 6 / p10 6 ki 1 / an 5 / p10 5 ki 0 / an 4 / p10 4 an 3 / p10 3 an 2 / p10 2 an 1 / p10 1 avss an 0 / p10 0 v ref avcc stxd4 / scl4 / rxd4 / ad trg / p9 7 p4 4 / cs3 / a 20 (ma 12 ) p4 5 / cs2 / a 21 p4 6 / cs1 / a 22 p4 7 / cs0 / a 23 p12 5 / outc3 5 p12 6 / outc3 6 p12 7 / outc3 7 p5 0 / wrl / wr / casl p5 1 / wrh / bhe / cash p5 2 / rd / dw p5 3 / clk out / bclk / ale p13 0 / outc2 4 p13 1 / outc2 5 vcc p13 2 / outc2 6 vss p13 3 / outc2 3 p5 4 / hlda / ale p5 5 / hold p5 6 / ale / ras p5 7 / rdy p13 4 / outc2 0 / istxd2 / ie out p13 5 / outc2 2 / isrxd2 / ie in p13 6 / outc2 1 / isclk2 p13 7 / outc2 7 p6 0 / cts0 / rts0 / ss0 p6 1 / clk0 p6 2 / rxd0 / scl0 / stxd0 p6 3 / txd0 / sda0 / srxd0 p6 4 / cts1 / rts1 / ss1 / outc2 1 / isclk2 p6 5 / clk1 vss p6 6 / rxd1 / scl1 / stxd1 vcc p6 7 / txd1 / sda1 / srxd1 p7 0 / ta0 out / txd2 / sda2 / srxd2 / outc2 0 / istxd2 / ie out note: p7 0 and p7 1 are n-channel open drain output.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 7 table 1.1.4. 144-pin version pin description (1/3) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 control byte cnv ss x cin /v cont x cout reset x out v ss x in v cc v cc v ss port p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 p14 6 p14 5 p14 4 p14 3 p14 2 p14 1 p14 0 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 p13 7 nmi int2 int1 int0 timer tb4 in tb3 in tb2 in tb1 in tb0 in ta4 in /u ta4 out /u ta3 in ta3 out ta2 in /w ta2 out /w ta1 in /v ta1 out /v tb5 in /ta0 in ta0 out uart/can txd4/sda4/srxd4 clk4 cts4/rts4/ss4 cts3/rts3/ss3 txd3/sda3/srxd3 rxd3/scl3/stxd3 clk3 can in can out can in can out cts2/rts2/ss2 clk2 rxd2/scl2/stxd2 txd2/sda2/srxd2 txd1/sda1/srxd1 rxd1/scl1/stxd1 clk1 cts1/rts1/ss1 txd0/sda0/srxd0 rxd0/scl0/stxd0 clk0 cts0/rts0/ss0 outc2 0 /ie out ie in inpc1 7 /outc1 7 inpc1 6 /outc1 6 outc1 5 outc1 4 outc3 2 outc3 0 inpc0 2 /isrxd0/be0 in inpc0 1 /outc0 1 /isclk0 inpc0 0 /outc0 0 /istxd0/be0 out inpc1 2 /outc1 2 /isrxd1/be1 in inpc1 1 /outc1 1 /isclk1 outc1 0 /istxd1/be1 out outc2 2 /isrxd2/ie in outc2 0 /istxd2/ie out outc2 1 /isclk2 outc2 7 anex1 anex0 da1 da0 intelligent i/o bus control analog interrupt pin no
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 8 table 1.1.5. 144-pin version pin description (2/3) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 control v ss v cc v cc v ss v cc v ss port p13 6 p13 5 p13 4 p5 7 p5 6 p5 5 p5 4 p13 3 p13 2 p13 1 p13 0 p5 3 p5 2 p5 1 p5 0 p12 7 p12 6 p12 5 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p12 4 p12 3 p12 2 p12 1 p12 0 p3 0 p2 7 p2 6 p2 5 timer uart/can outc2 1 /isclk2 outc2 2 /isrxd2/ie in outc2 0 /istxd2/ie out outc2 3 outc2 6 outc2 5 outc2 4 outc3 7 outc3 6 outc3 5 outc3 4 outc3 3 outc3 2 outc3 1 outc3 0 an3 7 an3 6 an3 5 rdy ale/ras hold hlda/ale clk out /bclk/ale rd/dw wrh/bhe/cash wrl/wr/casl cs0/a 23 cs1/a 22 cs2/a 21 cs3/a 20 (ma 12 ) a 19 (ma 11 ) a 18 (ma 10 ) a 17 (ma 9 ) a 16 (ma 8 ) a 15 (ma 7 )(/d 15 ) a 14 (ma 6 )(/d 14 ) a 13 (ma 5 )(/d 13 ) a 12 (ma 4 )(/d 12 ) a 11 (ma 3 )(/d 11 ) a 10 (ma 2 )(/d 10 ) a 9 (ma 1 )(/d 9 ) a 8 (ma 0 )(/d 8 ) a 7 (/d 7 ) a 6 (/d 6 ) a 5 (/d 5 ) intelligent i/o bus control analog interrupt pin no
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 9 table 1.1.6. 144-pin version pin description (3/3) 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 control v ss v cc av ss v ref av cc port p2 4 p2 3 p2 2 p2 1 p2 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 p0 7 p0 6 p0 5 p0 4 p11 4 p11 3 p11 2 p11 1 p11 0 p0 3 p0 2 p0 1 p0 0 p15 7 p15 6 p15 5 p15 4 p15 3 p15 2 p15 1 p15 0 p10 7 p10 6 p10 5 p10 4 p10 3 p10 2 p10 1 p10 0 p9 7 int5 int4 int3 ki 3 ki 2 ki 1 ki 0 timer uart/can rxd4/scl4/stxd4 an2 4 an2 3 an2 2 an2 1 an2 0 an0 7 an0 6 an0 5 an0 4 an0 3 an0 2 an0 1 an0 0 an15 7 an15 6 an15 5 an15 4 an15 3 an15 2 an15 1 an15 0 an 7 an 6 an 5 an 4 an 3 an 2 an 1 an 0 ad trg a 4 (/d 4 ) a 3 (/d 3 ) a 2 (/d 2 ) a 1 (/d 1 ) a 0 (/d 0 ) d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bus control analog interrupt pin no intelligent i/o outc1 3 inpc1 2 /outc1 2 /isrxd1/be1 in inpc1 1 /outc1 1 /isclk1 outc1 0 /istxd1/be1 out inpc0 7 inpc0 6 inpc0 5 /outc0 5 inpc0 4 /outc0 4 inpc0 3 inpc0 2 /isrxd0/be0 in inpc0 1 /outc0 1 /isclk0 inpc0 0 /outc0 0 /istxd0/be0 out
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 10 figure 1.1.4. 100-pin version pin configuration (top view) 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 srxd4 / sda4 / txd4 / anex1 / p9 6 clk4 / anex0 / p9 5 ss4 / rts4 / cts4 / tb4 in / da1 / p9 4 ss3 / rts3 / cts3 / tb3 in / da0 / p9 3 ie out / outc2 0 / srxd3 / sda3 / txd3 / tb2 in / p9 2 ie in / stxd3 / scl3 / rxd3 / tb1 in / p9 1 clk3 / tb0 in / p9 0 byte cnvss v cont / x cin / p8 7 x cout / p8 6 reset x out vss x in vcc nmi / p8 5 int2 / p8 4 can in / int1 / p8 3 can out / outc3 2 / int0 / p8 2 outc3 0 / u / ta4 in / p8 1 be0 in / isrxd0 /inpc0 2 / u / ta4 out / p8 0 can in / isclk0 / outc0 1 / inpc0 1 / ta3 in / p7 7 can out / be0 out / istxd0 / outc0 0 / inpc0 0 / ta3 out / p7 6 be1 in / isrxd1 / outc1 2 / inpc1 2 / w / ta2 in / p7 5 isclk1 / outc1 1 / inpc1 1 / w / ta2 out / p7 4 be1 out / istxd1 / outc1 0 / ss2 / rts2 / cts2 / v / ta1 in / p7 3 clk2 / v / ta1 out / p7 2 ie in / isrxd2 / outc2 2 / stxd2 / scl2 / rxd2 / ta0 in / tb5 in / p7 1 ie out / istxd2 / outc2 0 / srxd2 / sda2 / txd2 / ta0 out / p7 0 p4 4 / cs3 / a 20 (ma 12 ) p4 5 / cs2 / a 21 p4 6 / cs1 / a 22 p4 7 / cs0 / a 23 p5 0 / wrl / wr / casl p5 1 / wrh / bhe / cash p5 2 / rd / dw p5 3 / clk out / bclk / ale p5 4 / hlda / ale p5 5 / hold p5 6 / ale / ras p5 7 / rdy p6 0 / cts0 / rts0 / ss0 p6 1 / clk0 p6 2 / rxd0 / scl0 / stxd0 p6 3 / txd0 / sda0 / srxd0 p6 4 / cts1 / rts1 / ss1 / outc2 1 / isclk2 p6 5 / clk1 p6 6 / rxd1 / scl1 / stxd1 p6 7 / txd1 / sda1 / srxd1 p1 0 / d 8 p1 1 / d 9 p1 2 / d 10 p1 3 / d 11 p1 4 / d 12 p1 5 / d 13 / int3 p1 6 / d 14 / int4 p1 7 / d 15 / int5 p2 0 / a 0 ( / d 0 ) / an2 0 p2 1 / a 1 ( / d 1 ) / an2 1 p2 2 / a 2 ( / d 2 ) / an2 2 p2 3 / a 3 ( / d 3 ) / an2 3 p2 4 / a 4 ( / d 4 ) / an2 4 p2 5 / a 5 ( / d 5 ) / an2 5 p2 6 / a 6 ( / d 6 ) / an2 6 p2 7 / a 7 ( / d 7 ) / an2 7 vss p3 0 / a 8 ( ma 0 ) ( / d 8 ) vcc p3 1 / a 9 ( ma 1 ) ( / d 9 ) p3 2 / a 10 ( ma 2 ) ( / d 10 ) p3 3 / a 11 ( ma 3 ) ( / d 11 ) p3 4 / a 12 ( ma 4 ) ( / d 12 ) p3 5 / a 13 ( ma 5 ) ( / d 13 ) p3 6 / a 14 ( ma 6 ) ( / d 14 ) p3 7 / a 15 ( ma 7 ) ( / d 15 ) p4 0 / a 16 ( ma 8 ) p4 1 / a 17 ( ma 9 ) p4 2 / a 18 ( ma 10 ) p4 3 / a 19 ( ma 11 ) d 7 / an0 7 / p0 7 d 6 / an0 6 / p0 6 d 5 / an0 5 / p0 5 d 4 / an0 4 / p0 4 d 3 / an0 3 / p0 3 d 2 / an0 2 / p0 2 d 1 / an0 1 / p0 1 d 0 / an0 0 / p0 0 ki 3 / an 7 / p10 7 ki 2 / an 6 / p10 6 ki 1 / an 5 / p10 5 ki 0 / an 4 / p10 4 an 3 / p10 3 an 2 / p10 2 an 1 / p10 1 avss an 0 / p10 0 v ref avcc rxd4 / ad trg / p9 7 stxd4 / scl4 / m32c/83 (100p6s-a) note: p7 0 and p7 1 are n-channel open drain output.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 11 figure 1.1.5. 100-pin version pin configuration (top view) 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 30 29 28 27 26 76 77 78 79 80 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 ss4 / rts4 / cts4 / tb4 in / da1 / p9 4 ss3 / rts3 / cts3 / tb3 in / da0 / p9 3 ie out / outc2 0 / srxd3 / sda3 / txd3 / tb2 in / p9 2 ie in / stxd3 / scl3 / rxd3 / tb1 in / p9 1 clk3 / tb0 in / p9 0 byte cnvss v cont / x cin / p8 7 x cout / p8 6 reset x out vss x in vcc nmi / p8 5 int2 / p8 4 can in / int1 / p8 3 can out / outc3 2 / int0 / p8 2 outc3 0 / u / ta4 in / p8 1 be0 in / isrxd0 /inpc0 2 / u / ta4 out / p8 0 can in / isclk0 / outc0 1 / inpc0 1 / ta3 in / p7 7 can out / be0 out / istxd0 / outc0 0 / inpc0 0 / ta3 out / p7 6 be1 in / isrxd1 / outc1 2 / inpc1 2 / w / ta2 in / p7 5 isclk1 / outc1 1 / inpc1 1 / w / ta2 out / p7 4 be1 out / istxd1 / outc1 0 / ss2 / rts2 / cts2 / v / ta1 in / p7 3 p4 2 / a 18 ( ma 10 ) p4 3 / a 19 ( ma 11 ) p4 4 / cs3 / a 20 (ma 12 ) p4 5 / cs2 / a 21 p4 6 / cs1 / a 22 p4 7 / cs0 / a 23 p5 0 / wrl / wr / casl p5 1 / wrh / bhe / cash p5 2 / rd / dw p5 3 / clk out / bclk / ale p5 4 / hlda / ale p5 5 / hold p5 6 / ale / ras p5 7 / rdy p6 0 / cts0 / rts0 / ss0 p6 1 / clk0 p6 2 / rxd0 / scl0 / stxd0 p6 3 / txd0 / sda0 / srxd0 p6 4 / cts1 / rts1 / ss1 / outc2 1 / isclk2 p6 5 / clk1 p6 6 / rxd1 / scl1 / stxd1 p6 7 / txd1 / sda1 / srxd1 p7 0 / ta0 out / txd2 / sda2 / srxd2 / outc2 0 p7 1 / ta0 in / tb5 in / rxd2 / scl2 / stxd2 / outc2 2 p7 2 / ta1 out / v / clk2 p1 3 / d 11 p1 4 / d 12 p1 5 / d 13 / int3 p1 6 / d 14 / int4 p1 7 / d 15 / int5 p2 0 / a 0 ( / d 0 ) / an2 0 p2 1 / a 1 ( / d 1 ) / an2 1 p2 2 / a 2 ( / d 2 ) / an2 2 p2 3 / a 3 ( / d 3 ) / an2 3 p2 4 / a 4 ( / d 4 ) / an2 4 p2 5 / a 5 ( / d 5 ) / an2 5 p2 6 / a 6 ( / d 6 ) / an2 6 p2 7 / a 7 ( / d 7 ) / an2 7 vss p3 0 / a 8 ( ma 0 ) ( / d 8 ) vcc p3 1 / a 9 ( ma 1 ) ( / d 9 ) p3 2 / a 10 ( ma 2 ) ( / d 10 ) p3 3 / a 11 ( ma 3 ) ( / d 11 ) p3 4 / a 12 ( ma 4 ) ( / d 12 ) p3 5 / a 13 ( ma 5 ) ( / d 13 ) p3 6 / a 14 ( ma 6 ) ( / d 14 ) p3 7 / a 15 ( ma 7 ) ( / d 15 ) p4 0 / a 16 ( ma 8 ) p4 1 / a 17 ( ma 9 ) d 10 / p1 2 d 9 / p1 1 d 8 / p1 0 d 7 / an0 7 / p0 7 d 6 / an0 6 / p0 6 d 5 / an0 5 / p0 5 d 4 / an0 4 / p0 4 d 3 / an0 3 / p0 3 d 2 / an0 2 / p0 2 d 1 / an0 1 / p0 1 d 0 / an0 0 / p0 0 ki 3 / an3 7 / p10 7 ki 2 / an3 6 / p10 6 ki 1 / an3 5 / p10 5 ki 0 / an3 4 / p10 4 an3 3 / p10 3 an3 2 / p10 2 an3 1 / p10 1 avss an3 0 / p10 0 v ref avcc stxd4 / scl4 / rxd4 / ad trg / p9 7 srxd4 / sda4 / txd4 / anex1 / p9 6 clk4 / anex0 / p9 5 / isrxd2 / ie in / istxd2 / ie out m32c/83 (100p6q-a) note: p7 0 and p7 1 are n-channel open drain output.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 12 table 1.1.7. 100-pin version pin description (1/2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 byte cnv ss x cin /v cont x cout reset x out v ss x in v cc p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 p4 7 p4 6 p4 5 p4 4 nmi int2 int1 int0 tb4 in tb3 in tb2 in tb1 in tb0 in ta4 in /u ta4 out /u ta3 in ta3 out ta2 in /w ta2 out /w ta1 in /v ta1 out /v tb5 in /ta0 in ta0 out txd4/sda4/srxd4 clk4 cts4/rts4/ss4 cts3/rts3/ss3 txd3/sda3/srxd3 rxd3/scl3/stxd3 clk3 can in can out can in can out cts2/rts2/ss2 clk2 rxd2/scl2/stxd2 txd2/sda2/srxd2 txd1/sda1/srxd1 rxd1/scl1/stxd1 clk1 cts1/rts1/ss1 txd0/sda0/srxd0 rxd0/scl0/stxd0 clk0 cts0/rts0/ss0 outc2 0 /ie out ie in outc3 2 outc3 0 inpc0 2 /isrxd0/be0 in inpc0 1 /outc0 1 /isclk0 inpc0 0 /outc0 0 /istxd0/be0 out inpc1 2 /outc1 2 /isrxd1/be1 in inpc1 1 /outc1 1 /isclk1 outc1 0 /istxd1/be1 out outc2 2 /isrxd2/ie in outc2 0 /istxd2/ie out outc2 1 /isclk2 anex1 anex0 da1 da0 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 rdy ale/ras hold hlda/ale clk out /bclk/ale rd/dw wrh/bhe/cash wrl/wr/casl cs0/a 23 cs1/a 22 cs2/a 21 cs3/a 20 (ma 12 ) package pin no fp gp control port timer uart/can intelligent i/o bus control analog interrupt
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 13 table 1.1.8. 100-pin version pin description (2/2) 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 control v cc v ss av ss v ref av cc port p4 3 p4 2 p4 1 p4 0 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p0 1 p0 0 p10 7 p10 6 p10 5 p10 4 p10 3 p10 2 p10 1 p10 0 p9 7 timer uart/can an2 7 an2 6 an2 5 an2 4 an2 3 an2 2 an2 1 an2 0 an0 7 an0 6 an0 5 an0 4 an0 3 an0 2 an0 1 an0 0 an 7 an 6 an 5 an 4 an 3 an 2 an 1 an 0 ad trg a 19 (ma 11 ) a 18 (ma 10 ) a 17 (ma 9 ) a 16 (ma 8 ) a 15 (ma 7 )(/d 15 ) a 14 (ma 6 )(/d 14 ) a 13 (ma 5 )(/d 13 ) a 12 (ma 4 )(/d 12 ) a 11 (ma 3 )(/d 11 ) a 10 (ma 2 )(/d 10 ) a 9 (ma 1 )(/d 9 ) a 8 (ma 0 )(/d 8 ) a 7 (/d 7 ) a 6 (/d 6 ) a 5 (/d 5 ) a 4 (/d 4 ) a 3 (/d 3 ) a 2 (/d 2 ) a 1 (/d 1 ) a 0 (/d 0 ) d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 intelligent i/o bus control analog interrupt int5 int4 int3 ki 3 ki 2 ki 1 ki 0 rxd4/scl4/stxd4 fp gp package pin no
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 14 table 1.1.9. pin description (1/4) function i/o port i/o port i/o port i/o port description an 8-bit cmos i/o port. it has an input/output port direction register that allows the user to set each pin for input or output individually. the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. when set as a separate bus, these pins input and output 8 low-order data bits. this is an 8-bit i/o port equivalent to p0. when set as a separate bus, these pins input and output 8 high-order data bits. this is an 8-bit i/o port equivalent to p0. these pins output 8 low-order address bits. if a multiplexed bus is set, these pins input and output data and output 8 low-order address bits separated in time by multiplexing. this is an 8-bit i/o port equivalent to p0. these pins output 8 middle-order address bits. if the external bus is set as a 16-bit wide multiplexed bus, these pins output 8 middle-order address bits, and input and output 8 middle-order data separated in time by multiplexing. i/o i/o i/o i/o i/o type i/o o i/o i/o o i/o p0 0 to p0 7 d 0 to d 7 p1 0 to p1 7 d 8 to d 15 p2 0 to p2 7 a 0 to a 7 a 0 /d 0 to a 7 /d 7 p3 0 to p3 7 a 8 to a 15 a 8 /d 8 to a 15 /d 15 pin name ma0 to ma7 if accessing to dram area, these pins output row address and column address separated in time by multiplexing. o p0 p1 p2 p3 port data bus data bus address bus address bus/data bus address bus address bus/data bus p1 5 to p1 7 function as external interrupt pins. external interrupt input port i int 3 to int 5 address bus i/o port this is an 8-bit i/o port equivalent to p0. i/o o o p4 0 to p4 7 a 16 to a 22 a 23 chip select ma8 to ma12 o p4 address bus address bus cs 0 to cs 3 p4 0 to p4 7 are chip select output pins to specify access area. these pins output 8 high-order address bits. highest address bit (a 23 ) outputs inversely. if accessing to dram area, these pins output row address and column address separated in time by multiplexing. p0 0 to p0 7 are analog input ports for the a-d converter. i an0 0 to an0 7 analog input port p2 0 to p2 7 are analog input ports for the a-d converter. i an2 0 to an2 7 analog input port v cc v ss cnv ss x in x out byte av cc av ss v ref 4.2 to 5.5 v or 3.0v to 3.6v. 0 v. connect it to v ss : single-chip or memory expansion mode connect it to v cc : microprocessor mode a l on this input resets the microcomputer. these pins are provided for the main clock generating circuit. connect a ceramic resonator or crystal between the x in and the x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. selects the width of the data bus for external memory. connect it to v ss : a 16-bit width connect it to v cc : an 8-bit width connect this pin to v cc . connect this pin to v ss . this pin is a reference voltage input for the a-d converter. i i i o i i power supply input cpu mode switch reset input clock input clock output external data bus width select input analog power supply input reference voltage input reset i i i i
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 15 table 1.1.10. pin description (2/4) function i/o port bus control uart port timer a port description i/o o i/o i/o i/o type i/o o i i/o i/o i i/o o i p5 0 to p5 7 clk out outc/isclk ta out ta in tb in inpc/outc isclk/istxd/ isrxd ie out /ie in be out /be in can pin name v, v w, w o p5 p6 p7 port clock output i/o port intelligent i/o port i/o port timer b port three phase motor control output port bus control for dram p6 0 to p6 7 p7 0 to p7 7 this is an 8-bit i/o port equivalent to p0. p6 0 to p6 3 are i/o ports for uart0. p6 4 to p6 7 are i/o ports for uart1. this is an 8-bit i/o port equivalent to p0. however, p7 0 and p7 1 are n-channel open drain outputs. wrl / wr, wrh / bhe, rd ale, rdy output wrl, wrh and rd, or wr, bhe and rd bus control signals. wrl, wrh, and rd selected in 16-bit data bus, data is written to even addresses when the wrl signal is l . data is written to odd addresses when the wrh signal is l . data is read when rd is l . wr, bhe, and rd selected data is written when wr is l . data is read when rd is l . odd addresses are accessed when bhe is l . even addresses are accessed when bhe is h . use wr, bhe, and rd when all external memory is an 8-bit data bus. output operation clock for cpu. while the input level at the hold pin is l , the microcomputer is placed in the hold state. while in the hold state, hlda outputs a l level. ale is used to latch the address. while the input level of the rdy pin is l , the microcomputer is in the ready state. dw, casl, cash, ras when dw signal is l , write to dram. timing signal when latching to line address of even address. timing signal when latching to line address of odd address. timing signal when latching to row address. p5 3 in this port outputs a divide-by-8 or divide-by-32 clock of x in or a clock of the same frequency as x cin . bclk, hold, hlda o o o i o i o o o o o this is an 8-bit i/o port equivalent to p0. i/o isclk is a clock i/o port for intelligent i/o communication. outc is an output port for waveform generation function. p7 0 to p7 7 are i/o ports for timers a0 C a3. p7 1 is an input port for timer b5. p7 2 and p7 3 are v phase outputs. p7 4 and p7 5 are w phase outputs. p7 0 to p7 3 are i/o ports for uart2. inpc is an input port for time measurement function. outc is an output port for waveform generation function. isclk is a clock i/o port for intelligent i/o communication. istxd/ie out /be out is transmit data output port for intelligent i/o communication. isrxd/ie in /be in is receive data input port for intelligent i/o communication. p7 6 and p7 7 are i/o ports for can communication function. cts/rts/ss clk rxd/scl/stxd txd/sda/srxd uart port cts/rts/ss clk rxd/scl/stxd txd/sda/srxd intelligent i/o port can out can in
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 16 table 1.1.11. pin description (3/4) function i/o port uart port description i/o o i/o i i/o type p8 0 -p8 4 , p8 6 , p8 7 inpc/isrxd/be in pin name p8 p9 port i/o port intelligent i/o port p9 0 to p9 7 this is a 7-bit i/o port equivalent to p0. p9 0 to p9 3 are i/o ports for uart3. p9 4 to p9 7 are i/o ports for uart4. i this is an 8-bit i/o port equivalent to p0. i/o inpc is an input port for time measurement function. isrxd/be in is receive data input port for intelligent i/o communication. cts/rts/ss clk rxd/scl/stxd txd/sda/srxd timer a port three phase motor control output port p8 0 to p8 1 are i/o ports for timer a4. p8 0 and p8 1 are u phase output ports. o i ta4 out ta4 in external interrupt input port p8 2 to p8 4 are external interrupt input ports. i int 0 to int 2 input port p8 5 /nmi input port and input ports for nmi interrupt. i tb0 in to tb4 in timer b port p9 0 to p9 4 are input port for timer b4. o da0, da1 d-a output port p9 3 and p9 4 are d-a output ports. i i anex1, anex2 ad trg a-d related port p9 5 to p9 6 are expanded input port for a-d converter. p9 7 is a-d trigger input port. intelligent i/o port outc is an output port for waveform generation function. ie out is transmit data output port for intelligent i/o communication. ie in is receive data input port for intelligent i/o communication. outc/ie out ie in key input interrupt port i i/o i ki 0 to ki 3 an 0 to an 7 p10 i/o port analog input port p10 0 to p10 7 this is an 8-bit i/o port equivalent to p0. p10 4 to p10 7 are key input interrupt ports. p10 0 to p10 7 are analog input ports for a-d convertor. the protect register prevents a false write to p9 direction register and function select register a3. u, u i/o i i/o i/o i/o x cin x cout p8 6 and p8 7 function as i/o ports for the sub clock generating circuit by software. connect a crystal between the x cin and the x cout pins. i o sub clock input sub clock output v cout when using pll frequency synthesizer, connect p8 7 to a low-pass filter. to stabilize pll frequency, connect p8 6 to vss. o low-pass filter connect pin for pll frequency synthesizer
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 17 table 1.1.12. pin description (4/4) function description i/o type inpc/outc isclk/istxd/ isrxd be out /be in pin name port intelligent i/o port i/o inpc/outc isclk istxd/isrxd be out /be in p11 i/o port p11 0 to p11 4 this is an 5-bit i/o port equivalent to p0. inpc is an input port for time measurement function. outc is an output port for waveform generation function. isclk is a clock i/o port for intelligent i/o communication. istxd/be out is transmit data output port for intelligent i/o communication. isrxd/be in is receive data input port for intelligent i/o communication. intelligent i/o port o i/o outc p12 i/o port p12 0 to p12 7 this is an 8-bit i/o port equivalent to p0. outc is an output port for waveform generation function. intelligent i/o port i/o i/o outc isclk/istxd/ isrxd ie out /ie in p13 i/o port p13 0 to p13 7 this is an 8-bit i/o port equivalent to p0. outc is an output port for waveform generation function. isclk is a clock i/o port for intelligent i/o communication. istxd/ie out is transmit data output port for intelligent i/o communication. isrxd/ie in is receive data input port for intelligent i/o communication. intelligent i/o port i/o i/o inpc/outc p14 i/o port p14 0 to p14 6 this is a 7-bit i/o port equivalent to p0. inpc is an input port for time measurement function. outc is an output port for waveform generation function. intelligent i/o port i/o i/o p15 i/o port p15 0 to p15 7 this is an 8-bit i/o port equivalent to p0. inpc is an input port for time measurement function. outc is an output port for waveform generation function. isclk is a clock i/o port for intelligent i/o communication. istxd/be out is transmit data output port for intelligent i/o communication. isrxd/be in is receive data input port for intelligent i/o communication. i an15 0 to an15 7 analog input port p15 0 to p15 7 are analog input ports for a-d convertor. i/o i/o i/o i/o i/o i/o i/o i/o note :port p11 to p15 exist in 144-pin version. (note) (note) (note) (note) (note)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 18 block diagram the m32c/83 group includes the following devices in a single-chip. rom and ram for code instructions and data, storage, cpu for executing operation and peripheral functions such as timer, serial i/o, d-a converter, dmac, crc operation circuit, a-d converter, dram controller, intelligent i/o and i/o ports. figure 1.1.6 is a block diagram of the m32c/83 group (144-pin version). figure 1.1.6. block diagram of the m32c/83 group (144-pin version) port p0 port p1 port p2 port p3 port p4 port p5 port p6 port p7 port p15 port p14 port p13 port p12 port p11 port p10 port p9 port p8 p8 5 timer (16 bits) input (6) timer b0 timer b1 timer b2 timer b3 timer b4 timer b5 output (5) timer a0 timer a1 timer a2 timer a3 timer a4 three-phase control circuit watchdog timer (15 bits) intelligent i/o group 0 group 1 group 2 group 3 d-a converter (8-bit x 2 circuit) a-d converter (10-bit x 2 circuits) uart/clock synchronous si/o (8-bit x 5 channels) x-y converter (16-bit x 16-bit) crc arithmetic circuit (ccitt) system clock generator x in - x out x cin - x cout ring oscillator memory (note) rom ram internal peripheral functions m32c/80 series cpu core r0h r0l r1h r1l r2 r3 a0 a1 fb sb flg intb isp usp pc svf svp vct dma controller dma ii controller dram controller multiplier i/o ports 88888888 87 885 88 7 can communication function
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description 19 memory figure 1.2.1 is a memory map of the m32c/83 group. the address space extends 16 mbytes from address 000000 16 to ffffff 16 . from ffffff 16 down is rom. for example, in the m30835fjgp, there are 512k bytes of internal rom from f80000 16 to ffffff 16 . the vector table for fixed interrupts such as the reset _______ and nmi are mapped to ffffdc 16 to ffffff 16 . the starting address of the interrupt routine is stored here. the address of the vector table for timer interrupts, etc., can be set as desired using the internal register (intb). see the section on interrupts for details. from 000400 16 up is ram. for example, in the m30835fjgp, 31 kbytes of internal ram are mapped to the space from 000400 16 to 007fff 16 . in addition to storing data, the ram also stores the stack used when calling subroutines and when interrupts are generated. the sfr area is mapped from 000000 16 to 0003ff 16 . this area accommodates the control registers for peripheral devices such as i/o ports, a-d converter, serial i/o, and timers, etc. any part of the sfr area that is not occupied is reserved and cannot be used for any other purpose. the special page vector table is mapped from fffe00 16 to ffffdb 16 . if the starting addresses of subrou- tines or the destination addresses of jumps are stored here, subroutine call instructions and jump instruc- tions can be used as 2-byte instructions, reducing the number of program steps. in memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be used. figure 1.2.1. memory map 000000 16 yyyyyy 16 ffffff 16 000400 16 008000 16 xxxxxx 16 f00000 16 aaaaa a aaa a a aaa a aaaaa external area internal rom area internal ram area internal reserved area (note 1) internal reserved area (note 2) fffe00 16 ffffdc 16 ffffff 16 note 1: during memory expansion and microprocessor modes, can not be used. note 2: in memory expansion mode, can not be used. undefined instruction overflow brk instruction address match watchdog timer reset special page vector table nmi sfr area address xxxxx 16 f80000 16 007fff 16 m30835f/mj type no. address yyyyy 16 m30833f/mj
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer software reset 20 central processing unit (cpu) the cpu has a total of 28 registers shown in figure 1.3.1. eight of these registers (r0, r1, r2, r3, a0, a1, sb and fb) come in two sets; therefore, these have two register banks. figure 1.3.1. central processing unit register b23 b7 b0 flag register address register (note) static base register (note) frame base register (note) user stack pointer interrupt stack pointer interrupt table register flag save register pc save register vector register dma mode register dma transfer count register dma transfer count reload register dma memory address register dma sfr address register dma memory address reload register b15 b0 b15 b0 b23 b15 b23 data register (note) flg r0h r1h r2 r3 a0 a1 sb fb usp isp intb pc svf vct dmd0 dmd1 dct0 dct1 drc0 drc1 dma0 dma1 dsa0 dsa1 dra0 dra1 svp dmac related register program counter r2 r3 high-speed interrupt register general register b31 r0l r1l note: these registers have two register banks.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 21 processor mode (1) data registers (r0, r0h, r0l, r1, r1h, r1l, r2, r3, r2r0 and r3r1) data registers (r0, r1, r2, and r3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. registers r0 and r1 each can be used as separate 8-bit data registers, high-order bits as (r0h/r1h), and low-order bits as (r0l/r1l). registers r2 and r0, as well as r3 and r1 can function as 32-bit data registers (r2r0/r3r1). (2) address registers (a0 and a1) address registers (a0 and a1) are configured with 24 bits, and have functions equivalent to those of data registers. these registers can also function as address register, indirect addressing and address register relative addressing. (3) static base register (sb) static base register (sb) is configured with 24 bits, and is used for sb relative addressing. (4) frame base register (fb) frame base register (fb) is configured with 24 bits, and is used for fb relative addressing. (5) program counter (pc) program counter (pc) is configured with 24 bits, indicating the address of an instruction to be executed. (6) interrupt table register (intb) interrupt table register (intb) is configured with 24 bits, indicating the start address of an interrupt vector table. (7) user stack pointer (usp), interrupt stack pointer (isp) stack pointer comes in two types: user stack pointer (usp) and interrupt stack pointer (isp), each config- ured with 24 bits. the desired type of stack pointer (usp or isp) can be selected by a stack pointer select flag (u flag). this flag is located at bit 7 in the flag register (flg). to execute efficienly set usp and isp to an even number. (8) save flag register (svf) this register consists of 16 bits and is used to save the flag register when a high-speed interrupt is generated. (9) save pc register (svp) this register consists of 24 bits and is used to save the program counter when a high-speed interrupt is generated. this register consist of 24 bits and is used to indicate a jump address when a high-speed interrupt is generated.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 22 processor mode (10) vector register (vct) this register consists of 24 bits and is used to indicate the jump address when a high-speed interrupt is generated. (11) dma mode registers (dmd0/dmd1) these registers consist of 8 bits and are used to set the transfer mode, etc. for dma. (12) dma transfer count registers (dct0/dct1) these registers consist of 16 bits and are used to set the number of dma transfers performed. (13) dma transfer count reload registers (drc0/drc1) these registers consist of 16 bits and are used to reload the dma transfer count registers. (14) dma memory address registers (dma0/dma1) these registers consist of 24 bits and are used to set a memory address at the source or destination of dma transfer. (15) dma sfr address registers (dsa0/dsa1) these registers consist of 24 bits and are used to set a fixed address at the source or destination of dma transfer. (16) dma memory address reload registers (dra0/dra1) these registers consist of 24 bits and are used to reload the dma memory address registers. (17) flag register (flg) flag register (flg) is configured with 11 bits, each bit is used as a flag. figure 1.3.2 shows the flag register (flg). the following explains the function of each flag: ?bit 0: carry flag (c) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. ?bit 1: debug flag (d) this flag enables a single-step interrupt. when this flag is 1 , a single-step interrupt is generated after instruction execution. this flag is cleared to 0 when the interrupt is acknowledged. ?bit 2: zero flag (z) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, cleared to 0 . ?bit 3: sign flag (s) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, cleared to 0 .
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 23 processor mode processor mode bit 4: register bank select flag (b) this flag chooses a register bank. register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1 . bit 5: overflow flag (o) this flag is set to 1 when an arithmetic operation resulted in overflow; otherwise, cleared to 0 . bit 6: interrupt enable flag (i) this flag enables a maskable interrupt. an interrupt is disabled when this flag is 0 , and is enabled when this flag is 1 . this flag is cleared to 0 when the interrupt is acknowledged. bit 7: stack pointer select flag (u) interrupt stack pointer (isp) is selected when this flag is 0 ; user stack pointer (usp) is selected when this flag is 1 . this flag is cleared to 0 when a hardware interrupt is acknowledged or an int instruction of software interrupt numbers. 0 to 31 is executed. bits 8 to 11: reserved area bits 12 to 14: processor interrupt priority level (ipl) processor interrupt priority level (ipl) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than the processor interrupt priority level (ipl), the interrupt is enabled. bit 15: reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level reserved area flag register (flg) aa aa aa aa aa aa a a aaaaaaa aaaaaaa aa aa aa aa a a aa aa aa aa c d z s b o i u ipl b0 b15 figure 1.3.2. flag register (flg)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer reset 24 reset there are two kinds of resets; hardware and software. in both cases, operation is the same after the reset. (see software reset for details of software resets.) this section explains hardware resets. when the supply voltage is in the range where operation is guaranteed, a reset is enabled by holding the reset pin low (0.2v cc max.) for at least 20 cycles. when the reset pin level is then returned to high while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. since the value of ram is indeterminate when power is applied, the initial values must be set. also, if a reset signal is input during write to ram, the access to the ram will be interrupted. consequently, the value of the ram being written may change to an unintended value due to the interruption. figure 1.4.1 shows the example reset circuit. figure 1.4.2 shows the reset sequence. ____________ table 1.4.1 shows the status of other pins while the reset pin level is low. figures 1.4.3 and 1.4.4 show the internal status of the microcomputer immediately after the reset is cancelled. reset v cc 0.8v reset v cc 0v 0v 5v 5v 4.2v example when v cc = 5v . figure 1.4.1. example reset circuit
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer reset 25 bclk x in reset rd wr cs0 rd wr cs0 address address address microprocessor mode byte = h microprocessor mode byte = l content of reset vector single chip mode bclk 24cycles ffffc 16 ffffd 16 ffffe 16 content of reset vector ffffe 16 content of reset vector ffffe 16 ffffc 16 more than 20 cycles are needed ffffc 16 figure 1.4.2. reset sequence
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer reset 26 status cnv ss = v cc cnv ss = v ss byte = v ss byte = v cc pin name p0 p1 p2, p3, p4 p5 0 p5 1 p5 2 p5 3 p5 4 p5 5 p5 6 p5 7 input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) data input (floating) data input (floating) address output (undefined) bclk output ras output wr output ( h level output) rd output ( h level output) rdy input (floating) input port (floating) bhe output (undefined) hlda output (the output value depends on the input to the hold pin) hold input (floating) input port (floating) p6 to p15 (note) ____________ table 1.4.1. pin status when reset pin level is l note :port p11 to p15 exists in 144-pin version.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer reset 27 (006b 16 ) (006c 16 ) (006d 16 ) (006e 16 ) (006f 16 ) (0070 16 ) (0071 16 ) (0072 16 ) (0073 16 ) (0074 16 ) (0075 16 ) (0076 16 ) (0077 16 ) (0078 16 ) (0079 16 ) (007a 16 ) (007b 16 ) (007c 16 ) (007d 16 ) (007e 16 ) (007f 16 ) (0081 16 ) (0086 16 ) (0088 16 ) (0089 16 ) (008a 16 ) (008b 16 ) (008c 16 ) (008d 16 ) (008e 16 ) (008f 16 ) (0090 16 ) (0091 16 ) (0004 16 ) (0005 16 ) (0006 16 ) (0007 16 ) (0008 16 ) (0009 16 ) (000a 16 ) (000b 16 ) (000c 16 ) (000d 16 ) (000e 16 ) (000f 16 ) (0010 16 ) (0011 16 ) (0012 16 ) (0014 16 ) (0015 16 ) (0016 16 ) (0017 16 ) (0018 16 ) (0019 16 ) (001a 16 ) (001b 16 ) (001c 16 ) (001d 16 ) (001e 16 ) (001f 16 ) (0040 16 ) (0041 16 ) (0057 16 ) (0068 16 ) (0069 16 ) (006a 16 ) processor mode register 0 processor mode register 1 system clock control register 0 system clock control register 1 wait control register address match interrupt control register protect register external data bus width control register main clock divided register oscillation stop detect register watchdog timer start register watchdog timer control register address match interrupt register 0 address match interrupt register 1 vdc control register for pll address match interrupt register 2 vdd control register 1 address match interrupt register 3 vdd control register 1 dram control register dram refresh interval set register flash memory control register 0 dma0 interrupt control register timer b5 interrupt control register dma2 interrupt control register (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (47) (48) (49) (50) (51) (52) (53) (54) (55) (56) (57) (58) 80 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ?? 16 uart2 receive /ack interrupt control register timer a0 interrupt control register uart3 receive/ack interrupt control register timer a2 interrupt control register uart4 receive/ack interrupt control register timer a4 interrupt control register uart0 receive/ack interrupt control register a-d0 interrupt control register uart1 receive/ack interrupt control register intelligent i/o interrupt control register 0 timer b1 interrupt control register intelligent i/o interrupt control register 2 timer b3 interrupt control register intelligent i/o interrupt control register 4 int5 interrupt control register intelligent i/o interrupt control register 6 int3 interrupt control register intelligent i/o interrupt control register 8 int1 interrupt control register a - d1 interrupt control register dm a1 interrupt control register uart2 transmit /nack interrupt control register dma3 interrupt control register uart3 transmit /nack interrupt control register timer a1 interrupt control register uart4 transmit /nack interrupt control register timer a3 interrupt control register uart2 bus collision detection interrupt control register uart0 transmit /nack interrupt control register 20 16 ff 16 xxxx 0000 x00000xx 0000x000 xxxx 0000 xxxxx000 xxx01000 ?? 16 000????? 00 16 00 16 00 16 ?xxx ???? xxxxxx01 xxxx ?000 xx00 0001 xxxx ?000 xxxx ?000 uart0/uart3 bus collision detection interrupt control register xxxx?000 xxxx?0 0 0 xxxx?0 0 0 xxxx?0 0 0 xxxx?0 0 0 xxxx?0 0 0 xxxx?000 xxxx ?000 xxxx ?000 xxxx ?000 xxxx ?000 xxxx ?000 xxxx ?000 xxxx?000 xxxx?000 xxxx?000 xxxx?000 xxxx?000 xxxx?000 xxxx?000 xxxx?000 xx00?0 0 0 xx00?0 0 0 xx00?0 0 0 xxxx ?000 xxxx ?000 xxxx ?000 xxxx ?000 xxxx ?000 xxxx ?000 xxxx ?000 uart1/uart4 bus collision detection interrupt control register xxxx ?000 x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. note 1: when the v cc level is applied to the cnv ss pin, it is 03 16 at a reset. note 2: when the byte pin is "l", bit 3 is "1". when the byte pin is "h", bit 3 is "0". (note 1) (note 2) 00 16 00 16 xxxx ?000 intelligent i/o interrupt control register 10/ can interrupt 1 control register intelligent i/o interrupt control register 11/ can interrupt 2 control register figure 1.4.3. device's internal status after a reset is cleared (1/10)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer reset 28 (00b7 16 ) (00b8 16 ) (00b9 16 ) (00ba 16 ) (00bb 16 ) (00c0 16 ) (00c1 16 ) (00c2 16 ) (00c3 16 ) (00c4 16 ) (00c5 16 ) (00c6 16 ) (00c7 16 ) (00c8 16 ) (00c9 16 ) (00ca 16 ) (00cb 16 ) (00cc 16 ) (00cd 16 ) (00ce 16 ) (00cf 16 ) (00d0 16 ) (00d1 16 ) (00d4 16 ) (00d5 16 ) (00d8 16 ) (00d9 16 ) (00da 16 ) (00db 16 ) (00dc 16 ) (00dd 16 ) (00de 16 ) (00df 16 ) (0092 16 ) (0093 16 ) (0094 16 ) (0095 16 ) (0096 16 ) (0097 16 ) (0098 16 ) (0099 16 ) (009a 16 ) (009b 16 ) (009c 16 ) (009d 16 ) (009e 16 ) (009f 16 ) (00a0 16 ) (00a1 16 ) (00a2 16 ) (00a3 16 ) (00a4 16 ) (00a5 16 ) (00a6 16 ) (00a7 16 ) (00a8 16 ) (00a9 16 ) (00aa 16 ) (00ab 16 ) (00b0 16 ) (00b1 16 ) (00b2 16 ) (00b3 16 ) (00b4 16 ) (00b5 16 ) (00b6 16 ) uart1 transmit/nack interrupt control register key input interrupt control register timer b0 interrupt control register intelligent i/o interrupt control register 1 timer b2 interrupt control register intelligent i/o interrupt control register 3 timer b4 interrupt control register intelligent i/o interrupt control register 5 int4 interrupt control register intelligent i/o interrupt control register 7 int2 interrupt control register int0 interrupt control register exit priority register interrupt request register 0 interrupt request register 1 interrupt request register 2 interrupt request register 3 interrupt request register 4 interrupt request register 5 interrupt request register 6 interrupt request register 7 interrupt request register 8 interrupt request register 9 interrupt request register 10 interrupt request register 11 interrupt enable register 0 interrupt enable register 1 interrupt enable register 2 interrupt enable register 3 interrupt enable register 4 interrupt enable register 5 interrupt enable register 6 (59) (60) (61) (62) (63) (64) (65) (66) (67) (68) (69) (70) (71) (72) (73) (74) (75) (76) (77) (78) (79) (80) (81) (82) (83) (84) (85) (86) (87) (88) (89) (90) (91) (92) (93) (94) (95) (96) (97) (98) (99) (100) (101) (102) (103) (104) (105) (106) (107) (108) (109) (110) (111) (112) (113) (114) (115) (116) interrupt enable register 7 interrupt enable register 8 interrupt enable register 9 interrupt enable register 10 interrupt enable register 11 group 0 time measurement/waveform generate register 0 group 0 time measurement/waveform generate register 1 group 0 time measurement/waveform generate register 2 group 0 time measurement/waveform generate register 3 group 0 time measurement/waveform generate register 4 group 0 time measurement/waveform generate register 5 group 0 time measurement/waveform generate register 6 group 0 time measurement/waveform generate register 7 group 0 waveform generate control register 0 group 0 waveform generate control register 1 group 0 waveform generate control register 4 group 0 waveform generate control register 5 group 0 time measurement control register 0 group 0 time measurement control register 1 group 0 time measurement control register 2 group 0 time measurement control register 3 group 0 time measurement control register 4 group 0 time measurement control register 5 group 0 time measurement control register 6 group 0 time measurement control register 7 xxxx ?000 xxxx ?000 xx00?000 xx00?000 xxxx ?000 xxxx ?000 xxxx ?000 xxxx ?000 xxxx ?000 xxxx ?000 xxxx ?000 xxxx ?000 xx00?000 xx0x0000 0x00x000 0xx00000 00x00000 0xxx0000 0xxx0000 0xx00000 0x00x000 0x00x000 0x00x000 00 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. xx00x00x xx00000x 00x0000x xxx0000x 00x0000x xx00x00x xx00x0xx xxx0000x 0xx0000x 0xx0000x 0xx0000x 0xx0000x xx00x000 xx00x000 xx00x0x0 xx000000 00x00000 xxx00000 xxx00000 intelligent i/o interrupt control register 9/ can interrupt 0 control register figure 1.4.3. device's internal status after a reset is cleared (2/10)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer reset 29 (0104 16 ) (0105 16 ) (0106 16 ) (0107 16 ) (0108 16 ) (0109 16 ) (010a 16 ) (010b 16 ) (010c 16 ) (010d 16 ) (010e 16 ) (010f 16 ) (0110 16 ) (0111 16 ) (0112 16 ) (0113 16 ) (0114 16 ) (0115 16 ) (0116 16 ) (0117 16 ) (0119 16 ) (011a 16 ) (011e 16 ) (011f 16 ) (0120 16 ) (0121 16 ) (0122 16 ) (0123 16 ) (00e0 16 ) (00e1 16 ) (00e2 16 ) (00e3 16 ) (00e4 16 ) (00e5 16 ) (00e6 16 ) (00e7 16 ) (00e8 16 ) (00e9 16 ) (00ea 16 ) (00ec 16 ) (00ed 16 ) (00ee 16 ) (00ef 16 ) (00f0 16 ) (00f1 16 ) (00f2 16 ) (00f3 16 ) (00f4 16 ) (00f5 16 ) (00f8 16 ) (00f9 16 ) (00fa 16 ) (00fb 16 ) (00fc 16 ) (00fd 16 ) (00fe 16 ) (00ff 16 ) (0100 16 ) (0101 16 ) (0102 16 ) (0103 16 ) group 0 base timer register group 0 base timer control register 0 group 0 base timer control register 1 group 0 time measurement prescaler register 6 group 0 time measurement prescaler register 7 group 0 function enable register group 0 function select register group 0 si/o receive buffer register group 0 transmit buffer/receive data register group 0 receive input register group 0 si/o communication mode register group 0 transmit output register group 0 si/o communication control register group 0 data compare register 0 group 0 data compare register 1 group 0 data compare register 2 group 0 data compare register 3 group 0 data mask register 0 group 0 data mask register 1 group 0 receive crc code register group 0 transmit crc code register group 0 si/o expansion mode register group 0 si/o expansion receive control register group 0 si/o special communication interrupt detect register group 0 si/o expansion transmit control register group 1 time measurement/waveform generate register 0 group 1 time measurement/waveform generate register 1 (117) (118) (119) (120) (121) (122) (123) (124) (125) (126) (127) (128) (129) (130) (131) (132) (133) (134) (135) (136) (137) (138) (139) (140) (141) (142) (143) (144) (145) (146) (147) (148) (149) (150) (151) (152) (153) (154) (155) (156) (157) (158) (159) (160) (161) (162) (163) (164) group 1 time measurement/waveform generate register 2 group 1 time measurement/waveform generate register 3 group 1 time measurement/waveform generate register 4 group 1 time measurement/waveform generate register 5 group 1 time measurement/waveform generate register 6 group 1 time measurement/waveform generate register 7 group 1 waveform generate control register 0 group 1 waveform generate control register 1 group 1 waveform generate control register 2 group 1 waveform generate control register 3 group 1 waveform generate control register 4 group 1 waveform generate control register 5 group 1 waveform generate control register 6 group 1 waveform generate control register 7 group 1 time measurement control register 1 group 1 time measurement control register 2 group 1 time measurement control register 6 group 1 time measurement control register 7 group 1 base timer register group 1 base timer control register 0 group 1 base timer control register 1 x000xxxx 0000x011 000000xx 00000xxx 0x00x000 0x00x000 0x00x000 0x00x000 0x00x000 0x00x000 0x00x000 0x00x000 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ?? 16 ?? 16 00 16 00 16 00 16 00 16 00 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 00 16 00 16 00 16 ?? 16 00 16 00 16 ?? 16 ?? 16 x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. figure 1.4.3. device's internal status after a reset is cleared (3/10)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer reset 30 (0148 16 ) (0149 16 ) (014a 16 ) (014b 16 ) (014c 16 ) (014d 16 ) (014e 16 ) (014f 16 ) (0150 16 ) (0151 16 ) (0152 16 ) (0153 16 ) (0154 16 ) (0155 16 ) (0156 16 ) (0157 16 ) (0160 16 ) (0161 16 ) (0162 16 ) (0163 16 ) (0164 16 ) (0166 16 ) (0167 16 ) (016a 16 ) (016b 16 ) (016c 16 ) (016d 16 ) (016e 16 ) (016f 16 ) (0170 16 ) (0171 16 ) (0172 16 ) (0124 16 ) (0125 16 ) (0126 16 ) (0127 16 ) (0128 16 ) (0129 16 ) (012a 16 ) (012c 16 ) (012d 16 ) (012e 16 ) (012f 16 ) (0130 16 ) (0131 16 ) (0132 16 ) (0133 16 ) (0134 16 ) (0135 16 ) (0138 16 ) (0139 16 ) (013a 16 ) (013b 16 ) (013c 16 ) (013d 16 ) (013e 16 ) (013f 16 ) (0140 16 ) (0141 16 ) (0142 16 ) (0143 16 ) (0144 16 ) (0145 16 ) (0146 16 ) (0147 16 ) group 1 time measurement prescaler register 6 group 1 time measurement prescaler register 7 group 1 function enable register group 1 function select register group 1 si/o receive buffer register group 1 transmit buffer/receive data register group 1 receive input register group 1 si/o communication mode register group 1 transmit output register group 1 si/o communication control register group 1 data compare register 0 group 1 data compare register 1 group 1 data compare register 2 group 1 data compare register 3 group 1 data mask register 0 group 1 data mask register 1 group 1 receive crc code register group 1 transmit crc code register group 1 si/o expansion mode register group 1 si/o expansion receive control register group 1 si/o special communication interrupt detect register group 1 si/o expansion transmit control register group 2 waveform generate register 0 group 2 waveform generate register 1 group 2 waveform generate register 2 group 2 waveform generate register 3 (165) (166) (167) (168) (169) (170) (171) (172) (173) (174) (175) (176) (177) (178) (179) (180) (181) (182) (183) (184) (185) (186) (187) (188) (189) (190) (191) (192) (193) (194) (195) (196) (197) (198) (199) (200) (201) (202) (203) (204) (205) (206) (207) (208) (209) (210) (211) (212) (213) (214) group 2 waveform generate register 4 group 2 waveform generate register 5 group 2 waveform generate register 6 group 2 waveform generate register 7 group 2 waveform generate control register 0 group 2 waveform generate control register 1 group 2 waveform generate control register 2 group 2 waveform generate control register 3 group 2 waveform generate control register 4 group 2 waveform generate control register 5 group 2 waveform generate control register 6 group 2 waveform generate control register 7 group 2 base timer register group 2 base timer control register 0 group 2 base timer control register 1 base timer start register group 2 function enable register group 2 rtp output buffer register group 2 si/o communication mode register group 2 si/o communication control register group 2 si/o transmit buffer register group 2 si/o receive buffer register group 2 iebus address register group 2 iebus control register x000xxxx 0000x011 00xxx000 0000x110 ???xx??? xxx?xxxx xxxx???? xxxx0000 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ?? 16 ?? 16 00 16 00 16 00 16 00 16 ?? 16 ?? 16 ?? 16 00 16 00 16 ?? 16 ?? 16 ?? 16 00 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 00 16 00 16 00 16 00 16 ?? 16 ?? 16 00 16 00 16 00xxx000 x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 000000xx 00000xxx figure 1.4.3. device's internal status after a reset is cleared (4/10)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer reset 31 (0198 16 ) (0199 16 ) (019a 16 ) (019b 16 ) (019c 16 ) (019d 16 ) (019e 16 ) (019f 16 ) (01a0 16 ) (01a1 16 ) (01a2 16 ) (01a3 16 ) (01a6 16 ) (01a7 16 ) (01ab 16 ) (01ac 16 ) (01ad 16 ) (01ae 16 ) (01af 16 ) (01b0 16 ) (01b1 16 ) (01b2 16 ) (01b3 16 ) (01b4 16 ) (01b5 16 ) (01b6 16 ) (01b7 16 ) (01b8 16 ) (01b9 16 ) (01ba 16 ) (01bb 16 ) (01bc 16 ) (01bd 16 ) (0173 16 ) (0174 16 ) (0178 16 ) (017a 16 ) (017b 16 ) (017c 16 ) (017d 16 ) (017e 16 ) (017f 16 ) (0180 16 ) (0181 16 ) (0182 16 ) (0183 16 ) (0184 16 ) (0185 16 ) (0186 16 ) (0187 16 ) (0188 16 ) (0189 16 ) (018a 16 ) (018b 16 ) (018c 16 ) (018d 16 ) (018e 16 ) (018f 16 ) (0190 16 ) (0191 16 ) (0192 16 ) (0193 16 ) (0194 16 ) (0195 16 ) (0196 16 ) (0197 16 ) input function select register group 3 si/o communication mode register group 3 si/o communication control register group 3 si/o transmit buffer register group 3 si/o receive buffer register group 3 waveform generate register 0 group 3 waveform generate register 1 group 3 waveform generate register 2 group 3 waveform generate register 3 group 3 waveform generate register 4 group 3 waveform generate register 5 group 3 waveform generate register 6 group 3 waveform generate register 7 group 3 waveform generate control register 0 group 3 waveform generate control register 1 group 3 waveform generate control register 2 group 3 waveform generate control register 3 group 3 waveform generate control register 4 group 3 waveform generate control register 5 group 3 waveform generate control register 6 group 3 waveform generate control register 7 (215) (216) (217) (218) (219) (220) (221) (222) (223) (224) (225) (226) (227) (228) (229) (230) (231) (232) (233) (234) (235) (236) (237) (238) (239) (240) (241) (242) (243) (244) (245) (246) (247) (248) (249) (250) (251) (252) (253) (254) (255) (256) (257) group 3 waveform generate mask register 4 group 3 waveform generate mask register 5 group 3 waveform generate mask register 6 group 3 waveform generate mask register 7 group 3 base timer register group 3 base timer control register 0 group 3 base timer control register 1 group 3 function enable register group 3 rtp output buffer register group 3 high-speed hdlc communication control register 1 group 3 high-speed hdlc communication control register group 3 high-speed hdlc communication register group 3 high-speed hdlc transmit counter group 3 high-speed hdlc data compare register 0 group 3 high-speed hdlc data mask register 0 group 3 high-speed hdlc data compare register 1 group 3 high-speed hdlc data mask register 1 group 3 high-speed hdlc data compare register 2 group 3 high-speed hdlc data mask register 2 group 3 high-speed hdlc data compare register 3 xxx00000 xxx00000 00?0x??0 00xx0000 0xx0x000 group 2 iebus transmit interrupt cause detect register group 2 iebus receive interrupt cause detect register 00 16 00 16 00 16 00 16 00 16 00 16 ?? 16 ?? 16 00 16 00 16 00 16 00 16 ?? 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ?? 16 ?? 16 ?? 16 ?? 16 00 16 x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. 00xxxxx0 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 figure 1.4.3. device's internal status after a reset is cleared (5/10)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer reset 32 (01ec 16 ) (01ed 16 ) (01ee 16 ) (01ef 16 ) (01f0 16 ) (01f1 16 ) (01f2 16 ) (01f3 16 ) (01f4 16 ) (01f5 16 ) (01f6 16 ) (01f7 16 ) (01f8 16 ) (01f9 16 ) (01fa 16 ) (01fb 16 ) (01fc 16 ) (01fd 16 ) (01fe 16 ) (01ff 16 ) (0200 16 ) (0201 16 ) (0202 16 ) (0203 16 ) (0204 16 ) (0205 16 ) (0206 16 ) (0207 16 ) (0208 16 ) (0209 16 ) (020a 16 ) (020b 16 ) (01be 16 ) (01bf 16 ) (01c0 16 ) (01c1 16 ) (01c2 16 ) (01c3 16 ) (01c4 16 ) (01c5 16 ) (01c6 16 ) (01c7 16 ) (01c8 16 ) (01c9 16 ) (01ca 16 ) (01cb 16 ) (01cc 16 ) (01cd 16 ) (01ce 16 ) (01cf 16 ) (01d4 16 ) (01d6 16 ) (01d7 16 ) (01e0 16 ) (01e1 16 ) (01e2 16 ) (01e3 16 ) (01e4 16 ) (01e5 16 ) (01e6 16 ) (01e7 16 ) (01e8 16 ) (01e9 16 ) (01ea 16 ) (01eb 16 ) group 3 high-speed hdlc data mask register 3 a-d1 register 0 a-d1 register 1 a-d1 register 2 a-d1 register 3 a-d1 register 4 a-d1 register 5 a-d1 register 6 a-d1 register 7 a-d1 control register 2 a-d1 control register 0 a-d1 control register 1 can0 message slot buffer 0 standard id 0 can0 message slot buffer 0 standard id 1 can0 message slot buffer 0 extended id 0 can0 message slot buffer 0 extended id 1 can0 message slot buffer 0 extended id 2 can0 message slot buffer 0 data length code can0 message slot buffer 0 data 0 can0 message slot buffer 0 data 1 can0 message slot buffer 0 data 2 can0 message slot buffer 0 data 3 can0 message slot buffer 0 data 4 can0 message slot buffer 0 data 5 (258) (259) (260) (261) (262) (263) (264) (265) (266) (267) (268) (269) (270) (271) (272) (273) (274) (275) (276) (277) (278) (279) (280) (281) (282) (283) (284) (285) (286) (287) (288) (289) (290) (291) (292) (293) (294) (295) (296) (297) (298) (299) (300) (301) (302) (303) (304) (305) (306) (307) (308) can0 message slot buffer 0 data 6 can0 message slot buffer 0 data 7 can0 message slot buffer 0 time stamp high can0 message slot buffer 0 time stamp low can1 message slot buffer 0 standard id 0 can1 message slot buffer 0 standard id 1 can1 message slot buffer 0 extended id 0 can1 message slot buffer 0 extended id 1 can1 message slot buffer 0 extended id 2 can1 message slot buffer 0 data length code can1 message slot buffer 0 data 0 can1 message slot buffer 0 data 1 can1 message slot buffer 0 data 2 can1 message slot buffer 0 data 3 can1 message slot buffer 0 data 4 can1 message slot buffer 0 data 5 can1 message slot buffer 0 data 6 can1 message slot buffer 0 data 7 can1 message slot buffer 0 time stamp high can1 message slot buffer 0 time stamp low can0 control register 0 can0 status register can0 expansion id register can0 configuration register can0 time stamp register can0 transmit error count register can0 receive error count register xxxx0 0 0 0 0000xxxx x00xx000 xx000000 x0000x01 xx 0 1 0x0 1 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 00 16 ?? 16 ?? 16 00 16 ?? 16 x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) xxx????? xx?????? xxxx???? xx?????? xxxx???? xxx????? xx?????? xxxx???? xx?????? xxxx???? figure 1.4.3. device's internal status after a reset is cleared (6/10)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer reset 33 (02c0 16 ) (02c1 16 ) (02c2 16 ) (02c3 16 ) (02c4 16 ) (02c5 16 ) (02c6 16 ) (02c7 16 ) (02c8 16 ) (02c9 16 ) (02ca 16 ) (02cb 16 ) (02cc 16 ) (02cd 16 ) (02ce 16 ) (02cf 16 ) (02d0 16 ) (02d1 16 ) (02d2 16 ) (02d3 16 ) (02d4 16 ) (02d5 16 ) (02d6 16 ) (02d7 16 ) (02d8 16 ) (02d9 16 ) (02da 16 ) (02db 16 ) (02dc 16 ) (02dd 16 ) (02de 16 ) (02df 16 ) (02e0 16 ) (020c 16 ) (020d 16 ) (0210 16 ) (0211 16 ) (0214 16 ) (0215 16 ) (0217 16 ) (0228 16 ) (0229 16 ) (022a 16 ) (022b 16 ) (022c 16 ) (0230 16 ) (0231 16 ) (0232 16 ) (0233 16 ) (0234 16 ) (0235 16 ) (0236 16 ) (0237 16 ) (0238 16 ) (0239 16 ) (023a 16 ) (023b 16 ) (023c 16 ) (023d 16 ) (023e 16 ) (023f 16 ) (0240 16 ) (0241 16 ) (0242 16 ) (0244 16 ) (0245 16 ) can0 slot interrupt status register can0 slot interrupt mask register can0 error interrupt mask register can0 error interrupt status register can0 baud rate prescaler can0 global mask register standard id0 can0 global mask register standard id1 can0 global mask register extended id0 can0 global mask register extended id1 can0 global mask register extended id2 can0 message slot 5 control register can0 message slot 6 control register can0 message slot 7 control register can0 message slot 13 control register can0 message slot 14 control register can0 message slot 15 control register can0 slot buffer select register can0 control register 1 can0 sleep control register can0 acceptance filter support register (309) (310) (311) (312) (313) (314) (315) (316) (317) (318) (319) (320) (321) (322) (323) (324) (325) (326) (327) (328) (329) (330) (331) (332) (333) (334) (335) (336) (337) (338) (339) (340) (341) (342) (343) (344) (345) (346) (347) (348) (349) (350) (351) (352) (353) (354) (355) x0 register/y0 register x1 register/y1 register x2 register/y2 register x3 register/y3 register x4 register/y4 register x5 register/y5 register x6 register/y6 register x7 register/y7 register x8 register/y8 register x9 register/y9 register x10 register/y10 register x11 register/y11 register x12 register/y12 register x13 register/y13 register x14 register/y14 register x15 register/y15 register xy control register xxxxx0 00 xxxxx0 00 xxxxxxx0 xxxxxx0 0 can0 message slot 0 control register / can0 local mask register a standard id0 can0 message slot 8 control register / can0 local mask register b standard id0 can0 message slot 9 control register / can0 local mask register b standard id1 can0 message slot 10 control register / can0 local mask register b extended id0 can0 message slot 11 control register / can0 local mask register b extended id1 can0 message slot 12 control register / can0 local mask register b extended id2 can0 message slot 1 control register / can0 local mask register a standard id1 can0 message slot 3 control register / can0 local mask register a extended id1 can0 message slot 2 control register / can0 local mask register a extended id0 can0 message slot 4 control register / can0 local mask register a extended id2 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 00 16 00 16 01 16 00 16 01 16 00 16 00 16 xx0000xx ?? 16 ?? 16 ?? 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 xxx00000 xx000000 xxx00000 xx000000 00 16 xxx00000 xx000000 x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) figure 1.4.3. device's internal status after a reset is cleared (7/10)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer reset 34 (030a 16 ) (030b 16 ) (030c 16 ) (030d 16 ) (0310 16 ) (0311 16 ) (0312 16 ) (0313 16 ) (0314 16 ) (0315 16 ) (031b 16 ) (031c 16 ) (031d 16 ) (031f 16 ) (0324 16 ) (0325 16 ) (0326 16 ) (0327 16 ) (0328 16 ) (0329 16 ) (032a 16 ) (032b 16 ) (032c 16 ) (032d 16 ) (032e 16 ) (032f 16 ) (0334 16 ) (0335 16 ) (0336 16 ) (0337 16 ) (0338 16 ) (0339 16 ) (02e4 16 ) (02e5 16 ) (02e6 16 ) (02e7 16 ) (02e8 16 ) (02e9 16 ) (02ea 16 ) (02eb 16 ) (02ec 16 ) (02ed 16 ) (02ee 16 ) (02ef 16 ) (02f4 16 ) (02f5 16 ) (02f6 16 ) (02f7 16 ) (02f8 16 ) (02f9 16 ) (02fa 16 ) (02fb 16 ) (02fc 16 ) (02fd 16 ) (02fe 16 ) (02ff 16 ) (0300 16 ) (0302 16 ) (0303 16 ) (0304 16 ) (0305 16 ) (0306 16 ) (0307 16 ) (0308 16 ) (0309 16 ) uart1 special mode register 4 uart1 special mode register 3 uart1 special mode register 2 uart1 special mode register uart1 transmit-receive mode register uart1 bit rate generator uart1 transmit buffer register uart1 transmit-receive control register 0 uart1 transmit-receive control register 1 uart1 receive buffer register uart4 special mode register 4 uart4 special mode register 3 uart4 special mode register 2 uart4 special mode register uart4 transmit-receive mode register uart4 bit rate generator uart4 transmit buffer register uart4 transmit-receive control register 0 uart4 transmit-receive control register 1 uart4 receive buffer register timer b3,b4,b5 count start flag timer a1-1 register timer a2-1 register timer a4-1 register three-phase pwm control register 0 three-phase pwm control register 1 (356) (357) (358) (359) (360) (361) (362) (363) (364) (365) (366) (367) (368) (369) (370) (371) (372) (373) (374) (375) (376) (377) (378) (379) (380) (381) (382) (383) (384) (385) (386) (387) (388) (389) (390) (391) (392) (393) (394) (395) (396) (397) (398) (399) (400) (401) (402) (403) (404) (405) (406) (407) (408) three-phase output buffer register 0 three-phase output buffer register 1 dead time timer timer b2 interrupt occurrence frequency set counter timer b3 register timer b4 register timer b5 register timer b3 mode register timer b4 mode register timer b5 mode register external interrupt cause select register uart3 special mode register 4 uart3 special mode register 3 uart3 special mode register 2 uart3 special mode register uart3 transmit-receive mode register uart3 bit rate generator uart3 transmit buffer register uart3 transmit-receive control register 0 uart3 transmit-receive control register 1 uart3 receive buffer register uart2 special mode register 4 uart2 special mode register 3 uart2 special mode register 2 uart2 special mode register uart2 transmit-receive mode register uart2 bit rate generator xxxxxxx? xxxxxxx? xx000000 xx000000 xxxx???? 00?x0000 ?????xx? ?????xx? 000xxxxx 00?x0000 00?00000 xxxxxxx? ?????xx? 08 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 00 16 00 16 00 16 00 16 00 16 00 16 ?? 16 ?? 16 02 16 ?? 16 00 16 00 16 00 16 00 16 00 16 ?? 16 00 16 00 16 00 16 ?? 16 08 16 ?? 16 02 16 ?? 16 00 16 00 16 00 16 ?? 16 ?? 16 08 16 02 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 00 16 00 16 00 16 00 16 00 16 00 16 x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. figure 1.4.3. device's internal status after a reset is cleared (8/10)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer reset 35 (035c 16 ) (035d 16 ) (035e 16 ) (035f 16 ) (0364 16 ) (0365 16 ) (0366 16 ) (0367 16 ) (0368 16 ) (0369 16 ) (036a 16 ) (036b 16 ) (036c 16 ) (036d 16 ) (036e 16 ) (036f 16 ) (0376 16 ) (0378 16 ) (0379 16 ) (037a 16 ) (037b 16 ) (037c 16 ) (037d 16 ) (037e 16 ) (0380 16 ) (0381 16 ) (0382 16 ) (0383 16 ) (0384 16 ) (0385 16 ) (0386 16 ) (0387 16 ) (033a 16 ) (033b 16 ) (033c 16 ) (033d 16 ) (033e 16 ) (033f 16 ) (0340 16 ) (0341 16 ) (0342 16 ) (0343 16 ) (0344 16 ) (0346 16 ) (0347 16 ) (0348 16 ) (0349 16 ) (034a 16 ) (034b 16 ) (034c 16 ) (034d 16 ) (034e 16 ) (034f 16 ) (0350 16 ) (0351 16 ) (0352 16 ) (0353 16 ) (0354 16 ) (0355 16 ) (0356 16 ) (0357 16 ) (0358 16 ) (0359 16 ) (035a 16 ) (035b 16 ) uart2 transmit buffer register uart2 transmit/receive control register 0 uart2 transmit/receive control register 1 uart2 receive buffer register count start flag clock prescaler reset flag one-shot start flag trigger select register up-down flag timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register (409) (410) (411) (412) (413) (414) (415) (416) (417) (418) (419) (420) (421) (422) (423) (424) (425) (426) (427) (428) (429) (430) (431) (432) (433) (434) (435) (436) (437) (438) (439) (440) (441) (442) (443) (444) (445) (446) (447) (448) (449) (450) (451) (452) (453) (454) (455) (456) timer b1 mode register timer b2 mode register timer b2 special mode register count source prescaler register uart0 pecial mode register 4 uart0 special mode register 3 uart0 special mode register 2 uart0 special mode register uart0 transmit/receive mode register uart0 bit rate generator uart0 transmit buffer register uart0 transmit/receive control register 0 uart0 transmit/receive control register 1 uart0 receive buffer register pll control register 0 dma0 cause select register dma1 cause select register dma2 cause select register dma3 cause select register crc data register crc input register a-d0 register 0 a-d0 register 1 a-d0 register 2 a-d0 register 3 0xxxxxxx xxxxxxx? ?????xx? 00?x0000 00?x0000 0xxx0000 xxxxxxx0 00000x00 00000x00 00000x00 00000x00 00000x00 00?00000 xxxxxxx? ?????xx? 00110100 0x000000 0x000000 0x000000 0x000000 ?? 16 ?? 16 00 16 00 16 00 16 00 16 00 16 ?? 16 ?? 16 02 16 08 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 02 16 ?? 16 00 16 00 16 00 16 00 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 08 16 x : nothing is mapped to this bit ? : undefined the content of other registers and ram are undefined when the microcomputer is reset. the initial values must therefore be set. figure 1.4.3. device's internal status after a reset is cleared (9/10)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer reset 36 (03c5 16 ) (03c6 16 ) (03c7 16 ) (03c8 16 ) (03c9 16 ) (03ca 16 ) (03cb 16 ) (03cc 16 ) (03cd 16 ) (03ce 16 ) (03cf 16 ) (03d0 16 ) (03d1 16 ) (03d2 16 ) (03d3 16 ) (03da 16 ) (03db 16 ) (03dc 16 ) (03e0 16 ) (03e1 16 ) (03e2 16 ) (03e3 16 ) (03e4 16 ) (03e5 16 ) (03e6 16 ) (03e7 16 ) (03e8 16 ) (03e9 16 ) (03ea 16 ) (03eb 16 ) (03f0 16 ) (03f1 16 ) (03ff 16 ) (0388 16 ) (0389 16 ) (038a 16 ) (038b 16 ) (038c 16 ) (038d 16 ) (038e 16 ) (038f 16 ) (0394 16 ) (0396 16 ) (0397 16 ) (0398 16 ) (039a 16 ) (039c 16 ) (03a0 16 ) (03a1 16 ) (03af 16 ) (03b0 16 ) (03b1 16 ) (03b2 16 ) (03b3 16 ) (03b4 16 ) (03b5 16 ) (03b6 16 ) (03b7 16 ) (03b9 16 ) (03bc 16 ) (03bd 16 ) (03c0 16 ) (03c1 16 ) (03c2 16 ) (03c3 16 ) (03c4 16 ) a-d0 register 4 a-d0 register 5 a-d0 register 6 a-d0 register 7 a-d0 control register 2 a-d0 control register 0 a-d0 control register 1 d-a register 0 d-a register 1 d-a control register function select register a8 function select register a9 function select register c function select register a0 function select register a1 function select register b0 function select register b1 function select register a2 function select register a3 function select register b2 function select register b3 function select register a5 function select register a6 function select register a7 port p6 port p7 port p6 direction register port p7 direction register port p8 (457) (458) (459) (460) (461) (462) (463) (464) (465) (466) (467) (468) (469) (470) (471) (472) (473) (474) (475) (476) (477) (478) (479) (480) (481) (482) (483) (484) (485) (486) (487) (488) (489) (490) (491) (492) (493) (494) (495) (496) (497) (498) (499) (500) (501) (502) (503) (504) (505) (506) (507) (508) (509) (510) (511) (512) (513) (514) (515) (516) (517) (518) port p9 port p8 direction register port p9 direction register port p10 port p11 port p10 direction register port p11 direction register port p12 port p13 port p12 direction register port p13 direction register port p14 port p15 port p14 direction register port p15 direction register pull-up control register 2 pull-up control register 3 pull-up control register 4 port p0 port p1 port p0 direction register port p1 direction register port p2 port p3 port p2 direction register port p3 direction register port p4 port p5 port p4 direction register port p5 direction register pull-up control register 0 pull-up control register 1 port control register x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. note :this register exists in 144-pin version. x0000000 xxxxxx0 0 xxxx0 0 00 00x00000 xxxxx0 0 0 00x00000 xxx????? xxx00000 xxxxx0 0 0 xxxx0 0 0 0 x??????? x0000000 xxxx0 0 0 0 xxxx0 0 0 0 xxxxxxx0 ?? 16 00 16 ?? 16 ?? 16 00 16 ?? 16 ?? 16 00 16 00 16 ?? 16 00 16 00 16 00 16 ?? 16 ?? 16 00 16 ?? 16 00 16 00 16 ?? 16 ?? 16 00 16 00 16 00 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 ?? 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ?? 16 ?? 16 00 16 00 16 ?? 16 ?? 16 ?? 16 ?? 16 (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) 00 16 00 16 00 16 00 16 00 16 figure 1.4.3. device's internal status after a reset is cleared (10/10)
sfr under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 37 sfr address register 0000 16 0001 16 0002 16 0003 16 0004 16 processor mode register 0 pm0 0005 16 processor mode register 1 pm1 0006 16 system clock control register 0 cm0 0007 16 system clock control register 1 cm1 0008 16 wait control register wcr 0009 16 address match interrupt control register aier 000a 16 protect register prcr 000b 16 external data bus width control register ds 000c 16 main clock divided register mcd 000d 16 oscillation stop detect register cm2 000e 16 watchdog timer start register wdts 000f 16 watchdog timer control register wdc 0010 16 0011 16 address match interrupt register 0 rmad0 0012 16 0013 16 0014 16 0015 16 address match interrupt register 1 ramd1 0016 16 0017 16 vdc control register for pll plv 0018 16 0019 16 address match interrupt register 2 ramd2 001a 16 001b 16 vdc control register 1 vdc1 * 001c 16 001d 16 address match interrupt register 3 ramd3 001e 16 001f 16 vdc control register 0 vdc0 * 0020 16 0021 16 emulator interrupt vector table register eiad0 * 0022 16 0023 16 emulator interrupt detect register eitd * 0024 16 emulator protect register eprr * 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 address register 0030 16 rom area set register roa * 0031 16 debug moritor area set register dba * 0032 16 expansion area set register 0 exa0 * 0033 16 expansion area set register 1 exa1 * 0034 16 expansion area set register 2 exa2 * 0035 16 expansion area set register 3 exa3 * 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0040 16 dram control register dramcont 0041 16 dram refresh interval set register refcnt 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 flash memory control register 2 fmr2 * 0056 16 flash memory control register 1 fmr1 * 0057 16 flash memory control register 0 fmr0 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 the blank area is reserved and cannot be used by user. *: user cannot use this. do not access to the register.
sfr under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 38 address register 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 dma0 interrupt control register dm0ic 0069 16 timer b5 interrupt control register tb5ic 006a 16 dma2 interrupt control register dm2ic 006b 16 uart2 receive /ack interrupt control register s2ric 006c 16 timer a0 interrupt control register ta0ic 006d 16 uart3 receive /ack interrupt control register s3ric 006e 16 timer a2 interrupt control register ta2ic 006f 16 uart4 receive /ack interrupt control register s4ric 0070 16 timer a4 interrupt control register ta4ic 0071 16 uart0/uart3 bus collision detection interrupt control register bcn0ic 0072 16 uart0 receive/ack interrupt control register s0ric 0073 16 a-d0 interrupt control register ad0ic 0074 16 uart1 receive/ack interrupt control register s1ric 0075 16 intelligent i/o interrupt control register 0 iio0ic 0076 16 timer b1 interrupt control register tb1ic 0077 16 intelligent i/o interrupt control register 2 iio2ic 0078 16 timer b3 interrupt control register tb3ic 0079 16 intelligent i/o interrupt control register 4 iio4ic 007a 16 int5 interrupt control register int5ic 007b 16 intelligent i/o interrupt control register 6 iio6ic 007c 16 int3 interrupt control register int3ic 007d 16 intelligent i/o interrupt control register 8 iio8ic 007e 16 int1 interrupt control register int1ic 007f 16 intelligent i/o interrupt control register 10/ iio10ic can interrupt 1 control register can1ici 0080 16 0081 16 intelligent i/o interrupt control register 11/ iio11ic can interrupt 2 control register can2ic 0082 16 0083 16 0084 16 0085 16 0086 16 a-d1 interrupt control register ad1ic 0087 16 0088 16 dma1 interrupt control register dm1ic 0089 16 uart2 transmit /nack interrupt control register s2tic 008a 16 dma3 interrupt control register dm3ic 008b 16 uart3 transmit /nack interrupt control register s3tic 008c 16 timer a1 interrupt control register ta1ic 008d 16 uart4 transmit /nack interrupt control register s4tic 008e 16 timer a3 interrupt control register ta3ic 008f 16 uart2 bus collision detection interrupt control register bcn2ic address register 0090 16 uart0 transmit /nack interrupt control register s0tic 0091 16 uart1/uart4 bus collision detection interrupt control register bcn1ic 0092 16 uart1 transmit/nack interruptcontrol register s1tic 0093 16 key input interrupt control register kupic 0094 16 timer b0 interrupt control register tb0ic 0095 16 intelligent i/o interrupt control register 1 iio1ic 0096 16 timer b2 interrupt control register tb2ic 0097 16 intelligent i/o interrupt control register 3 iio3ic 0098 16 timer b4 interrupt control register tb4ic 0099 16 intelligent i/o interrupt control register 5 iio5ic 009a 16 int4 interrupt control register int4ic 009b 16 intelligent i/o interrupt control register 7 iio7ic 009c 16 int2 interrupt control register int2ic 009d 16 intelligent i/o interrupt control register 9/ iio9ic can interrupt 0 control register can0ici 009e 16 int0 interrupt control register int0ic 009f 16 exit priority register rlvl 00a0 16 interrupt request register 0 iio0ir 00a1 16 interrupt request register 1 iio1ir 00a2 16 interrupt request register 2 iio2ir 00a3 16 interrupt request register 3 iio3ir 00a4 16 interrupt request register 4 iio4ir 00a5 16 interrupt request register 5 iio5ir 00a6 16 interrupt request register 6 iio6ir 00a7 16 interrupt request register 7 iio7ir 00a8 16 interrupt request register 8 iio8ir 00a9 16 interrupt request register 9 iio9ir 00aa 16 interrupt request register 10 iio10ir 00ab 16 interrupt request register 11 iio11ir 00ac 16 00ad 16 00ae 16 00af 16 00b0 16 interrupt enable register 0 iio0ie 00b1 16 interrupt enable register 1 iio1ie 00b2 16 interrupt enable register 2 iio2ie 00b3 16 interrupt enable register 3 iio3ie 00b4 16 interrupt enable register 4 iio4ie 00b5 16 interrupt enable register 5 iio5ie 00b6 16 interrupt enable register 6 iio6ie 00b7 16 interrupt enable register 7 iio7ie 00b8 16 interrupt enable register 8 iio8ie 00b9 16 interrupt enable register 9 iio9ie 00ba 16 interrupt enable register 10 iio10ie 00bb 16 interrupt enable register 11 iio11ie 00bc 16 00bd 16 00be 16 00bf 16 the blank area is reserved and cannot be used by user.
sfr under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 39 address register 00c0 16 group 0 tm /wg register 0 g0tm0/g0po0 00c1 16 00c2 16 group 0 tm /wg register 1 g0tm1/g0po1 00c3 16 00c4 16 group 0 tm /wg register 2 g0tm2/g0po2 00c5 16 00c6 16 group 0 tm /wg register 3 g0tm3/g0po3 00c7 16 00c8 16 group 0 tm /wg register 4 g0tm4/g0po4 00c9 16 00ca 16 group 0 tm /wg register 5 g0tm5/g0po5 00cb 16 00cc 16 group 0 tm /wg register 6 g0tm6/g0po6 00cd 16 00ce 16 group 0 tm /wg register 7 g0tm7/g0po7 00cf 16 00d0 16 group 0 waveform generate control register 0 g0pocr0 00d1 16 group 0 waveform generate control register 1 g0pocr1 00d2 16 00d3 16 00d4 16 group 0 waveform generate control register 4 g0pocr4 00d5 16 group 0 waveform generate control register 5 g0pocr5 00d6 16 00d7 16 00d8 16 group 0 time measurement control register 0 g0tmcr0 00d9 16 group 0 time measurement control register 1 g0tmcr1 00da 16 group 0 time measurement control register 2 g0tmcr2 00db 16 group 0 time measurement control register 3 g0tmcr3 00dc 16 group 0 time measurement control register 4 g0tmcr4 00dd 16 group 0 time measurement control register 5 g0tmcr5 00de 16 group 0 time measurement control register 6 g0tmcr6 00df 16 group 0 time measurement control register 7 g0tmcr7 00e0 16 group 0 base timer register g0bt 00e1 16 00e2 16 group 0 base timer control register 0 g0bcr0 00e3 16 group 0 base timer control register 1 g0bcr1 00e4 16 group 0 time measurement prescaler register 6 g0tpr6 00e5 16 group 0 time measurement prescaler register 7 g0tpr7 00e6 16 group 0 function enable register g0fe 00e7 16 group 0 function select register g0fs 00e8 16 group 0 si/o receive buffer register g0bf 00e9 16 00ea 16 group 0 transmit buffer/receive data register g0dr 00eb 16 00ec 16 group 0 receive input register g0ri 00ed 16 group 0 si/o communication mode register g0mr 00ee 16 group 0 transmit output register g0to 00ef 16 group 0 si/o communication control register g0cr address register 00f0 16 group 0 data compare register 0 g0cmp0 00f1 16 group 0 data compare register 1 g0cmp1 00f2 16 group 0 data compare register 2 g0cmp2 00f3 16 group 0 data compare register 3 g0cmp3 00f4 16 group 0 data mask register 0 g0msk0 00f5 16 group 0 data mask register 1 g0msk1 00f6 16 00f7 16 00f8 16 group 0 receive crc code register g0rcrc 00f9 16 00fa 16 group 0 transmit crc code register g0tcrc 00fb 16 00fc 16 group 0 si/o expansion mode register g0emr 00fd 16 group 0 si/o expansion receive control register g0erc 00fe 16 group 0 si/o special communication interrupt detect register g0irf 00ff 16 group 0 si/o expansion transmit control register g0etc 0100 16 group 1 tm /wg register 0 g1tm0/g1po0 0101 16 0102 16 group 1 tm /wg register 1 g1tm1/g1po1 0103 16 0104 16 group 1 tm /wg register 2 g1tm2/g1po2 0105 16 0106 16 group 1 tm /wg register 3 g1tm3/g1po3 0107 16 0108 16 group 1 tm /wg register 4 g1tm4/g1po4 0109 16 010a 16 group 1 tm /wg register 5 g1tm5/g1po5 010b 16 010c 16 group 1 tm /wg register 6 g1tm6/g1po6 010d 16 010e 16 group 1 tm /wg register 7 g1tm7/g1po7 010f 16 0110 16 group 1 waveform generate control register 0 g1pocr0 0111 16 group 1 waveform generate control register 1 g1pocr1 0112 16 group 1 waveform generate control register 2 g1pocr2 0113 16 group 1 waveform generate control register 3 g1pocr3 0114 16 group 1 waveform generate control register 4 g1pocr4 0115 16 group 1 waveform generate control register 5 g1pocr5 0116 16 group 1 waveform generate control register 6 g1pocr6 0117 16 group 1 waveform generate control register 7 g1pocr7 0118 16 0119 16 group 1 time measurement control register 1 g1tmcr1 011a 16 group 1 time measurement control register 2 g1tmcr2 011b 16 011c 16 011d 16 011e 16 group 1 time measurement control register 6 g1tmcr6 011f 16 group 1 time measurement control register 7 g1tmcr7 the blank area is reserved and cannot be used by user.
sfr under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 40 address register 0120 16 group 1 base timer register g1bt 0121 16 0122 16 group 1 base timer control register 0 g1bcr0 0123 16 group 1 base timer control register 1 g1bcr1 0124 16 group 1 time measurement prescaler register 6 g1tpr6 0125 16 group 1 time measurement prescaler register 7 g1tpr7 0126 16 group 1 function enable register g1fe 0127 16 group 1 function select register g1fs 0128 16 group 1 si/o receive buffer register g1bf 0129 16 012a 16 group 1 transmit buffer/receive data register g1dr 012b 16 012c 16 group 1 receive input register g1ri 012d 16 group 1 si/o communication mode register g1mr 012e 16 group 1 transmit output register g1to 012f 16 group 1 si/o communication control register g1cr 0130 16 group 1 data compare register 0 g1cmp0 0131 16 group 1 data compare register 1 g1cmp1 0132 16 group 1 data compare register 2 g1cmp2 0133 16 group 1 data compare register 3 g1cmp3 0134 16 group 1 data mask register 0 g1msk0 0135 16 group 1 data mask register 1 g1msk1 0136 16 0137 16 0138 16 group 1 receive crc code register g1rcrc 0139 16 013a 16 group 1 transmit crc code register g1tcrc 013b 16 013c 16 group 1 si/o expansion mode register g1emr 013d 16 group 1 si/o expansion receive control register g1erc 013e 16 group 1 si/o special communication interrupt detect register g1irf 013f 16 group 1 si/o expansion transmit control register g1etc 0140 16 group 2 waveform generate register 0 g2po0 0141 16 0142 16 group 2 waveform generate register 1 g2po1 0143 16 0144 16 group 2 waveform generate register 2 g2po2 0145 16 0146 16 group 2 waveform generate register 3 g2po3 0147 16 0148 16 group 2 waveform generate register 4 g2po4 0149 16 014a 16 group 2 waveform generate register 5 g2po5 014b 16 014c 16 group 2 waveform generate register 6 g2po6 014d 16 014e 16 group 2 waveform generate register 7 g2po7 014f 16 address register 0150 16 group 2 waveform generate control register 0 g2pocr0 0151 16 group 2 waveform generate control register 1 g2pocr1 0152 16 group 2 waveform generate control register 2 g2pocr2 0153 16 group 2 waveform generate control register 3 g2pocr3 0154 16 group 2 waveform generate control register 4 g2pocr4 0155 16 group 2 waveform generate control register 5 g2pocr5 0156 16 group 2 waveform generate control register 6 g2pocr6 0157 16 group 2 waveform generate control register 7 g2pocr7 0158 16 0159 16 015a 16 015b 16 015c 16 015d 16 015e 16 015f 16 0160 16 group 2 base timer register g2bt 0161 16 0162 16 group 2 base timer control register 0 g2bcr0 0163 16 group 2 base timer control register 1 g2bcr1 0164 16 base timer start register btsr 0165 16 0166 16 group 2 function enable register g2fe 0167 16 group 2 rtp output buffer register g2rtp 0168 16 0169 16 016a 16 group 2 si/o communication mode register g2mr 016b 16 group 2 si/o communication control register g2cr 016c 16 group 2 si/o transmit buffer register g2tb 016d 16 016e 16 group 2 si/o receive buffer register g2rb 016f 16 0170 16 group 2 iebus address register iear 0171 16 0172 16 group 2 iebus control register iecr 0173 16 group 2 iebus transmit interrupt cause detect register ietif 0174 16 group 2 iebus receive interrupt cause detect register ierif 0175 16 0176 16 0177 16 0178 16 input function select register ips 0179 16 017a 16 group 3 si/o communication mode register g3mr 017b 16 group 3 si/o communication control register g3cr 017c 16 group 3 si/o transmit buffer register g3tb 017d 16 017e 16 group 3 si/o receive buffer register g3rb 017f 16 the blank area is reserved and cannot be used by user.
sfr under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 41 address register 0180 16 group 3 waveform generate register 0 g3po0 0181 16 0182 16 group 3 waveform generate register 1 g3po1 0183 16 0184 16 group 3 waveform generate register 2 g3po2 0185 16 0186 16 group 3 waveform generate register 3 g3po3 0187 16 0188 16 group 3 waveform generate register 4 g3po4 0189 16 018a 16 group 3 waveform generate register 5 g3po5 018b 16 018c 16 group 3 waveform generate register 6 g3po6 018d 16 018e 16 group 3 waveform generate register 7 g3po7 018f 16 0190 16 group 3 waveform generate control register 0 g3pocr0 0191 16 group 3 waveform generate control register 1 g3pocr1 0192 16 group 3 waveform generate control register 2 g3pocr2 0193 16 group 3 waveform generate control register 3 g3pocr3 0194 16 group 3 waveform generate control register 4 g3pocr4 0195 16 group 3 waveform generate control register 5 g3pocr5 0196 16 group 3 waveform generate control register 6 g3pocr6 0197 16 group 3 waveform generate control register 7 g3pocr7 0198 16 group 3 waveform generate mask register 4 g3mk4 0199 16 019a 16 group 3 waveform generate mask register 5 g3mk5 019b 16 019c 16 group 3 waveform generate mask register 6 g3mk6 019d 16 019e 16 group 3 waveform generate mask register 7 g3mk7 019f 16 01a0 16 group 3 base timer register g3bt 01a1 16 01a2 16 group 3 base timer control register 0 g3bcr0 01a3 16 group 3 base timer control register 1 g3bcr1 01a4 16 01a5 16 01a6 16 group 3 function enable register g3fe 01a7 16 group 3 rtp output buffer register g3rtp 01a8 16 01a9 16 01aa 16 01ab 16 group 3 high-speed hdlc communication control register 1 hdlc1 01ac 16 group 3 high-speed hdlc communication control register hdlc 01ad 16 group 3 high-speed hdlc communication register hdlcf 01ae 16 group 3 high-speed hdlc transmit counter hdlcc 01af 16 address register 01b0 16 group 3 high-speed hdlc data compare register 0 hdlccp0 01b1 16 01b2 16 group 3 high-speed hdlc data mask register 0 hdlcmk0 01b3 16 01b4 16 group 3 high-speed hdlc data compare register1 hdlccp1 01b5 16 01b6 16 group 3 high-speed hdlc data mask register 1 hdlcmk1 01b7 16 01b8 16 group 3 high-speed hdlc data compare register 2 hdlccp2 01b9 16 01ba 16 group 3 high-speed hdlc data mask register 2 hdlcmk2 01bb 16 01bc 16 group 3 high-speed hdlc data compare register 3 hdlccp3 01bd 16 01be 16 group 3 high-speed hdlc data mask register 3 hdlcmk3 01bf 16 01c0 16 a-d1 register 0 ad10 01c1 16 01c2 16 a-d1 register 1 ad11 01c3 16 01c4 16 a-d1 register 2 ad12 01c5 16 01c6 16 a-d1 register 3 ad13 01c7 16 01c8 16 a-d1 register 4 ad14 01c9 16 01ca 16 a-d1 register 5 ad15 01cb 16 01cc 16 a-d1 register 6 ad16 01cd 16 01ce 16 a-d1 register 7 ad17 01cf 16 01d0 16 01d1 16 01d2 16 01d3 16 01d4 16 a-d1 control register 2 ad1con2 01d5 16 01d6 16 a-d1 control register 0 ad1con0 01d7 16 a-d1 control register 1 ad1con1 01d8 16 01d9 16 01da 16 01db 16 01dc 16 01dd 16 01de 16 01df 16 the blank area is reserved and cannot be used by user.
sfr under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 42 address register 01e0 16 can0 message slot buffer 0 standard id0 c0slot0_0 01e1 16 can0 message slot buffer 0 standard id1 c0slot0_1 01e2 16 can0 message slot buffer 0 extend id0 c0slot0_2 01e3 16 can0 message slot buffer 0 extend id1 c0slot0_3 01e4 16 can0 message slot buffer 0 extend id2 c0slot0_4 01e5 16 can0 message slot buffer 0 data length code c0slot0_5 01e6 16 can0 message slot buffer 0 data 0 c0slot0_6 01e7 16 can0 message slot buffer 0 data 1 c0slot0_7 01e8 16 can0 message slot buffer 0 data 2 c0slot0_8 01e9 16 can0 message slot buffer 0 data 3 c0slot0_9 01ea 16 can0 message slot buffer 0 data 4 c0slot0_10 01eb 16 can0 message slot buffer 0 data 5 c0slot0_11 01ec 16 can0 message slot buffer 0 data 6 c0slot0_12 01ed 16 can0 message slot buffer 0 data 7 c0slot0_13 01ee 16 can0 message slot buffer 0 time stamp highc0slot0_14 01ef 16 can0 message slot buffer 0 time stamp low c0slot0_15 01f0 16 can0 message slot buffer 1 standard id0 c0slot1_0 01f1 16 can0 message slot buffer 1 standard id1 c0slot1_1 01f2 16 can0 message slot buffer 1 extend id0 c0slot1_2 01f3 16 can0 message slot buffer 1 extend id1 c0slot1_3 01f4 16 can0 message slot buffer 1 extend id2 c0slot1_4 01f5 16 can0 message slot buffer 1 data length code c0slot1_5 01f6 16 can0 message slot buffer 1 data 0 c0slot1_6 01f7 16 can0 message slot buffer 1 data 1 c0slot1_7 01f8 16 can0 message slot buffer 1 data 2 c0slot1_8 01f9 16 can0 message slot buffer 1 data 3 c0slot1_9 01fa 16 can0 message slot buffer 1 data 4 c0slot1_10 01fb 16 can0 message slot buffer 1 data 5 c0slot1_11 01fc 16 can0 message slot buffer 1 data 6 c0slot1_12 01fd 16 can0 message slot buffer 1 data 7 c0slot1_13 01fe 16 can0 message slot buffer 1 time stamp highc0slot1_14 01ff 16 can0 message slot buffer 1 time stamp low c0slot1_15 0200 16 can0 control register 0 c0ctlr0 0201 16 0202 16 can0 status register c0str 0203 16 0204 16 can0 expansion id register c0idr 0205 16 0206 16 can0 configuration register c0conr 0207 16 0208 16 can0 time stamp register c0tsr 0209 16 020a 16 can0 transmit error count register c0tec 020b 16 can0 receive error count register c0rec 020c 16 can0 slot interrupt status register c0sistr 020d 16 020e 16 020f 16 address register 0210 16 can0 slot interrupt mask register c0simkr 0211 16 0212 16 0213 16 0214 16 can0 error interrupt mask register c0eimkr 0215 16 can0 error interrupt status register c0eistr 0216 16 0217 16 can0 baud rate prescaler c0bpr 0218 16 0219 16 021a 16 021b 16 021c 16 021d 16 021e 16 021f 16 0220 16 0221 16 0222 16 0223 16 0224 16 0225 16 0226 16 0227 16 0228 16 can0 global mask register standard id0 c0gmr0 0229 16 can0 global mask register standard id1 c0gmr1 022a 16 can0 global mask register extend id0 c0gmr2 022b 16 can0 global mask register extend id1 c0gmr3 022c 16 can0 global mask register extend id2 c0gmr4 022d 16 022e 16 022f 16 0230 16 can0 message slot 0 control register / c0mctl0/ can0 local mask register a standard id0 c0lmar0 0231 16 can0 message slot 1 control register / c0mctl1/ can0 local mask register a standard id1 c0lmar1 0232 16 can0 message slot 2 control register / c0mctl2/ can0 local mask register a extend id0 c0lmar2 0233 16 can0 message slot 3 control register / c0mctl3/ can0 local mask register a extend id1 c0lmar3 0234 16 can0 message slot 4 control register / c0mctl4/ can0 local mask register a extend id2 c0lmar4 0235 16 can0 message slot 5 control register c0mctl5 0236 16 can0 message slot 6 control register c0mctl6 0237 16 can0 message slot 7 control register c0mctl7 0238 16 can0 message slot 8 control register / c0mctl8/ can0 local mask register b standard id0 c0lmbr0 the blank area is reserved and cannot be used by user. note 1: can0 message slot i control registers (i=0 to 15) are allocated to addresses 0230 16 to 023f 16 by switching banks.
sfr under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 43 address register 0239 16 can0 message slot 9 control register / c0mctl9/ can0 local mask register b standard id1 c0lmbr1 023a 16 can0 message slot 10 control register / c0mctl10/ can0 local mask register b extend id0 c0lmbr2 023b 16 can0 message slot 11 control register / c0mctl11/ can0 local mask register b extend id1 c0lmbr3 023c 16 can0 message slot 12 control register / c0mctl12/ can0 local mask register b extend id2 c0lmbr4 023d 16 can0 message slot 13 control register c0mctl13 023e 16 can0 message slot 14 control register c0mctl14 023f 16 can0 message slot 15 control register c0mctl15 0240 16 can0 slot buffer select register c0sbs 0241 16 can0 control register 1 c0ctlr1 0242 16 can0 sleep control register c0slpr 0243 16 0244 16 can0 acceptance filter support register c0afs 0245 16 address register 02c0 16 x0 register/y0 register x0r/y0r 02c1 16 02c2 16 x1 register/y1 register x1r/y1r 02c3 16 02c4 16 x2 register/y2 register x2r/y2r 02c5 16 02c6 16 x3 register/y3 register x3r/y3r 02c7 16 02c8 16 x4 register/y4 register x4r/y4r 02c9 16 02ca 16 x5 register/y5 register x5r/y5r 02cb 16 02cc 16 x6 register/y6 register x6r/y6r 02cd 16 02ce 16 x7 register/y7 register x7r/y7r 02cf 16 02d0 16 x8 register/y8 register x8r/y8r 02d1 16 02d2 16 x9 register/y9 register x9r/y9r 02d3 16 02d4 16 x10 register/y10 register x10r/y10r 02d5 16 02d6 16 x11 register/y11 register x11r/y11r 02d7 16 02d8 16 x12 register/y12 register x12r/y12r 02d9 16 02da 16 x13 register/y13 register x13r/y13r 02db 16 02dc 16 x14 register/y14 register x14r/y14r 02dd 16 02de 16 x15 register/y15 register x15r/y15r 02df 16 02e0 16 xy control register xyc 02e1 16 02e2 16 02e3 16 02e4 16 uart1 special mode register 4 u1smr4 02e5 16 uart1 special mode register 3 u1smr3 02e6 16 uart1 special mode register 2 u1smr2 02e7 16 uart1 special mode register u1smr 02e8 16 uart1 transmit-receive mode register u1mr 02e9 16 uart1 bit rate generator u1brg 02ea 16 uart1 transmit buffer register u1tb 02eb 16 02ec 16 uart1 transmit-receive control register 0 u1c0 02ed 16 uart1 transmit-receive control register 1 u1c1 02ee 16 uart1 receive buffer register u1rb 02ef 16 the blank area is reserved and cannot be used by user.
sfr under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 44 address register 02f0 16 02f1 16 02f2 16 02f3 16 02f4 16 uart4 special mode register 4 u4smr4 02f5 16 uart4 special mode register 3 u4smr3 02f6 16 uart4 special mode register 2 u4smr2 02f7 16 uart4 special mode register u4smr 02f8 16 uart4 transmit-receive mode register u4mr 02f9 16 uart4 bit rate generator u4brg 02fa 16 uart4 transmit buffer register u4tb 02fb 16 02fc 16 uart4 transmit-receive control register 0 u4c0 02fd 16 uart4 transmit-receive control register 1 u4c1 02fe 16 uart4 receive buffer register u4rb 02ff 16 0300 16 timer b3,b4,b5 count start flag tbsr 0301 16 0302 16 timer a1-1 register ta11 0303 16 0304 16 timer a2-1 register ta21 0305 16 0306 16 timer a4-1 register ta41 0307 16 0308 16 three-phase pwm control register 0 invc0 0309 16 three-phase pwm control register 1 invc1 030a 16 three-phase output buffer register 0 idb0 030b 16 three-phase output buffer register 1 idb1 030c 16 dead time timer dtt 030d 16 timer b2 interrupt occurrence frequency set counter ictb2 030e 16 030f 16 0310 16 timer b3 register tb3 0311 16 0312 16 timer b4 register tb4 0313 16 0314 16 timer b5 register tb5 0315 16 0316 16 0317 16 0318 16 0319 16 031a 16 031b 16 timer b3 mode register tb3mr 031c 16 timer b4 mode register tb4mr 031d 16 timer b5 mode register tb5mr 031e 16 031f 16 external interrupt cause select register ifsr address register 0320 16 0321 16 0322 16 0323 16 0324 16 uart3 special mode register 4 u3smr4 0325 16 uart3 special mode register 3 u3smr3 0326 16 uart3 special mode register 2 u3smr2 0327 16 uart3 special mode register u3smr 0328 16 uart3 transmit-receive mode register u3mr 0329 16 uart3 bit rate generator u3brg 032a 16 uart3 transmit buffer register u3tb 032b 16 032c 16 uart3 transmit-receive control register 0 u3c0 032d 16 uart3 transmit-receive control register 1 u3c1 032e 16 uart3 receive buffer register u3rb 032f 16 0330 16 0331 16 0332 16 0333 16 0334 16 uart2 special mode register 4 u2smr4 0335 16 uart2 special mode register 3 u2smr3 0336 16 uart2 special mode register 2 u2smr2 0337 16 uart2 special mode register u2smr 0338 16 uart2 transmit-receive mode register u2mr 0339 16 uart2 bit rate generator u2brg 033a 16 uart2 transmit buffer register u2tb 033b 16 033c 16 uart2 transmit/receive control register 0 u2c0 033d 16 uart2 transmit/receive control register 1 u2c1 033e 16 uart2 receive buffer register u2rb 033f 16 0340 16 count start flag tabsr 0341 16 clock prescaler reset flag cpsrf 0342 16 one-shot start flag onsf 0343 16 trigger select register trgsr 0344 16 up-down flag udf 0345 16 0346 16 timer a0 register ta0 0347 16 0348 16 timer a1 register ta1 0349 16 034a 16 timer a2 register ta2 034b 16 034c 16 timer a3 register ta3 034d 16 034e 16 timer a4 register ta4 034f 16 the blank area is reserved and cannot be used by user.
sfr under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 45 address register 0350 16 timer b0 register tb0 0351 16 0352 16 timer b1 register ta1 0353 16 0354 16 timer b2 register ta2 0355 16 0356 16 timer a0 mode register ta0mr 0357 16 timer a1 mode register ta1mr 0358 16 timer a2 mode register ta2mr 0359 16 timer a3 mode register ta3mr 035a 16 timer a4 mode register ta4mr 035b 16 timer b0 mode register tb0mr 035c 16 timer b1 mode register tb1mr 035d 16 timer b2 mode register tb2mr 035e 16 timer b2 special mode register tb2sc 035f 16 count source prescaler register tcspr 0360 16 0361 16 0362 16 0363 16 0364 16 uart0 special mode register 4 u0smr4 0365 16 uart0 special mode register 3 u0smr3 0366 16 uart0 special mode register 2 u0smr2 0367 16 uart0 special mode register u0smr 0368 16 uart0 transmit/receive mode register u0mr 0369 16 uart0 bit rate generator u0brg 036a 16 uart0 transmit buffer register u0tb 036b 16 036c 16 uart0 transmit/receive control register 0 u0c0 036d 16 uart0 transmit/receive control register 1 u0c1 036e 16 uart0 receive buffer register u0rb 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 pll control register 0 plc0 0377 16 0378 16 dma0 cause select register dm0sl 0379 16 dma1 cause select register dm1sl 037a 16 dma2 cause select register dm2sl 037b 16 dma3 cause select register dm3sl 037c 16 crc data register crcd 037d 16 037e 16 crc input register crcin 037f 16 the blank area is reserved and cannot be used by user. address register 0380 16 a-d0 register 0 ad00 0381 16 0382 16 a-d0 register 1 ad01 0383 16 0384 16 a-d0 register 2 ad02 0385 16 0386 16 a-d0 register 3 ad03 0387 16 0388 16 a-d0 register 4 ad04 0389 16 038a 16 a-d0 register 5 ad05 038b 16 038c 16 a-d0 register 6 ad06 038d 16 038e 16 a-d0 register 7 ad07 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 a-d0 control register 2 ad0con2 0395 16 0396 16 a-d0 control register 0 ad0con0 0397 16 a-d0 control register 1 ad0con1 0398 16 d-a register 0 da0 0399 16 039a 16 d-a register 1 da1 039b 16 039c 16 d-a control register dacon 039d 16 039e 16 039f 16
sfr under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 46 <144-pin version> address register 03a0 16 function select register a8 ps8 03a1 16 function select register a9 ps9 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 function select register c psc 03b0 16 function select register a0 ps0 03b1 16 function select register a1 ps1 03b2 16 function select register b0 psl0 03b3 16 function select register b1 psl1 03b4 16 function select register a2 ps2 03b5 16 function select register a3 ps2 03b6 16 function select register b2 psl2 03b7 16 function select register b3 psl3 03b8 16 03b9 16 function select register a5 ps5 03ba 16 03bb 16 03bc 16 function select register a6 ps6 03bd 16 function select register a7 ps7 03be 16 03bf 16 03c0 16 port p6 register p6 03c1 16 port p7 register p7 03c2 16 port p6 direction register pd6 03c3 16 port p7 direction register pd7 03c4 16 port p8 register p8 03c5 16 port p9 register p9 03c6 16 port p8 direction register pd8 03c7 16 port p9 direction register pd9 03c8 16 port p10 register p10 03c9 16 port p11 register p11 03ca 16 port p10 direction register pd10 03cb 16 port p11 direction register pd11 03cc 16 port p12 register p12 03cd 16 port p13 register p13 03ce 16 port p12 direction register pd12 03cf 16 port p13 direction register pd13 address register 03d0 16 port p14 register p14 03d1 16 port p15 register p15 03d2 16 port p14 direction register pd14 03d3 16 port p15 direction register pd15 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 pull-up control register 2 pur2 03db 16 pull-up control register 3 pur3 03dc 16 pull-up control register 4 pur4 03dd 16 03de 16 03df 16 03e0 16 port p0 register p0 03e1 16 port p1 register p1 03e2 16 port p0 direction register pd0 03e3 16 port p1 direction register pd1 03e4 16 port p2 register p2 03e5 16 port p3 register p3 03e6 16 port p2 direction register pd2 03e7 16 port p3 direction register pd3 03e8 16 port p4 register p4 03e9 16 port p5 register p5 03ea 16 port p4 direction register pd4 03eb 16 port p5 direction register pd5 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 pull-up control register 0 pur0 03f1 16 pull-up control register 1 pur1 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 port control register pcr the blank area is reserved and cannot be used by user.
sfr under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 47 1234567890123456789012345678901212345678901234567890123456789012 1 23456789012345678901234567890121234567890123456789012345678901 2 1 23456789012345678901234567890121234567890123456789012345678901 2 1 23456789012345678901234567890121234567890123456789012345678901 2 1 23456789012345678901234567890121234567890123456789012345678901 2 1 23456789012345678901234567890121234567890123456789012345678901 2 1 23456789012345678901234567890121234567890123456789012345678901 2 1234567890123456789012345678901212345678901234567890123456789012 1234567890123456789012345678901212345678901234567890123456789012 1 23456789012345678901234567890121234567890123456789012345678901 2 1 23456789012345678901234567890121234567890123456789012345678901 2 1 23456789012345678901234567890121234567890123456789012345678901 2 1 23456789012345678901234567890121234567890123456789012345678901 2 1 23456789012345678901234567890121234567890123456789012345678901 2 1 23456789012345678901234567890121234567890123456789012345678901 2 1234567890123456789012345678901212345678901234567890123456789012 1234567890123456789012345678901212345678901234567890123456789012 1 23456789012345678901234567890121234567890123456789012345678901 2 1 23456789012345678901234567890121234567890123456789012345678901 2 1 23456789012345678901234567890121234567890123456789012345678901 2 1234567890123456789012345678901212345678901234567890123456789012 12345678901234567890123456789012123456789 1 234567890123456789012345678901212345678 9 12345678901234567890123456789012123456789 12345678901234567890123456789 1 234567890123456789012345678 9 1 234567890123456789012345678 9 12345678901234567890123456789 12345678901234567890123456789 1 234567890123456789012345678 9 1 234567890123456789012345678 9 12345678901234567890123456789 12345678901234567890123456789 1 234567890123456789012345678 9 12345678901234567890123456789 12345678901234567890123456789 1 234567890123456789012345678 9 1 234567890123456789012345678 9 12345678901234567890123456789 12345678901234567890123456789 1 234567890123456789012345678 9 12345678901234567890123456789 12345678901234567890123456789 1 234567890123456789012345678 9 1 234567890123456789012345678 9 12345678901234567890123456789 <100-pin version> address register 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 function select register c psc 03b0 16 function select register a0 ps0 03b1 16 function select register a1 ps1 03b2 16 function select register b0 psl0 03b3 16 function select register b1 psl1 03b4 16 function select register a2 ps2 03b5 16 function select register a3 ps3 03b6 16 function select register b2 psl2 03b7 16 function select register b3 psl3 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 03c0 16 port p6 register p6 03c1 16 port p7 register p7 03c2 16 port p6 direction register pd6 03c3 16 port p7 direction register pd7 03c4 16 port p8 register p8 03c5 16 port p9 register p9 03c6 16 port p8 direction register pd8 03c7 16 port p9 direction register pd9 03c8 16 port p10 register p10 03c9 16 03ca 16 port p10 direction register pd10 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 address register 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 pull-up control register 2 pur2 03db 16 pull-up control register 3 pur3 03dc 16 03dd 16 03de 16 03df 16 03e0 16 port p0 register p0 03e1 16 port p1 register p1 03e2 16 port p0 direction register pd0 03e3 16 port p1 direction register pd1 03e4 16 port p2 register p2 03e5 16 port p3 register p3 03e6 16 port p2 direction register pd2 03e7 16 port p3 direction register pd3 03e8 16 port p4 register p4 03e9 16 port p5 register p5 03ea 16 port p4 direction register pd4 03eb 16 port p5 direction register pd5 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 pull-up control register 0 pur0 03f1 16 pull-up control register 1 pur1 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 port control register pcr 1234567 1 23456 7 1 23456 7 1234567 12345 1 234 5 12345 the blank area is reserved and cannot be used by user. note 1: addresses 03cb 16 , 03ce 16 , 03cf 16 , 03d2 16 , 03d3 16 does not exist in 100-pin version. must set "ff 16 " to the addresses at initial setting. note 2: addresses 03dc 16 area does not exist in 100-pin version. must set "00 16 " to addresses 03dc 16 at initial setting. note 3: addresses 03a0 16 , 03a1 16 , 03b9 16 , 03bc 16 , 03bd 16 , 03c9 16 , 03cc 16 , 03cd 16 , 03d30 16 , 03d1 16 does not exist in 100-pin version. 1234 1234
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer software reset 48 software reset writing 1 to bit 3 of the processor mode register 0 (address 0004 16 ) applies a (software) reset to the microcomputer. a software reset has the same effect as a hardware reset. the contents of internal ram are preserved. processor mode (1) types of processor mode one of three processor modes can be selected: single-chip mode, memory expansion mode, and micro- processor mode. the functions of some pins, memory map, and access space differ according to the selected processor mode. single-chip mode in single-chip mode, only internal memory space (sfr, internal ram, and internal rom) can be accessed. ports p0 to p15 can be used as programmable i/o ports or as i/o ports for the internal peripheral functions. memory expansion mode in memory expansion mode, external memory can be accessed in addition to the internal memory space (sfr, internal ram, and internal rom). in this mode, some of the pins function as an address bus, a data bus, and as control signals. the number of pins assigned to these functions depends on the bus and register settings. (see bus settings for details.) microprocessor mode in microprocessor mode, the sfr, internal ram and external memory space can be accessed. the internal rom area cannot be accessed. in this mode, some of the pins function as the address bus, the data bus, and as control signals. the number of pins assigned to these functions depends on the bus and register settings. (see bus settings for details.) (2) setting processor modes the processor mode is set using the cnv ss pin and the processor mode bits (bits 1 and 0 at address 0004 16 ). do not set the processor mode bits to 10 2 . regardless of the level of the cnv ss pin, changing the processor mode bits selects the mode. there- fore, never change the processor mode bits when changing the contents of other bits. also do not attempt to shift to or from the microprocessor mode within the program stored in the internal rom area. applying v ss to cnv ss pin the microcomputer begins operation in single-chip mode after being reset. memory expansion mode is selected by writing 01 2 to the processor mode is selected bits. applying v cc to cnv ss pin the microcomputer starts to operate in microprocessor mode after being reset. figure 1.6.1 and 1.6.2 show the processor mode register 0 and 1. figure 1.6.3 shows the memory maps applicable for each processor modes.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 49 processor mode 0 0 : multiplexed bus is not used 0 1 : allocated to cs2 space 0 1 : allocated to cs1 space 1 1 : allocated to entire cs space (note 5) note 1: set bit 1 of the protect register (address 000a 16 ) to "1" when writing new values to this register. note 2: do not set the processor mode bits and other bits simultaneously when setting the processor mode bits to 012 or 112 . set the other bits first,and then change the processor mode bits. note 3: when using 16-bit bus width in dram controler, must set this bit to "1". note 4: valid in microprocessor and memory expansion modes 1, 2 and 3. do not use multiplex bus when mode 0 is selected. do not set to allocated to cs2 space when mode 2 is selected. note 5: after the reset has been released, the m32c/83 group mcu operates using the separate bus. as a result, in microprocessor mode, you cannot select the full cs space multiplex bus. when you select the full cs space multiplex bus in memory expansion mode, the address bus operates with 64 kbytes boundaries, for each chip select. mode 0: multiplexed bus cannot be used. mode 1: cs0 to cs2 when you select full cs space. mode 2: cs0 to cs1 when you select full cs space. mode 3: cs0 to cs3 when you select full cs space. note 6: no bclk is output in single chip mode even when "0" is set in pm07. when stopping clock output in microprocessor or memory expansion mode, make the following settings: pm07="1", bit 0 (cm00) and bit 1 (cm01) of system clock control register 0 (address 0006 16 ) = "0". "l" is now output from p5 3 . note 7: when selecting bclk, set bits 0 and 1 of system clock control register 0 (cm00, cm01) to "0". symbol address when reset pm0 0004 16 80 16 (cnvss = "l") 03 16 (cnvss = "h") processor mode register 0 (note 1) rw b1 b0 b5 b4 0: rd / bhe / wr 1: rd / wrh / wrl pm00 pm01 pm02 (note 3) (note 2) pm03 software reset bit r/w mode select bit pm04 pm05 0 0: single-chip mode 0 1: memory expansion mode 1 0: must not be set 1 1: microprocessor mode must always be set to "0" pm07 bclk output disable bit (note 6) reserved bit 0 : bclk is output (note 7) 1 : function set by bit 0,1 of system clock control register 0 the device is reset when this bit is set to "1". the value of this bit is "0" when read bit name function bit symbol processor mode bit multiplexed bus space select bit (note 4) b7 b6 b5 b4 b3 b2 b1 b0 0 figure 1.6.1. processor mode register 0
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 50 processor mode processor mode register 1 (note 1) when reset 0x000000 2 address 0005 16 symbol pm1 rw pm10 pm11 pm12 external memory area mode bit (note 2) pm13 internal memory wait bit 0 : no wait state 1 : wait state inserted sfr area wait bit 0 reserved bit must set to "0" 0 : one wait state inserted 1 : two wait states inserted (note 4) pm14 pm15 pm17 ale pin select bit (note 2) 0 0 : no ale 0 1 : p5 3 /bclk (note 5) 1 0 : p5 6 /ras 1 1 : p5 4 /hlda nothing is assigned. when write, set "0". when read, its content is indeterminate. 0 0 : mode 0 (p4 4 to p4 7 : a 20 to a 23 ) 0 1 : mode 1 (p4 4 : a 20 , p4 5 to p4 7 : cs2 to cs0) 1 0 : mode 2 (p4 4 , p4 5 : a 20 , a 21 , p4 6 , p4 7 : cs1, cs0) 1 1 : mode 3 (note 3) (p4 4 to p4 7 : cs3 to cs0) b1 b0 b5 b4 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 note 1: set bit 1 of the protect register (address 000a 16 ) to 1 when writing new values to this register. note 2: valid in memory expansion mode or in microprocessor mode. note 3: when mode 3 is selected, dramc is not used. note 4: when accessing sfr area for can, pm13 must be set to "1". note 5: when selecting p5 3 /bclk, set bits 0 and 1 of system clock control register 0 (cm00, cm01) to "0". 0 figure 1.6.2. processor mode register 1
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 51 processor mode single chip mode memory expanded mode microprocessor mode sfr area internal ram area internal reserved area internal rom area no use external area 0 cs2 2mbytes external area 1 cs0 2mbytes external area 3 no use internal rom area internal reserved area internal rom area internal reserved area internal rom area internal reserved area cs0 3mbytes external area 3 cs1 4mbytes (note2) external area 0 external area 3 no use cs0 2mbytes external area 3 cs0 4mbytes external area 3 000000 16 000400 16 000800 16 200000 16 400000 16 c00000 16 e00000 16 f00000 16 ffffff 16 each cs0 to cs3 can set 0 to 3 wait. mode 0 mode 1 mode 2 mode 0 mode 1 mode 2 sfr area internal ram area internal reserved area sfr area internal ram area internal reserved area sfr area internal ram area internal reserved area sfr area internal ram area internal reserved area sfr area internal ram area internal reserved area sfr area internal ram area mode 3 internal reserved area sfr area internal ram area internal rom area internal reserved area cs1, 1mbytes external area 0 mode 3 internal reserved area sfr area internal ram area no use cs2, 1mbytes external area 1 no use connect with dram 0, 0.5 to 8mb (when not connect with dram, use as external area.) connect with dram 0, 0.5 to 8mb (when open area is under 8mb, cannot use the rest of this area.) connect with dram 0, 0.5 to 8mb (when open area is under 8mb, cannot use the rest of this area.) connect with dram 0, 0.5 to 8mb (when open area is under 8mb, cannot use the rest of this area.) no use (cannot use as dram area or external area.) connect with dram 0, 0.5 to 8mb (when not connect with dram, use as external area.) connect with dram 0, 0.5 to 8mb (when open area is under 8mb, cannot use the rest of this area.) no use (cannot use as dram area or external area.) no use no use no use cs1 2mbytes (note1) external area 0 no use note 1: 200000 16 C 008000 16 =2016 kbytes. 32 k less than 2 mb. note 2: 400000 16 C 008000 16 =4064 kbytes. 32 k less than 4 mb. external area 1 external area 0 cs2 2mbytes external area 1 cs1 4mbytes (note2) external area 0 cs1, 1mbytes external area 0 cs2, 1mbytes external area 1 cs1 2mbytes (note1) external area 0 external area 1 (external area 2) (external area 2) (external area 2) (external area 2) (external area 2) (external area 2) external area 3 cs3, 1mbytes external area 2 cs0, 1mbytes external area 3 cs3, 1mbytes external area 2 cs0, 1mbytes external area 3 processor mode figure 1.6.3. memory maps in each processor mode
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer bus settings 52 table 1.7.1. factors for switching bus settings bus settings the byte pin, bit 0 to 3 of the external data bus width control register (address 000b 16 ), bits 4 and 5 of the processor mode register 0 (address 0004 16 ) and bit 0 and 1 of the processor mode register 1 (address 0005 16 ) are used to change the bus settings. table 1.7.1 shows the factors used to change the bus settings, figure 1.7.1 shows external data bus width control register and table 1.7.2 shows external area 0 to 3 and external area mode. bus setting switching factor switching external address bus width external data bus width control register switching external data bus width byte pin (external area 3 only) switching between separate and multiplex bus bits 4 and 5 of processor mode register 0 selecting external area bits 0 and 1 of processor mode register 1 (1) selecting external address bus width you can select the width of the address bus output externally from the 16 mbytes address space, the number of chip select signals, and the address area of the chip select signals. (note, however, that ____ when you select full cs space multiplex bus , addresses a 0 to a 15 are output.) the combination of bits 0 and 1 of the processor mode register 1 allow you to set the external area mode. when using dram controller, the dram area is output by multiplexing of the time splitting of the row and column addresses. (2) selecting external data bus width you can select 8-bit or 16-bit for the width of the external data bus for external areas 0, 1, 2, and 3. when the data bus width bit of the external data bus width control register is 0 , the data bus width is 8 bits; when 1 , it is 16 bits. the width can be set for each of the external areas. the default bus width for external area 3 is 16 bits when the byte pin is l after a reset, or 8 bits when the byte pin is h after a reset. the bus width selection is valid only for the external bus (the internal bus width is always 16 bits). during operation, fix the level of the byte pin to h or l . (3) selecting separate/multiplex bus the bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0. separate bus in this bus configuration, input and output is performed on separate data and address buses. the data bus width can be set to 8 bits or 16 bits using the external data bus width control register. for all programmable external areas, p0 is the data bus when the external data bus is set to 8 bits, and p1 is a programmable io port. when the external data bus width is set to 16 bits for any of the external areas, p0 and p1 (although p1 is undefined for any 8-bit bus areas) are the data buses. when accessing memory using the separate bus configuration, you can select a software wait using the wait control register. multiplex bus in this bus configuration, data and addresses are input and output on a time-sharing basis. for areas for which 8-bit has been selected using the external data bus width control register, the 8 bits d 0 to d 7 are multiplexed with the 8 bits a 0 to a 7 . for areas for which 16-bit has been selected using the external data bus width control register, the 16 bits d 0 to d 15 are multiplexed with the 16 bits a 0 to a 15 . when
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer bus settings 53 external data bus width control register symbol address when reset ds 000b 16 xxxxx000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ds3 ds1 ds0 external area 0 data bus width bit ds2 external area 1 data bus width bit external area 2 data bus width bit external area 3 data bus width bit (note) 0 : 8 bits data bus width 1 : 16 bits data bus width note: the value after a reset is determined by the input via the byte pin. when byte pin is "l", ds3 is "1". when "h", it is "0". w r aa a aa a aa a aa a nothing is assigned. when write, set "0". when read, their contents are indeterminate. 0 : 8 bits data bus width 1 : 16 bits data bus width 0 : 8 bits data bus width 1 : 16 bits data bus width 0 : 8 bits data bus width 1 : 16 bits data bus width external area mode (note 2) mode 0 mode 1 mode 2 mode 3 external area 0 external area 1 external area 2 external area 3 memory expansion mode memory expansion mode , microprocessor mode microprocessor mode memory expansion mode , microprocessor mode 008000 16 to 1fffff 16 200000 16 to 3fffff 16 400000 16 to bfffff 16 (note 1) c00000 16 to efffff 16 c00000 16 to ffffff 16 008000 16 to 1fffff 16 200000 16 to 3fffff 16 400000 16 to bfffff 16 c00000 16 to efffff 16 e00000 16 to ffffff 16 008000 16 to 1fffff 16 400000 16 to bfffff 16 c00000 16 to efffff 16 c00000 16 to ffffff 16 100000 16 to 1fffff 16 200000 16 to 2fffff 16 c00000 16 to cfffff 16 e00000 16 to efffff 16 f00000 16 to ffffff 16 memory expansion mode , microprocessor mode no area is selected. accessing memory using the multiplex bus configuration, two waits are inserted regardless of whether you select no wait or 1 wait in the appropriate bit of the wait control register. ____ the default after a reset is a separate bus configuration, and the full cs space multiplex bus configu- ____ ration cannot be selected in microprocessor mode. if you select full cs space multiplex bus , the 16 bits from a0 to a15 are output for the address figure 1.7.1. external data bus width control register table 1.7.2. external area 0 to 3 and external area mode note 1: dramc area when using dramc. note 2: set the external area mode (modes 0, 1, 2, and 3) using bits 0 and 1 of the processor mode register 1 (address 0005 16 ).
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer bus settings 54 p0 0 to p0 7 i/o port data bus data bus data bus data bus i/o port i/o port cs1 or cs2 : multiplexed bus, and the other : separate bus separate bus all space multiplexed bus single-chip mode memory expansion mode/microprocessor modes memory expansion mode data bus width byte pin level 01 , 10 00 11 (note 1) all external area is 8 bits some external area is 16 bits all external area is 8 bits some external area is 16 bits note 1:the default after a reset is the separate bus configuration, and "full cs space multiplex bus" cannot be selected in microprocessor mode. when you select "full cs space multiplex bus" in extended memory mode, the address bus operates with 64 kbytes boundaries for each chip select. note 2: address bus in separate bus configuration. note 3: the ale output pin is selected using bits 4 and 5 of the processor mode register 1. note 4: when you have selected the dram controller and access the dram area, these are outputs casl, cash, dw, and bclk. note 5: the cs signal and address bus selection are set by the external area mode. processor mode multiplexed bus space select bit cs (chip select) or address bus (a 23 ) (for details, refer to bus control ) (note 5) outputs rd, wrl, wrh, and bclk or rd, bhe, wr, and bclk (for details, refer to bus control ) (note 3,4) p1 0 to p1 7 i/o port i/o port i/o port data bus i/o port i/o port i/o port p2 0 to p2 7 i/o port address bus address bus address bus address bus address bus address bus /data bus /data bus /data bus /data bus p4 0 to p4 3 i/o port address bus address bus address bus address bus i/o port i/o port p4 4 to p4 6 i/o port cs (chip select) or address bus (a 23 ) (for details, refer to bus control ) (note 5) p4 7 i/o port p5 0 to p5 3 i/o port p5 4 i/o port hlda(note 3) hlda(note 3) hlda(note 3) hlda(note 3) hlda(note 3) hlda(note 3) p5 5 i/o port hold hold hold hold hold hold p5 6 i/o port ras (note 3) ras (note 3) ras (note 3) ras (note 3) ras (note 3) ras (note 3) p5 7 i/o port rdy rdy rdy rdy rdy rdy p3 0 to p3 7 i/o port address bus address bus address bus address bus address bus address bus /data bus /data bus (note 2) (note 2) (note 2) all external area is 8 bits some external area is 16 bits table 1.7.3. each processor mode and port function
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer bus control 55 processor mode memory space expansion mode specified address range memory expansion mode mode 0 chip select signal cs0 cs1 cs2 cs3 c00000 16 to dfffff 16 (2 mbytes) microprocessor mode memory expansion mode 008000 16 to 1fffff 16 (2016 kbytes) 200000 16 to 3fffff 16 (2 mbytes) 008000 16 to 3fffff 16 (4064 kbytes) microprocessor mode e00000 16 to ffffff 16 (2 mbytes) c00000 16 to efffff 16 (3 mbytes) c00000 16 to ffffff 16 (4 mbytes) e00000 16 to efffff 16 (1 mbytes) 100000 16 to 1fffff 16 (1 mbytes) mode 1 mode 2 mode 3 memory expansion mode microprocessor mode f00000 16 to ffffff 16 (1 mbytes) 200000 16 to 2fffff 16 (1 mbytes) c00000 16 to cfffff 16 (1 mbytes) (a22) (a21) (a20) (a23) (a21) (a20) (a20) bus control the following explains the signals required for accessing external devices and software waits. the signals required for accessing the external devices are valid when the processor mode is set to memory expan- sion mode and microprocessor mode. (1) address bus/data bus _____ there are 24 pins, a 0 to a 22 and a 23 for the address bus for accessing the 16 mbytes address space. _____ a 23 is an inverted output of the msb of the address. the data bus consists of pins for data io. the external data bus control register (address 000b 16 ) selects the 8-bit data bus, d 0 to d 7 for each external area, or the 16-bit data bus, d 0 to d 15 . after a reset, there is by default an 8-bit data bus for the external area 3 when the byte pin is high, or a 16-bit data bus when the byte pin is low. when shifting from single-chip mode to extended memory mode, the value on the address bus is unde- fined until an external area is accessed. when accessing a dram area with dram control in use, a multiplexed signal consisting of row address and column address is output to a 8 to a 20 . (2) chip select signals _____ the chip select signals share a 0 to a 22 and a 23 . you can use bits 0 and 1 of the processor mode register 1 (address 0005 16 ) to set the external area mode, then select the chip select area and number of address outputs. in microprocessor mode, external area mode 0 is selected after a reset. the external area can be split into a maximum of four blocks or areas using the chip select signals. table 1.7.4 shows the external areas specified by the chip select signals. table 1.7.4. external areas specified by the chip select signals
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer bus control 56 example 1: after accessing the external area, the address bus and chip select signal both are changed in the next cycle. the following example shows the other chip select signal accessing area (j) in the cycle after having accessed external area (i). in this case, the address bus and chip select signal both change between the two cycles. note: these examples show the address bus and chip select signal for two consecutive cycles. by combining these examples, chip select signal can be extended beyond two cycles. data bus address bus chip select (csi) access to external area (i) chip select (csj) access to external area (j) address data data example 2: after accessing the external area, only the chip select signal is changed in the next cycle. (the address bus does not change.) the following example shows the cpu accesses the internal rom/ram area in the cycle after having accessed external area. in this case, the chip select signal changes between the two cycles but the address bus does not. example 3: after accessing the external area, only the address bus is changed in the next cycle. (the chip select signal does not change.) the following example shows the same chip select signal accessing area (i) in the cycle after having accessed external area (i). in this case, the address bus changes between the two cycles, but the chip select signal does not. data bus address bus chip select (csi) data address data bus address bus chip select data address access to external area no access access to external area (i) access to external area (i) data bus address bus chip select data address example 4: after accessing the external area, the address bus and chip select signal both are not changed in the next cycle. the following example shows cpu does not access any area in the cycle after having accessed external area (no instruction pre-fetch is occurred). in this case, the address bus and the chip select signal do not change between the two cycles. data access to external area access to internal rom/ram area the chip select signal turns low (active) in synchronize with the address bus. however, its turning high depends on the area accessed in the next cycle. figure 1.7.2 shows the output examples of the address bus and chip select signals. figure 1.7.2. example of address bus and chip select signal outputs (separate bus)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer bus control 57 status of external data bus rd bhe wr hll lhl hlh lhh write 1 byte of data to odd address read 1 byte of data from odd address write 1 byte of data to even address read 1 byte of data from even address data bus width a0 h h l l hll l lhl l hl h / l lh h / l 8-bit write data to both even and odd addresses read data from both even and odd addresses write 1 byte of data read 1 byte of data 16-bit not used not used status of external data bus read data write 1 byte of data to even address write 1 byte of data to odd address write data to both even and odd addresses wrh wrl rd data bus width 16-bit h h h h l h l h h l l l h h (note) l (note) l not used write 1 byte of data read 1 byte of data not used 8-bit (3) read/write signals with a 16-bit data bus, bit 2 of the processor mode register 0 (address 0004 16 ) selects the combinations _____ ________ ______ _____ ________ _________ of rd, bhe, and wr signals or rd, wrl, and wrh signals. with a 8-bit full space data bus, use the _____ ______ ________ combination of rd, wr, and bhe signals as read/write signals. (set "0" to bit 2 of the processor mode register 0 (address 0004 16 ).) when using both 8-bit and 16-bit data bus widths to access a 8-bit data bus _____ ______ ________ area, the rd, wr and bhe signals combination is selected regardless of the value of bit 2 of the processor mode register 0 (address 0004 16 ). tables 1.7.5 and 1.7.6 show the operation of these signals. _____ ______ ________ after a reset has been cancelled, the combination of rd, wr, and bhe signals is automatically se- lected. _____ _________ _________ when switching to the rd, wrl, and wrh combination, do not write to external memory until bit 2 of the processor mode register 0 (address 0004 16 ) has been set (note) . note 1: before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000a 16 ) to 1 . _____ ________ _________ note 2: when using 16-bit data bus width for dram controller, select rd, wrl, and wrh signals. _____ ________ _________ table 1.7.5. operation of rd, wrl, and wrh signals ______ note: it becomes wr signal. _____ ______ ________ table 1.7.6. operation of rd, wr, and bhe signals
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer bus control 58 when byte pin = h when byte pin = l ale address data address d 0 /a 0 to d 7 /a 7 a 8 to a 15 ale address data address d 0 /a 0 to d 15 /a 15 a 16 to a 19 note 1: floating when reading. note 2: when full space multiplexed bus is selected, these are i/o ports. address address or cs a 20 to a 22 , a 23 address or cs a 20 to a 22 , a 23 a 16 to a 19 (note 1) (note 1) (note 2) (note 2) (4) ale signal the ale signal latches the address when accessing the multiplex bus space. latch the address when the ale signal falls. the ale output pin is selected using bits 4 and 5 of the processor mode register 1 (address 0005 16 ). the ale signal is occurred regardless of internal area and external area. figure 1.7.3. ale signal and address/data bus (5) ready signal the ready signal facilitates access of external devices that require a long time for access. as shown in ________ figure 1.7.2, inputting l to the rdy pin at the falling edge of bclk causes the microcomputer to enter ________ the ready state. inputting h to the rdy pin at the falling edge of bclk cancels the ready state. table _____ 1.7.7 shows the microcomputer status in the ready state. figure 1.7.4 shows the example of the rd ________ signal being extended using the rdy signal. ready is valid when accessing the external area during the bus cycle in which the software wait is ________ applied. when no software wait is operating, the rdy signal is ignored, but even in this case, unused pins must be pulled up. table 1.7.7. microcomputer status in ready state (note) note: the ready signal cannot be received immediately prior to a software wait. item status oscillation on _____ _____ _____ rd/wr signal, address bus, data bus, cs maintain status when ready signal received __________ ale signal, hlda, programmable i/o ports internal peripheral circuits on
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer bus control 59 rdy received timing aa separate bus (2 wait) multiplexed bus (2 wait) bclk rd cs i (i=0 to 3) rdy aaaaaa aaaaaa bclk rd cs i (i=0 to 3) rdy tsu(rdy - bclk) aaaaaaaa aaaaaaaa 1st cycle 2nd cycle 3rd cycle 4th cycle tsu(rdy - bclk) rdy received timing tsu (rdy-bclk) =rdy input setup time rdy signal received timing for i wait(s): i + 1 cycles (i = 1 to 3) 1st cycle 2nd cycle 3rd cycle 4th cycle : wait using rdy signal : wait using software (note) (note) note: chip select (csi) may get longer by a state of cpu such as an instruction queue buffer. _____ ________ figure 1.7.4. example of rd signal extended by rdy signal
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer bus control 60 __________ hold > dmac > cpu (6) hold signal the hold signal is used to transfer the bus privileges from the cpu to the external circuits. inputting l __________ to the hold pin places the microcomputer in the hold state at the end of the current bus access. this __________ __________ status is maintained and l is output from the hlda pin as long as l is input to the hold pin. table 1.7.8 shows the microcomputer status in the hold state. the bus is used in the following descending __________ order of priority: hold, dmac, cpu. _____ ________ figure 1.7.5. example of rd signal extended by rdy signal table 1.7.8. microcomputer status in hold state item status oscillation on _____ _____ _____ _______ rd/wr signal, address bus, data bus, cs, bhe floating programmable i/o ports: p0 to p15 m aintains status when hold signal is received __________ hlda output l internal peripheral circuits on (but watchdog timer stops) ale signal output l (7) external bus status when accessing to internal area table 1.7.9 shows external bus status when accessing to internal area table 1.7.9. external bus status when accessing to internal area item sfr accessing status internal rom/ram accessing status address bus remain address of external area accessed immediately before data bus when read floating when write floating _____ ______ ________ _________ rd, wr, wrl, wrh output "h" ________ bhe remain external area status accessed immediately before ____ cs output "h" ale ale output (8) bclk output bclk output can be selected by bit 7 of the processor mode register 0 (address 0004 16 :pm07) and bit 1 and bit 0 of the system clock select register 0 (address 0006 16 :cm01, cm00). setting pm07 to 0 and cm01 and cm00 to 00 outputs the bclk signal from p5 3 . however, in single chip mode, bclk signal is inactive. when setting pm07 to 1 , the function is set by cm01 and cm00.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer bus control 61 status of external data bus ras cash casl lll llh llh lll read data from both even and odd addresses read 1 byte of data from even address read 1 byte of data from odd address write data to both even and odd addresses data bus width dw h h h l llhl lhl l ll h ll l 8-bit write 1 byte of data to even address write 1 byte of data to odd address read 1 byte of data write 1 byte of data 16-bit not used not used _______ __________ __________ _____ (9) dram controller signals (ras, casl, cash, and dw) bits 1, 2, and 3 of the dram control register (address 0004 16 ) select the dram space and enable the dram controller. the dram controller signals are output when the dram area is accessed. table 1.7.10 shows the operation of the respective signals. _______ __________ __________ _____ table 1.7.10. operation of ras, casl, cash, and dw signals (10) software wait a software wait can be inserted by setting the wait control register (address 0008 16 ). figure 1.7.6 shows wait control register. you can use the external area i wait bits (where i = 0 to 3) of the wait control register to specify from no wait to 3 waits for the external memory area. when you select no wait , the read cycle is executed in the bclk1 cycle. the write cycle is executed in the bclk2 cycle (which has 1 wait). when accessing external memory using the multiplex bus, access has two waits regardless of whether you specify no wait or 1 wait in the appropriate external area i wait bits in the wait control register. software waits in the internal memory (internal ram and internal rom) can be set using the internal memory wait bits of the processor mode register 1 (address 0005 16 ). setting the internal memory wait bit = 0 sets no wait . setting the internal memory wait bit = 1 specifies a wait. sfr area is accessed with either "1 wait" (bclk 2-cycle) or "2 waits" (bclk 3-cycle) by setting the sfr wait bit (bit 3) of the processor mode register 1 (address 0005 16 ). sfr area of can must be accessed with "2 waits". table 1.7.11 shows the software waits and bus cycles. figures 1.7.7 and 1.7.8 show example bus timing when using software waits.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer bus control 62 area bus status internal memory wait bit external memory area i wait bit bus cycle 1 2 bclk cycles external memory area 00 2 read :1 bclk cycle separate bus write : 2 bclk cycles 2 bclk cycles 3 bclk cycles multiplex bus 4 bclk cycles sfr internal rom/ram 0 1 bclk cycle 2 bclk cycles 3 bclk cycle 3 bclk cycles 3 bclk cycles 4 bclk cycles 01 2 11 2 00 2 01 2 11 2 10 2 10 2 3 bclk cycles sfr area wait bit 0 1 wait control register (note 1, 2) symbol address when reset wcr 0008 16 ff 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0: without wait 0 1: with 1 wait 1 0: with 2 waits 1 1: with 3 waits b1 b0 wcr3 wcr1 wcr0 external area 0 wait bit wcr2 external area 1 wait bit external area 2 wait bit wcr4 external area 3 wait bit wcr5 wcr7 note 1: when using the multiplex bus configuration, there are two waits regardless of whether you have specified "no wait" or "1 wait". however, you can specify "2 waits" or "3 waits". note 2: when using the separate bus configuration, the read bus cycle is executed in the bclk1 cycle, and the write cycle is executed in the bclk2 cycle (with 1 wait). w r a a aa aa a a aa aa a a aa aa a aa a aa a aa a aa a aa wcr6 0 0: without wait 0 1: with 1 wait 1 0: with 2 waits 1 1: with 3 waits b3 b2 0 0: without wait 0 1: with 1 wait 1 0: with 2 waits 1 1: with 3 waits b5 b4 0 0: without wait 0 1: with 1 wait 1 0: with 2 waits 1 1: with 3 waits b7 b6 figure 1.7.6. wait control register table 1.7.11. software waits and bus cycles
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer bus control 63 output input address address bus cycle (note) < separate bus (with wait) > bclk read signal write signal data bus address bus (note 2) chip select (note 2,3) bclk read signal data bus chip select (note 2,3) data output address address bus (note 2) address input < separate bus with 2 wait > write signal bclk read signal write signal address bus (note 2) address bus cycle (note) < separate bus (no wait) > output data bus chip select (note 2,3) input bus cycle (note) bus cycle (note) bus cycle (note 1) bus cycle (note 1) address note 1: this timing example shows bus cycle length. read cycle and write cycle may be continued after this bus cycle. note 2: address bus and chip select may get longer depending on the state of cpu such as an instruction queue buffer. note 3: when accessing same external area (same cs area) continuously, chip select may output continuously. figure 1.7.7. typical bus timings using software wait
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer bus control 64 bclk read signal write signal address bus/data bus (note 2) chip select (note 2,3) address address address data output address address input ale bus cycle (note) < multiplexed bus (with 2 wait) > bus cycle (note) bclk read signal write signal chip select (note 2,3) bus cycle (note) < separate bus (with 3 wait) > address address (note 2) address bus cycle (note) data bus data output input bclk read signal write signal address bus /data bus ( note 2) chip select (note 2,3) address address data output address input bus cycle (note) < multiplexed bus (with 3 wait) > address address ale bus cycle (note) note 1: this timing example shows bus cycle length. read cycle and write cycle may be continued after this bus cycle. note 2: address bus and chip select may get longer depending on the state of cpu such as an instruction queue buffer. note 3: when accessing same external area (same cs area) continuously, chip select may output continuously. figure 1.7.8. typical bus timings using software wait
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer clock generating circuit 65 table 1.8.2. control registers for each clock generating circuits clock generating circuit control register main clock system clock control register 0 (address 0006 16 ) :cm0 system clock control register 1 (address 0007 16 ) :cm1 main clock divide register (address 000c 16 ) : mcd sub clock system clock control register 0 (address 0006 16 ) : cm0 system clock control register 1 (address 0007 16 ) :cm1 oscillation stop detect function oscillation stop detect register (address 000d 16 ) : cm2 note : cm0, cm1, cm2 and mcd registers are protected from a false write by program runaway. when you want to rewrite these registers, set "1" to bit 0 of protect register (address 000a 16 ) to release protect, then rewrite the register. system clock clock generating circuit the clock generating circuit contains three oscillator circuits as follows: (1) main clock generating circuit (2) sub clock generating circuit (3) ring oscillator (oscillation stop detect function) table 1.8.1 lists the clock generating circuit specifications and table 1.8.2 lists registers controlling each clock generating circuit. figure 1.8.1 shows block diagram of the system clock generating circuit. figure 1.8.2 to 1.8.5 show clock control related registers. ? cpu's operating clock source ? internal peripheral unit's operating clock source use of clock main clock generating circuit sub clock generating circuit item ? cpu's operating clock source ? timer a/b's count clock source clock frequency 0 to 30 mhz 32.768 khz ? ceramic oscillator ? crystal oscillator usable oscillator ? crystal oscillator x in , x out pins to connect oscillator x cin , x cout presence oscillation stop/ restart function presence oscillating oscillator status after reset stopped externally derived clock can be input other ring oscillator ? cpu's operating clock source when main clock frequency stops about 1 mhz presence stopped table 1.8.1. the clock oscillation circuit specifications
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer clock generating circuit 66 interrupt request signal clock from x in ring oscillator clock ring oscillator circuit charge and discharge circuit interrupt generating circuit clock edge detect /charge and discharge circuit control watchdog timer interrupt cm21 switch select signal bclk cm05 cm02 cm07 f c x in x out x cin x cout main clock sub clock cm04 f c32 1/32 s q r s q r nmi reset interrupt request level judgment output software reset (wait mode) wait instruction (stop mode) write "1" to cm10 divide rate m (m=1,2,3,4,6,8,10,12,14,16 ) is set by bit 0 to 4 at main clock divide register (address 000c 16 ) 1/m e f divider 3 ring oscillator divider 1 1/2 1/2 1/2 a 1/2 1/n cd divide rate 2n (n=0 to 15) is set by bit 0 to 3 at count source prescaler register (address 035f 16 ) bit 7 at address 035f 16 divider 2 ef divider 3 f ad f 1 divider 1 a b f 2 n cd divider 2 cm0i : bit i at system clock control register 0 (address 0006 16 ) cm1i : bit i at system clock control register 1 (address 0007 16 ) cm2i : bit i at oscillation stop detect register (address 000d 16 ) ring oscillator circuit cm21 f 8 b figure 1.8.1. clock generating circuit
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer clock generating circuit 67 figure 1.8.2. clock control related register (1) system clock control register 0 (note 1) symbol address when reset cm0 0006 16 0000 x000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p5 3 0 1 : f c output 1 0 : f 8 output 1 1 : f 32 output b1 b0 cm07 cm05 cm04 cm01 cm02 cm00 clock output function select bit (note 2) wait peripheral function clock stop bit 0 : do not stop peripheral clock in wait mode 1 : stop peripheral clock in wait mode (note 3) port x c select bit 0 : i/o port 1 : x cin -x cout generation (note 4) main clock (x in -x out ) stop bit (note 5) 0 : main clock on 1 : main clock off (note 6) system clock select bit (note 8) 0 : x in , x out 1 : x cin , x cout w r a aa a aa a a aa aa a aa a aa a aa a aa cm06 watchdog timer function select bit 0 : watchdog timer interrupt 1 : reset (note 7) nothing is assigned. when write, set "0". when read, their contents are indeterminate. note 1: set bit 0 of the protect register (address 000a 16 ) to 1 before writing to this register. note 2: the port p5 3 dose not function as an i/o port in microprocessor or memory expansion mode. when outputting ale to p5 3 (bits 5 and 4 of processor mode register 0 is "01"), set these bits to "00". the port p5 3 function is not selected, even when you set "00" in microprocessor or memory expansion mode and bit 7 of the processor mode register 0 is "1". note 3: fc 32 is not included. when this bit is set to "1", pll cannot be used in wait. note 4: when xc in -xc out is used, set port p8 6 and p8 7 to no pull-up resistance with the input port. note 5: when entering the power saving mode, the main clock is stopped using this bit. to stop the main clock, set system clock stop bit (cm07) to "1" while an oscillation of sub clock is stable. then set this bit to "1". when x in is used after returning from stop mode, set this bit to "0". when this bit is "1", x out is "h". also, the internal feedback resistance remains on, so x in is pulled up to x out ("h" level) via the feedback resistance. note 6: when the main clock is stopped, the main clock division register (address 000c 16 ) is set to the division by 8 mode. however, in ring oscillator mode, the main clock division register is not set to the division by 8 mode when x in -x out is stopped by this bit. note 7: when "1" has been set once, "0" cannot be written by software. note 8: set this bit "0" to "1" when sub clock oscillation is stable by setting cm04 to "1". set this bit "1" to "0" when main clock oscillation is stable by setting cm05 to "0". do not set cm04 and cm05 simultaneously.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer clock generating circuit 68 system clock control register 1 (note 1) symbol address when reset cm1 0007 16 00100000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (note 2) 0 : clock on 1 : all clocks off (stop mode) (note 3) note 1: set bit 0 of the protect register (address 000a 16 ) to 1 before writing to this register. note 2: when this bit is "1", x out is "h", and the internal feedback resistance is disabled. x cin and x cout are high-inpedance. note 3: when all clocks are stopped (stop mode), the main clock division register (address 000c 16 ) is set to the division by 8 mode. w r reserved bit must set to 0 0 00 0 a a a a a a a a a a a a reserved bit must set to 0 a a 00 reserved bit must set to 1 1 main clock division register (note 1) symbol address when reset mcd 000c 16 xxx01000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 0 : no division mode 0 0 0 1 0 : division by 2 mode 0 0 0 1 1 : division by 3 mode 0 0 1 0 0 : division by 4 mode 0 0 1 1 0 : division by 6 mode 0 1 0 0 0 : division by 8 mode 0 1 0 1 0 : division by 10 mode 0 1 1 0 0 : division by 12 mode 0 1 1 1 0 : division by 14 mode 0 0 0 0 0 : division by 16 mode b4 b3 b2 b1 b0 mcd4 mcd3 mcd1 mcd2 mcd0 main clock division select bit (note 2, 4) note 1: set bit 0 of the protect register (address 000a 16 ) to 1 before writing to this register. note 2: these bits are "01000 2 " (8-division mode) when main clock is stopped or you shift to stop mode. however, in ring oscillator mode, this register is not set to the division by 8 mode when x in -x out is stopped by main clock stop bit. note 3: do not attempt to set combinations of values other than those shown in this figure. note 4: sfr area of can is accessed with no division mode. w r a a aa aa a a aa aa a a aa aa a a aa aa a a aa aa nothing is assigned. when write, set "0". when read, their contents are indeterminate. figure 1.8.3. clock control related registers (2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer clock generating circuit 69 cm20 cm21 cm22 cm23 (note 2,3) (note 4) (note 5) note 1: set bit 0 of the protect register (address 000a 16 ) to "1" before writing to this register. note 2: when x in oscillation stop is detected in cm20="1", this bit becomes "1". after this, although x in starts oscillating, this bit does not become "0". when you change to x in as system clock after x in restarts oscillating, write "0" to this bit. note 3: when cm20="1" and cm22="1", this bit cannot be written. note 4: when detecting oscillation stop, this bit becomes "1". "0" can be written by software. when "0" is written during x in oscillation stop, this bit does not becomes "1" although x in oscillating stops. note 5: x in state is judged by reading this bit several times in oscillation stop interrupt process program. oscillation stop detect register (note 1) main clock switching bit oscillation stop detect enable bit x in clock monitor flag oscillation stop detect flag reserved bit 0: x in oscillating 1: x in not oscillating 0: x in selected 1: ring oscillator selected 0: ignored 1: detect oscillation stop 0: oscillation stop detect function disabled 1: oscillation stop detect function enabled must set to "0" symbol address when reset cm2 000d 16 00 16 rw function bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 00 0 figure 1.8.4. clock control related register (3)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer clock generating circuit 70 cnt0 cnt1 cnt2 cnt3 cst (note) note : write to these bits during the count stop. count source prescale register division rate select bit operation enable bit 0: divider stops 1: divider starts 0 0 0 0: no-division 0 0 0 1: division by 2 0 0 1 0: division by 4 0 0 1 1: division by 6 ? ? ? 1 1 0 1: division by 26 1 1 1 0: division by 28 1 1 1 1: division by 30 nothing is assigned. when write, set to "0". when read, their contents are indeterminate. symbol address when reset tcspr 035f 16 0xxx 0000 2 rw b 3 b 2 b 1 b 0 function bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 figure 1.8.5. clock control related register (4) reserved bit must set to "0" plv00 (note 2) function note 1: when rewriting this register, set bit 3 of protect regiser (address 000a 16 ) to "1". note 2: set this bit to "0" before shifting to stop mode. vdc control register for pll (note 1) pll vdc enable bit 0 : cut off power to pll 1 : power to pll bit name bit symbol symbol address when reset plv 0017 16 xxxxxx01 2 rw b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. when write, set to "0". when read, their contents are indeterminate.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer clock generating circuit 71 (1) main clock the main clock is a clock source for cpu operation and peripheral i/o. figure 1.8.6 shows example of a main clock. when a reset, the clock oscillates and after a reset, the clock is divided by 8 to the bclk (cpu operating clock). (a) main clock on/off function ? main clock (x in -x out ) stop bit of system control register 0 (bit 5 at address 0006 16 ) 0: main clock on 1: main clock off also, the clock is stopped by shifting to the stop mode. ? all clock stop control bit of system control register 1 (bit 0 at address 0007 16 ) 0: clock on 1: all clocks off (stop mode) figure 1.8.6. examples of main clock microcomputer (built-in feedback resistance) x in x out externally derived clock open vcc vss microcomputer (built-in feedback resistance) x in x out r d c in c out (note) note: insert a damping resistance if required. the resistance will vary depending on the oscillator setting. use the value recommended by the maker of the oscillator. insert a feedback resistance between x in and x out when an oscillation manufacture required.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 72 (2) sub clock the sub clock is a clock source for cpu operation and count source for timer a and b. figure 1.8.7 shows example of sub clock. when the sub clock is used, set ports p8 6 and p8 7 to no pull-up resistance with the input port. no sub clock is generated during and after a reset. (a) sub clock on/off function when you want to use sub clock, set the following bit and sub clock enabled. ? port xc select bit of system control register 0 (bit 4 at address 0006 16 ) 0: i/o port (sub clock off) 1: x in -x out generation (sub-clock on) also, shifting to the stop mode stops the clock. ? all clock stop control bit of system control register 1 (bit 0 at address 0007 16 ) 0: clock on 1: all clock stop (stop mode) clock generating circuit figure 1.8.7. examples of sub clock microcomputer (built-in feedback resistance) x cin x cout externally derived clock open vcc vss note: insert a damping resistance if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. insert a feedback resistance between x cin and x cout when an oscillation manufacture required. microcomputer (built-in feedback resistance) x cin x cout (note) c cin c cout r cd
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer clock generating circuit 73 (3) oscillation stop detect function (osd function) this function monitor the main clock (x in pin). when main clock is stopped, internal ring oscillator starts ocsillation and replace the main clock. then oscillation stop detect interrupt process is operated. when frequency of main clock is less or equal than 2mhz, this function does not work. (a) osd function enable/disable ? osd enable bit of oscillation stop detect register (bit 0 at address 000d 16 ) 0: osd function disabled 1: osd function enabled set osd enable bit (bit 0) of oscillation stop detect register to "0" to disable osd function before setting stop mode. stop mode is canceled before setting this bit to "1". (b) operation when oscillation stop detects 1) when x in oscillation stops, a built in ring oscillation starts as a main clock automatically. 2) osd interrupt request is generated, jump to an address fffff0 16 to fffff3 16 allocated fixed vector table (watchdog timer interrupt vector) and execute program of jump address. 3) osd interrupt shares vector table with watchdog timer interrupt. when using both osd and watch- dog timer interrupts, read and judge osd flag in interrupt process routine. osd flag of oscillation stop detect register (bit 2 at address 000d 16 ) 1: oscillation stop detects 4) x in does not become main clock although x in on after oscillation stop detects. when you want x in to be main clock, execute a process shown in figure 1.8.8. x in switching x in is on confirm x in is on write "0" to osd flag write "0" to main clock select bit end off on confirm x in is on several times oscillation stop detect register (address 000d 16 ) bit 3: x in clock monitor flag 0: x in on 1: x in off bit2: oscillation stop detect flag bit 1: main clock select bit 0: x in selected 1: ring oscillator selected figure 1.8.8. main clock switching sequence
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 74 cpu clock (bclk) main clock, sub clock or clock from ring oscillator can be selected as clock source for bclk. system clock select bit of system clock control register (bit 7 at address 0006 16 ) 0: main clock is selected (x in -x out ) 1: sub clock is selected (x cin -x cout ) main clock select bit of oscillation stop detect register (bit 1 at address 000d 16 ) 0: main clock is selected (x in -x out ) 1: clock from ring oscillator is selected table 1.8.3. bclk source and setting bit bclk source system clock select bit main clock select bit (bit 7 of address 0006 16 ) (bit 1 of address 000d 16 ) main clock (x in -x out ) 0 0 sub clock (x cin -x cout ) 1 0 ring oscillator 0 1 when main clock or ring oscillator clock is selected as clock source for bclk, the bclk is the clock derived by dividing the main clock or ring oscillator clock by 1, 2, 3, 4, 6, 8, 10, 12, 14 or 16. main clock divide rate select bit of main clock division register (bit 0 to 4 at address 000c 16 ) the bclk is derived by dividing the main clock (x in -x out ) by 8 after a reset. (main clock division register = "xxx01000 2 ") when main clock is stopped under changing to stop mode or selecting x in -x out (main clock select bit = "0"), the main clock division register is set to the division by 8 ("xxx01000 2 "). when ring oscillator clock is selected as clock source for bclk, although main clock is stoped, the contents of main clock division register is maintained. peripheral function clock main clock, sub clock, pll clock or ring oscillator clock can be selected as clock source for peripheral function. (1) f 1 , f 8 , f 2n the clock is derived from the main clock or by dividing it by 1, 8 or 2n (n=1 to 15). it is used for the timer a and timer b counts and serial i/o and uart operation clock. the f 2n division rate is set by the count source prescaler register. figure 1.8.5 shows the count source prescaler register. (2) f ad this clock has the same frequency as the main clock or ring oscillator clock and is used for a-d conversion. (3) f c32 this clock is derived by dividing the sub clock by 32. it is used for the timer a and timer b counts. (4) f pll this clock is 80 mhz generated by pll synthesizer. it is used for the intelligent i/o group 3. wait mode
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer clock generating circuit 75 clock output you can output clock from the p5 3 pin. ? bclk output function select bit of processor mode register 0 (bit 7 at address 0004 16 ) ? ale select bits of processor mode register 1 (bit 4 and 5 at address 0005 16 ) ? clock output function select bits of system clock select register (bits 1 and 0 at address 0006 16 ) table 1.8.4 shows clock output setting (single chip mode) and table 1.8.5 shows clock output setting (memory expansion/microprocessor mode). table 1.8.4. clock output setting (single chip mode) pm07 cm01 cm00 pm14 p5 3 /bclk/ale/clk out pin function 1 1 1 0 0 1 1 ignored ignored ignored ignored ignored ignored ignored ignored pm15 p5 3 i/o port fc output f 8 output f 32 output bclk output function select bit clock output function select bit ale pin select bit 0 1 0 1 note :must use p5 7 as input port. (note) (note) (note) ignored table 1.8.5. clock output setting (memory expansion/microprocessor mode) 0 1 1 1 0 0 0 1 "0, 0" "1, 0" "1, 1" bclk output "l" output (not p5 3 ) fc output f 8 output 0 0 1 0 11 0 0 1 f 32 output ale output 1 0 pm07 cm01 cm00 pm14 p5 3 /bclk/ale/clk out pin function ignored pm15 bclk output function select bit clock output function select bit ale pin select bit note: the processor mode register 0 and 1 are protected from false write by program run away. set bit 1 to "1" at protect register (address 000a 16 ) and release protect before rewriting processor mode register 0 and 1.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 76 power saving power saving there are three power save modes. figure 1.8.9 shows the clock transition between each of the three modes, (1), (2), and (3). ? normal operating mode cpu and peripheral function operate when supplying clock. power dissipation is reduced by making bclk slow. ? wait mode bclk is stopped. peripheral function clock is stopped as desired. main clock and sub clock isn't stopped. power dissipation is reduced than normal operating mode. ? stop mode (note 1) main clock, sub clock and pll synthesizer are stopped. cpu and peripheral function clock are stopped. power dissipation is the most few in this mode. note :when using stop mode, oscillation stop detect function must be canceled. (1) normal operating mode high-speed mode main clock one cycle forms cpu operating clock. medium-speed mode the main clock divided into 2, 3, 4, 6, 8, 10, 12, 14, or 16 forms cpu operating clock. low-speed mode subclock (fc) forms cpu operating clock. low power-dissipation mode this mode is selected when the main clock is stopped from low-speed mode. only the peripheral functions for which the subclock was selected as the count source continue to run. ring oscillator mode the ring oscillator clock divided into 2, 3, 4, 6, 8, 10, 12, 14, or 16 forms cpu operating clock. ring oscillator low power-dissipation mode this mode is selected when the main clock is stopped from low-speed mode. when switching bclk from ring oscillator to main clock, switch clock after main clock oscillates fully stable. after setting divided by 8 (main clock division register =08 16 ) in ring oscilltor mode, switching to the middle mode (divided by 8) is recommended. (2) wait mode in wait mode, bclk is stopped and cpu and watchdog timer operated by bclk are halted. the main clock, subclock and ring oscillator clock continue to run. (a) shifting to wait mode execute wait instruction. (b) peripheral function clock stop function the f 1 , f 8 and f 2n being supplied to the internal peripheral functions stops. the internal peripheral functions operated by the clock stop.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 77 power saving wait peripheral function clock stop bit of system clock control register 0 (bit 2 at address 0006 16 ) 0: do not stop f 1 , f 8 and f 2n in wait mode and do not stop supplying clock to pll circuit 1: stop f 1 , f 8 and f 2n in wait mode and stop supplying clock to pll circuit (c) the status of the ports in wait mode table 1.8.6 shows the status of the ports in wait mode. (d) exit from wait mode wait mode is cancelled by a hardware reset or interrupt. if a peripheral function interrupt is used to cancel wait mode, set the following registers. interrupt priority set bits for exiting a stop/wait state of exit priority register (bits 0 to 2 at address 009f 16 ) :rlvl0 to rlvl2 set the same level as the flag register (flg) processor interrupt level (ipl). interrupt priority set bits of interrupt control register (bits 0 to 2) set to a priority level above the level set by rlvl0 to rlvl2 bits interrupt enable flag of flg register i = 1 when using an interrupt to exit wait mode, the microcomputer resumes operating the clock that was oper- ating when the wait command was executed as bclk from the interrupt routine. table 1.8.6. port status during wait mode pin memory expansion mode single-chip mode microprocessor mode _______ _______ address bus, data bus, cs0 to cs3, retains status before wait mode ________ bhe _____ ______ ________ _________ ______ _________ ________ rd, wr, wrl, wrh, dw, casl, cash h (note) ________ ras h (note) __________ hlda,bclk h ale l port retains status before wait mode clk out when f c selected does not stop when f 8 , f 32 selected does not stop when the wait peripheral function clock stop bit is 0 . when the wait peripheral function clock stop bit is 1 , the status immediately prior to entering wait mode is maint ained. ________ ________ note :when self-refresh is done in operating dram control, cas and ras becomes l .
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 78 power saving (3) stop mode all oscillation, main clock, subclock, and pll synthesizer stop in this mode. because the oscillation of bclk and peripheral clock stops in stop mode, peripheral functions such as the a-d converter, timer a and b, serial i/o, intelligent i/o and watchdog timer do not function. the content of the internal ram is retained provided that v cc remains above 2.5v. when changing to stop mode, the main clock division register (000c 16 ) is set to xxx01000 2 (division by 8 mode). (a) changing to stop mode all clock stop control bit of system clock control register 1 (bit 0 at address 0007 16 ) 0: clock on 1: all clocks off (stop mode) before changing to stop mode, set bit 7 of pll control register 0 (address 0376 16 ) to "0" to stop pll. also, set bit 0 of vdc control register for pll (address 0017 16 ) to "1" to turn pll circuit power off. (b) the status of the ports in stop mode table 1.8.7 shows the status of the ports in stop mode. (c) exit from stop mode stop mode is cancelled by a hardware reset or interrupt. if a peripheral function interrupt is used to cancel stop mode, set the following registers. ? interrupt priority set bits for exiting a stop/wait state of exit priority register (bits 0 to 2 at address 009f 16 ) :rlvl0 to rlvl2 set the same level as the flag register (flg) processor interrupt level (ipl). ? interrupt priority set bits of interrupt control register (bits 0 to 2) set to a priority level above the level set by rlvl0 to rlvl2 bits ? interrupt enable flag of flg register i = 1 when exiting from stop mode using peripheral interrupt request, cpu operates the following bclk and the relevant interrupt routine is executed. ? when subclock was set as bclk before changing to stop mode, subclock is set to bclk after cancelled stop mode ? when main clock was set as bclk before changing to stop mode, the main clock division by 8 is set to bclk after cancelled stop mode. table 1.8.7. port status during stop mode pin memory expansion mode single-chip mode microprocessor mode _______ _______ _______ address bus, data bus, cs0 to cs3, bhe retains status before stop mode _____ ______ ________ _________ ______ _________ ________ rd, wr, wrl, wrh, dw, casl, cash h (note) ________ ras h (note) __________ hlda, bclk h ale h port retains status before stop mode clk out when fc selected h when f 8 , f 32 selected retains status before stop mode ________ ________ note :when self-refresh is done in operating dram control, cas and ras becomes l .
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 79 power saving reset middle-speed mode (divided by 8 mode) high-speed / middle-speed mode low-speed/ low power dissipation mode note 1 note 1, 5 note 2, 4 stop mode detect oscillation stop stop mode wait mode note 1 cm10="1" cm10="1" all oscillation is stopped all oscillation is stopped interrupt interrupt interrupt x in oscillation is stopped interrupt wait instruction wait instruction wait instruction interrupt interrupt normal operation mode note 1 :switch clocks after the main clock oscillation is fully stabled. note 2 :switch clocks after oscillation of sub clock is fully stable. note 3 :the main clock division register is set to the division by 8 mode (mcd="08 16 "). note 4 :when changing to low power dissipation mode, the main clock division register is set to the division by 8 mode (mcd="08 16 "). note 5 :low power dissipation mode can not be changed to high-speed / middle-speed mode. note 6 :other oscillation mode cannot be changed to low power dissipation mode. note 3 note 6 ring oscillator / ring oscillator low power dissipation mode cpu operation is stopped wait mode wait mode figure 1.8.9. clock transition
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 80 bclk :f(x in )/8 cm07= 0 mcd= 08 16 main clock is oscillating sub clock is oscillating main clock is oscillating sub clock is stopped note 1: switch clocks after oscillation of main clock is fully stable. note 2: switch clocks after oscillation of sub clock is fully stable. note 3: set the desired division to the main clock division register (mcd). note 4: set to divided by 8 mode (mcd is set to "08 16 "). main clock is oscillating sub clock is stopped cm04= 1 mcd= xx 16 note 1, 3 cm04= 0 bclk :f(x in ) /division rate cm07= 0 mcd= xx 16 note 3 bclk :f(x in ) cm07= 0 mcd= 12 16 high-speed mode middle-speed mode (divided-by-2, 3, 4, 6, 8, 10, 12, 14 and 16 mode) bclk :f(x in ) /division rate cm07= 0 mcd= xx 16 note 3 bclk :f(x in ) cm07= 0 mcd= 12 16 high-speed mode middle-speed mode (divided-by-2, 3, 4, 6, 8, 10, 12, 14 and 16 mode) middle-speed mode (divided-by-8 mode) transition of normal mode cm04= 1 cm05= 0 note 4 bclk :f(x cin ) cm07= 1 low-speed mode bclk :f(x cin ) cm07= 1 main clock is oscillating sub clock is oscillating mcd= xx 16 note 1, 3 cm07= 0 note 1 mcd= xx 16 note 3 cm07= 1 note 2 cm07= 0 note 1 mcd= xx 16 note 3 cm04= 0 low power dissipation mode cm05= 1 please change according to a direction of an arrow. cm07= 1 note 2 cm05= 1 high-speed/middle-speed mode low-speed/low power dissipation mode main clock is stopped sub clock is oscillating cm05= 0 (cm04="1") ring oscillator mode bclk: ring oscillator clock/division rate cm21="1" cm05="1" ring oscillator is selected main clock is oscillating sub clock is oscillating (stopped) ring oscillator low power dissipation mode cm05= 1 cm04="0" ring oscillator/ring oscillator low power dissipation mode ring oscillator is selected main clock is stopped sub clock is stopped bclk: ring oscillator clock/division rate cm21="1" cm05="0" cm21= 1 note 1 cm21= 0 note 1 figure 1.8.10. clock transition power saving
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 81 protection protection the protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. figure 1.8.11 shows the protect register. the following registers are protected by the protect register. (1) registers protected by prc0 (bit 0) ? system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) ? main clock division register (address 000c 16 ) ? oscillation stop detect register (address 000d 16 ) ? pll control register 0 (address 0376 16 ) (2) registers protected by prc1 (bit 1) ? processor mode registers 0 and 1 (addresses 0004 16 and 0005 16 ) ? three-phase pwm control registers 0 and 1 (addresses 0308 16 and 0309 16 ) (3) registers protected by prc2 (bit 2) ? port p9 direction register (address 03c7 16 ) ? function select register a3 (address 03b5 16 ) (4) registers protected by prc3 (bit 3) ? vdc control register for pll (address 0017 16 ) ? vdc control register 0 (address 001f 16 ) if, after 1 (write-enabled) has been written to the prc2, a value is written to any address, the bit automati- cally reverts to 0 (write-inhibited). change port p9 input/output and function select register a3 immedi- ately after setting "1" to prc2. interrupt and dma transfer should not be inserted between instructions. however, the prc0, prc1 and prc3 do not automatically return to 0 after a value has been written to an address. the program must therefore be written to return these bits to 0 .
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 82 protect register symbol address when reset prcr 000a 16 xxxx0000 2 bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 prc1 prc0 prc2 protect bit 1 function protect bit 0 protect bit 2 (note 1) w r nothing is assigned. when write, set 0 . when read, their contents are indeterminate. note 1: writing a value to an address after 1 is written to this bit returns the bit to 0 . other bits do not automatically return to 0 and they must therefore be reset by the program. note 2: user cannot use. writing to vdc control registers 0 and 1 (addresses 001f 16 , 001b 16 ) is enabled so that a careful handling is required. a a a a a a a a enables writing to processor mode registers 0 and 1 (addresses 0004 16 and 0005 16 ) and three- phase pwm control register 0 and 1 (addresses 0308 16 and 0309 16 ) 0 : write-inhibited 1 : write-enabled enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ), main clock division register (address 000c 16 ) , oscillation stop detect register (address 000d 16 ) and pll control register 0 (address 0376 16 ) 0 : write-inhibited 1 : write-enabled enables writing to port p9 direction register ( address 03c7 16 ) and function select register a3 (address 03b5 16 ) 0 : write-inhibited 1 : write-enabled protect bit 3 enables writing to vdc control register for pll ( address 0017 16 ), vdc control register 0 and 1 ( addresses 001f 16 and 001b 16 ) 0 : write-inhibited 1 : write-enabled prc3 (note 2) figure 1.8.11. protect register
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 83 undefined instruction (und instruction) overflow (into instruction) brk instruction brk2 instruction int instruction ? ? ? ? ? ? ? ? ? ? ? ? ? ? software hardware interrupt ? ? ? ? ? ? ? ? ? ? ? reset _______ nmi watchdog timer ocsillation stop detection single step address matched special peripheral i/o *1 *1 peripheral i/o interrupts are generated by the peripheral functions built into the microcomputer system. high-speed interrupt can be used as highest priority in peripheral i/o interrupts. interrupt outline types of interrupts ? maskable interrupt : an interrupt which can be disabled by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt : an interrupt which cannot be disabled by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. figure 1.9.1 lists the types of interrupts. software interrupts software interrupts are generated by some instruction that generates an interrupt request when ex- ecuted. software interrupts are nonmaskable interrupts. (1) undefined-instruction interrupt this interrupt occurs when the und instruction is executed. (2) overflow interrupt this interrupt occurs if the into instruction is executed when the o flag is 1. the following lists the instructions that cause the o flag to change: abs, adc, adcf, add, addx, cmp, cmpx, div, divu, divx, neg, rmpa, sbb, scmpu, sha, sub, subx (3) brk interrupt this interrupt occurs when the brk instruction is executed. (4) brk2 interrupt this interrupt occurs when the brk2 instruction is executed. this interrupt is used exclusively for debugger purposes. you normally do not need to use this interrupt. figure 1.9.1. classification of interrupts
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 84 (5) int instruction interrupt this interrupt occurs when the int instruction is executed after specifying a software interrupt number from 0 to 63. note that software interrupt numbers 7 to 54 and 57 are assigned to peripheral i/o interrupts. this means that by executing the int instruction, you can execute the same interrupt routine as used in peripheral i/o interrupts. the stack pointer used in int instruction interrupt varies depending on the software interrupt number. for software interrupt numbers 0 to 31, the u flag is saved when an interrupt occurs and the u flag is cleared to 0 to choose the interrupt stack pointer (isp) before executing the interrupt sequence. the previous u flag before the interrupt occurred is restored when control returns from the interrupt rou- tine. for software interrupt numbers 32 to 63, such stack pointer switchover does not occur. however, in peripheral i/o interrupts, the u flag is saved when an interrupt occurs and the u flag is cleared to 0 to choose isp. therefore movement of u flag is different by peripheral i/o interrupt or int instruction in software interrupt number 32 to 54 and 57. hardware interrupts there are two types of hardware interrupts; special interrupts and peripheral i/o interrupts. (1) special interrupts special interrupts are nonmaskable interrupts. reset ____________ a reset occurs when the reset pin is pulled low. ______ nmi interrupt ______ this interrupt occurs when the nmi pin is pulled low. watchdog timer interrupt this interrupt is caused by the watchdog timer. ocsillation stop detect interrupt this interrupt is caused by the ocsillation stop detect function. it occurs when detecting the x in ocsillation is stopped. single-step interrupt this interrupt is used exclusively for debugger purposes. these interrupts normally do not need to use this interrupt. a single-step interrupt occurs when the d flag is set (= 1); in this case, an interrupt is generated each time an instruction is executed. address-match interrupt this interrupt occurs when the program's execution address matches the contents of the address match register while the address match interrupt enable bit is set (= 1). this interrupt does not occur if any address other than the start address of an instruction is set in the address match register.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 85 (2) peripheral i/o interrupts a peripheral i/o interrupt is generated by one of the built-in peripheral functions. built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. the interrupt vector table is the same as the one for software interrupt numbers 7 through 54 and 57 the int instruction uses. peripheral i/o interrupts are maskable interrupts. uart related interrupt (uart0 to 4) - uart transmission/nack interrupt - uart reception/ack interrupt - bus collision detection, start/stop condition detection interrupts this is an interrupt that the serial i/o bus collision detection generates. when i 2 c mode is selected, start, stop condition interrupt is selected. dma0 through dma3 interrupts key-input interrupt ___ a key-input interrupt occurs if an l is input to the ki pin. a-d conversion interrupt (ad0, 1) timer a interrupt (ta0 to 4) timer b interrupt (tb0 to 5) _____ _______ ________ int interrupt (int0 to int5 ) _____ _____ an int interrupt selects an edge sense or a level sense. in edge sense, an int interrupt occurs if _____ _____ either a rising edge or a falling edge is input to the int pin. in level sense, an int interrupt occurs if _____ either a "h" level or a "l" level is input to the int pin. intelligent i/o interrupt can interrupt high-speed interrupts high-speed interrupts are interrupts in which the response is executed at 5 cycles and the return is 3 cycles. when a high-speed interrupt is received, the flag register (flg) and program counter (pc) are saved to the save flag register (svf) and save pc register (svp) and the program is executed from the address shown in the vector register (vct). execute an freit instruction to return from the high-speed interrupt routine. high-speed interrupts can be set by setting 1 in the high-speed interrupt specification bit allocated to bit 3 of the exit priority register. setting 1 in the high-speed interrupt specification bit makes the interrupt set to level 7 in the interrupt control register a high-speed interrupt. you can only set one interrupt as a high-speed interrupt. when using a high-speed interrupt, do not set multiple interrupts as level 7 interrupts. when using high speed interrupt, dma ii cannot be used. the interrupt vector for a high-speed interrupt must be set in the vector register (vct). when using a high-speed interrupt, you can use a maximum of two dmac channels. the execution speed is improved when register bank 1 is used with high speed interrupt register selected by not saving registers to the stack but to the switching register bank. in this case, switch register bank mode for high-speed interrupt routine.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 86 aaaaaaaa aaaaaaaa mid address aaaaaaaa aaaaaaaa low address aaaaaaaa aaaaaaaa high address aaaaaaaa aaaaaaaa 0 0 16 vector address + 0 vector address + 1 vector address + 2 vector address + 3 lsb msb interrupts and interrupt vector tables if an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. set the first address of the interrupt routine in each vector table. figure 1.9.2 shows the format for specifying the address. two types of interrupt vector tables are available fixed vector table, in which addresses are fixed, and relocatable vector table, in which addresses can be varied by the setting. figure 1.9.2. format for specifying interrupt vector addresses fixed vector tables the fixed vector table is a table in which addresses are fixed. the vector tables are located in an area extending from ffffdc 16 to ffffff 16 . each vector comprises four bytes. set the first address of interrupt routine in each vector table. table 1.9.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. table 1.9.1. interrupt factors (fixed interrupt vector addresses) interrupt source vector table addresses remarks address (l) to address (h) undefined instruction ffffdc 16 to ffffdf 16 interrupt on und instruction overflow ffffe0 16 to ffffe3 16 interrupt on into instruction brk instruction ffffe4 16 to ffffe7 16 if contents of ffffe7 16 is filled with ff 16 , program execution starts from the address shown by the vector in the relocatable vector table address match ffffe8 16 to ffffeb 16 there is an address-matching interrupt enable bit watchdog timer fffff0 16 to fffff3 16 share it with watchdog timer and oscillation stop detect interrupt _______ nmi fffff8 16 to fffffb 16 _______ external interrupt by input to nmi pin reset fffffc 16 to ffffff 16
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 87 vector table dedicated for emulator table 1.9.2 shows interrupt vector address, which is vector table register dedicated for emulator (ad- dress 000020 16 to 000022 16 ). these instructions are not effected with interrupt enable flag (i flag) (non maskable interrupt). this interrupt is used exclusively for debugger purposes. you normally do not need to use this inter- rupt. do not access the interrupt vector table register dedicated for emulator (address 000020 16 to 000022 16 ). table 1.9.2. interrupt vector table register for emulator interrupt source vector table addresses remarks address (l) to address (h) brk2 instruction interrupt vector table register for emulator interrupt for debugger single step 000020 16 to 000022 16 relocatable vector tables the addresses in the relocatable vector table can be modified, according to the user s settings. indi- cate the first address using the interrupt table register (intb). the 256-byte area subsequent to the address the intb indicates becomes the area for the relocatable vector tables. one vector table comprises four bytes. set the first address of the interrupt routine in each vector table. table 1.9.3 shows the interrupts assigned to the relocatable vector tables and addresses of vector tables. set an even address to the start address of vector table setting in intb so that operating efficiency is increased.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 88 table 1.9.3. interrupt causes (variable interrupt vector addresses) (1/2) softwear interrupt number vector table address interrutp source address(l)to address(h) (note 1) softwear interrupt number 0 (note 2) +0 to +3 (0000 16 to 0003 16 ) brk instruction softwear interrupt number 7 +28 to +31 (001c 16 to 001f 16 ) a-d channel 1 softwear interrupt number 8 +32 to +35 (0020 16 to 0023 16 ) dma0 softwear interrupt number 9 +36 to +39 (0024 16 to 0027 16 ) dma1 softwear interrupt number 10 +40 to +43 (0028 16 to 002b 16 ) dma2 softwear interrupt number 11 +44 to +47 (002c 16 to 002f 16 ) dma3 softwear interrupt number 12 +48 to +51 (0030 16 to 0033 16 ) timer a0 softwear interrupt number 13 +52 to +55 (0034 16 to 0037 16 ) timer a1 softwear interrupt number 14 +56 to +59 (0038 16 to 003b 16 ) timer a2 softwear interrupt number 15 +60 to +63 (003c 16 to 003f 16 ) timer a3 softwear interrupt number 16 +64 to +67 (0040 16 to 0043 16 ) timer a4 softwear interrupt number 17 +68 to +71 (0044 16 to 0047 16 ) uart0 transmit/nack (note 3) softwear interrupt number 18 +72 to +75 (0048 16 to 004b 16 ) uart0 receive/ack (note 3) softwear interrupt number 19 +76 to +79 (004c 16 to 004f 16 ) uart1 transmit/nack (note 3) softwear interrupt number 20 +80 to +83 (0050 16 to 0053 16 ) uart1 receive/ack (note 3) softwear interrupt number 21 +84 to +87 (0054 16 to 0057 16 ) timer b0 softwear interrupt number 22 +88 to +91 (0058 16 to 005b 16 ) timer b1 softwear interrupt number 23 +92 to +95 (005c 16 to 005f 16 ) timer b2 softwear interrupt number 24 +96 to +99 (0060 16 to 0063 16 ) timer b3 softwear interrupt number 25 +100 to +103 (0064 16 to 0067 16 ) timer b4 softwear interrupt number 26 +104 to +107 (0068 16 to 006b 16 ) int5 softwear interrupt number 27 +108 to +111 (006c 16 to 006f 16 ) int4 softwear interrupt number 28 +112 to +115 (0070 16 to 0073 16 ) int3 softwear interrupt number 29 +116 to +119 (0074 16 to 0077 16 ) int2 softwear interrupt number 30 +120 to +123 (0078 16 to 007b 16 ) int1 softwear interrupt number 31 +124 to +127 (007c 16 to 007f 16 ) int0 softwear interrupt number 32 +128 to +131 (0080 16 to 0083 16 ) timer b5 softwear interrupt number 33 +132 to +135 (0084 16 to 0087 16 ) uart2 transmit/nack (note 3) softwear interrupt number 34 +136 to +139 (0088 16 to 008b 16 ) uart2 receive/ack (note 3) softwear interrupt number 35 +140 to +143 (008c 16 to 008f 16 ) uart3 transmit/nack (note 3) softwear interrupt number 36 +144 to +147 (0090 16 to 0093 16 ) uart3 receive/ack (note 3) softwear interrupt number 37 +148 to +151 (0094 16 to 0097 16 ) uart4 transmit/nack (note 3) softwear interrupt number 38 +152 to +155 (0098 16 to 009b 16 ) uart4 receive/ack (note 3) softwear interrupt number 39 +156 to +159 (009c 16 to 009f 16 ) bus collision detection, start/stop condition detection (uart2) (note 3) softwear interrupt number 40 +160 to +163 (00a0 16 to 00a3 16 ) bus collision detection, start/stop condition detection (uart3/uart0) (note 3) softwear interrupt number 41 +164 to +167 (00a4 16 to 00a7 16 ) bus collision detection, start/stop condition detection (uart4/uart1) (note 3) softwear interrupt number 42 +168 to +171 (00a8 16 to 00ab 16 ) a-d channel 0 softwear interrupt number 43 +172 to +175 (00ac 16 to 00af 16 ) key input interrupt softwear interrupt number 44 +176 to +179 (00b0 16 to 00b3 16 ) intelligent i/o interrupt 0 softwear interrupt number 45 +180 to +183 (00b4 16 to 00b7 16 ) intelligent i/o interrupt 1 softwear interrupt number 46 +184 to +187 (00b8 16 to 00bb 16 ) intelligent i/o interrupt 2 softwear interrupt number 47 +188 to +191 (00bc 16 to 00bf 16 ) intelligent i/o interrupt 3 softwear interrupt number 48 +192 to +195 (00c0 16 to 00c3 16 ) intelligent i/o interrupt 4 softwear interrupt number 49 +196 to +199 (00c4 16 to 00c7 16 ) intelligent i/o interrupt 5 softwear interrupt number 50 +200 to +203 (00c8 16 to 00cb 16 ) intelligent i/o interrupt 6 softwear interrupt number 51 +204 to +207 (00cc 16 to 00cf 16 ) intelligent i/o interrupt 7 softwear interrupt number 52 +208 to +211 (00d0 16 to 00d3 16 ) intelligent i/o interrupt 8 softwear interrupt number 53 +212 to +215 (00d4 16 to 00d7 16 ) intelligent i/o interrupt 9/can interrupt 0 softwear interrupt number 54 +216 to +219 (00d8 16 to 00db 16 ) intelligent i/o interrupt 10/can interrupt 1
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 89 table 1.9.3. interrupt causes (variable interrupt vector addresses) (2/2) softwear interrupt number vector table address interrutp source address(l)to address(h) (note 1) softwear interrupt number 55 +220 to +223 (00dc 16 to 00df 16 ) softwea interrupt softwear interrupt number 56 +224 to +227 (00e0 16 to 00e3 16 ) softwea interrupt softwear interrupt number 57 +228 to +231 (00e4 16 to 00e7 16 ) intelligent i/o interrupt 11/can interrupt 2 softwear interrupt number 58 (note 2) +232 to +235 (00e8 16 to 00eb 16 ) softwea interrupt to to softwear interrupt number 63 +252 to +255 (00fc 16 to 00ff 16 ) note 1: address relative to address in interrupt table register (intb). note 2: cannot be masked by i flag. note 3: when iic mode is selected, nack/ack, start/stop condition detection interrupts are selected. the fault error ____ interrupt is selected when ss pin is selected. interrupt request reception the following lists the conditions under which an interrupt request is acknowledged: ? interrupt enable flag (i flag) = 1 ? interrupt request bit = 1 ? interrupt priority level > processor interrupt priority level (ipl) the interrupt enable flag (i flag), the processor interrupt priority level (ipl), interrupt request bit and interrupt priority level select bit are all independent of each other, so they do not affect any other bit. there are i flag and ipl in flag register (flg). this flag and bit are described below. interrupt enable flag (i flag) and processor interrupt priority level (ipl) i flag is used to disable/enable maskable interrupts. when this flag is set (= 1), all maskable interrupts are enabled; when the flag is cleared to 0, they are disabled. this flag is automatically cleared to 0 after a reset. ipl is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than the processor interrupt priority level (ipl), the interrupt is enabled. table 1.9.4 shows interrupt enable levels in relation to the processor interrupt priority level (ipl). table 1.9.4. ipl and interrupt enable levels processor interrupt priority level (ipl) enabled interrupt priority levels ipl 2 ipl 1 ipl 0 0 0 0 interrupt levels 1 and above are enabled. 0 0 1 interrupt levels 2 and above are enabled. 0 1 0 interrupt levels 3 and above are enabled. 0 1 1 interrupt levels 4 and above are enabled. 1 0 0 interrupt levels 5 and above are enabled. 1 0 1 interrupt levels 6 and above are enabled. 1 1 0 interrupt levels 7 and above are enabled. 1 1 1 all maskable interrupts are disabled.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 90 interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a aa aa aa aa bit name function bit symbol w r symbol address when reset taiic(i=0 to 4) 006c 16 , 008c 16 , 006e 16 , 008e 16 , 0070 16 xxxxx000 2 tbiic(i=0 to 5) 0094 16 , 0076 16 , 0096 16 , 0078 16 , 0098 16 , 0069 16 xxxxx000 2 sitic(i=0 to 4) 0090 16 , 0092 16 , 0089 16 , 008b 16 , 008d 16 xxxxx000 2 siric(i=0 to 4) 0072 16 , 0074 16 , 006b 16 , 006d 16 , 006f 16 xxxxx000 2 bcniic(i=0 to 4) 0071 16 , 0091 16 , 008f 16 , 0071 16 (note 1) , 0091 16 (note 2) xxxxx000 2 dmiic(i=0 to 3) 0068 16 , 0088 16 , 006a 16 , 008a 16 xxxxx000 2 adiic(i=0,1) 0073 16 , 0086 16 xxxxx000 2 kupic (i=0) 0093 16 xxxxx000 2 iioiic(i=0 to 5) 0075 16 , 0095 16 , 0077 16 , 0097 16 , 0079 16 , 0099 16 xxxxx000 2 iioiic(i=6 to 11) 007b 16 , 009b 16 , 007d 16 , 009d 16 , 007f 16 , 0081 16 xxxxx000 2 caniic(i=0 to 2) 009d 16 , 007f 16 , 0081 16 xxxxx000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 nothing is assigned. when write, set "0". when read, their contents are indeterminate. (note 3) note 1: uart0 bus collision and start/stop condition detection interrupt control register is shared with uart3. note 2: uart1 bus collision and start/stop condition detection interrupt control register is shared with uart4. note 3: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 aa aa aa aa aa aa aa aa aa aa figure 1.9.3. interrupt control register (1) interrupt control registers and exit priority register peripheral i/o interrupts have their own interrupt control registers. figure 1.9.3 and 1.9.4 show the interrupt control registers and figure 1.9.5 shows exit priority register.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 91 symbol address when reset intiic(i=0 to 2) 009e 16 , 007e 16 , 009c 16 xx00 x000 2 intiic(i=3 to 5)(*1) 007c 16 , 009a 16 , 007a 16 xx00 x000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa ilvl0 ir pol nothing is assigned. when write, set "0". when read, their contents are indeterminate. interrupt priority level select bit interrupt request bit polarity select bit level sense/edge sense select bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge or l level 1 : selects rising edge or h level ilvl1 ilvl2 note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: when related bit of external interrupt cause select register (address 031f 16 ) are used for both edge, select the falling edge (=0). note 3: when level sense is selected, set related bit of external interrupt cause select register (address 031f 16 ) to one edge. (note 1) interrupt control register 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 a a a a a a a a a a a a a a 0 : edge sense 1 : level sense lvs (note 2) (note 3) *1 when using 16-bit data bus width in microprocessor mode or memory expansion mode, int3 to int5 are used for data bus. in this case, set the interrupt disabled to int3ic, int4ic and int5ic. figure 1.9.4. interrupt control register (2) bit 0 to 2: interrupt priority level select bits (ilvl0 to ilvl2) interrupt priority levels are set by ilvl0 to ilvl2 bits. when an interrupt request is generated, the interrupt priority level of this interrupt is compared with ipl. this interrupt is enabled only when its interrupt priority level is greater than ipl. this means that you can disable any particular interrupt by setting its interrupt priority level to 0. bit 3: interrupt request bit (ir) this bit is set (= 1) by hardware when an interrupt request is generated. the bit is cleared (= 0) by hardware when the interrupt request is acknowledged and jump to the interrupt vector. this bit can be cleared (= 0) (but never be set to 1) in software.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 92 exit priority register when reset xx0x0000 2 address 009f 16 symbol rlvl rw rlvl0 rlvl1 rlvl2 interrupt priority set bits for exiting stop/wait state (note 1) fsit high-speed interrupt set bit (note 2) 0: interrupt priority level 7 = normal interrupt 1: interrupt priority level 7 = high-speed interrupt dma ii dma ii select bit (note 3) 0: interrupt priority level 7 = normal interrupt or high-speed interrupt 1: interrupt priority level 7 = dma ii transfer nothing is assigned. when write, set "0". when read, its content is indeterminate. nothing is assigned. when write, set "0". when read, their contents are indeterminate. 0 0 0 : level 0 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 note 1: exits the stop or wait mode when the requested interrupt priority level is higher than that set in the exit priority register. set to the same value as the processor interrupt priority level (ipl) set in the flag register (flg). note 2: the high-speed interrupt can only be specified for interrupts with interrupt priority level 7. specify interrupt priority level 7 for only one interrupt. note 3: do not set this bit to 0 after once setting it to 1. when this bit is 1, do not set the high-speed interrupt select bit to 0. (this cannot be used simultaneously with the high-speed interrupt.) transfers by dmac ii are unaffected by the interrupt enable flag (i flag) and processor interrupt priority level (ipl). figure 1.9.5. exit priority register bit 0 to 2: interrupt priority set bits for exiting stop/wait state (rlvl0 to rlvl2) when using an interrupt to exit stop mode or wait mode, the relevant interrupt must be enabled and set to a priority level above the level set by the rlvl0 to rlvl2 bits. set the rlvl0 to rlvl2 bits to the same level as the flag register (flg) ipl.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 93 interrupt sequence an interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the scmpu, sin, smovb, smovf, smovu, sstr, sout or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. in the interrupt sequence, the processor carries out the following in sequence given: (1) cpu gets the interrupt information (the interrupt number and interrupt request level) by reading address 000000 16 (address 000002 16 when high-speed interrupt). after this, the related interrupt request bit is "0". (2) saves the contents of the flag register (flg) immediately before the start of interrupt sequence in the temporary register (note) within the cpu. (3) sets the interrupt enable flag (i flag), the debug flag (d flag), and the stack pointer select flag (u flag) to 0 (the u flag, however does not change if the int instruction, in software interrupt numbers 32 through 63, is executed) (4) saves the contents of the temporary register (note) within the cpu in the stack area. saves in the flag save register (svf) in high-speed interrupt. (5) saves the content of the program counter (pc) in the stack area. saves in the pc save register (svp) in high-speed interrupt. (6) sets the interrupt priority level of the accepted instruction in the ipl. after the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. note: this register cannot be utilized by the user. interrupt response time 'interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. this time comprises the period from the occur- rence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). figure 1.9.6 shows the interrupt response time. figure 1.9.6. interrupt response time (a) the period from the occurrence of an interrupt to the completion of the instruction under execution. (b) the time required for executing the interrupt sequence. (a) (b) time instruction interrupt response time instruction in interrupt routine interrupt sequence interrupt request acknowledged interrupt request generated
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 94 time (a) varies with each instruction being executed. the divx instruction requires a maximum time of 29* cycles. time (b) is shown in table 1.9.5. * it is when the divisor is immediate or register. when the divisor is memory, the following value is added. ? normal addressing : 2 + x ? index addressing : 3 + x ? indirect addressing : 5 + x + 2y ? indirect index addressing : 6 + x + 2y x is number of wait of the divisor area. y is number of wait of the indirect address stored area. when x and y are in odd address or in 8 bit bus area, double the value of x and y. table 1.9.5 interrupt sequence execution time note 1: allocate interrupt vector addresses in even addresses as much as possible. note 2: the vector table is fixed to even address. note 3: the high-speed interrupt is independent of these conditions. 8 bits data bus 16 cycles 16 cycles 14 cycles 14 cycles 15 cycles 16 cycles 19 cycles 19 cycles 21 cycles 16 bits data bus 14 cycles 16 cycles 12 cycles 14 cycles 13 cycles 14 cycles 17 cycles 19 cycles 19 cycles interrupt vector address even address odd address (note 1) even address odd address (note 1) even address (note 2) even address (note 2) even address odd address (note 1) even address (note 2) vector table is internal register interrupt peripheral i/o int instruction _______ nmi watchdog timer undefined instruction address match overflow brk instruction (relocatable vector table) single step brk2 instruction brk instruction (fixed vector table) high-speed interrupt (note 3) 5 cycles
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 95 value that is set to ipl 7 0 not changed figure 1.9.7. stack status before and after an interrupt request is acknowledged changes of ipl when interrupt request acknowledged when an interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is set to the processor interrupt priority level (ipl). if an interrupt request is acknowledged that does not have an interrupt priority level, the value shown in table 1.9.6 is set to the ipl. table 1.9.6 relationship between interrupts without interrupt priority levels and ipl interrupt sources without interrupt priority levels _______ watchdog timer, nmi reset other saving registers in an interrupt sequence, only the contents of the flag register (flg) and program counter (pc) are saved to the stack area. the order in which these contents are saved are as follows: first, the flg register is saved to the stack area. next, the 16 high-order bits and 16 low-order bits of the program counter expanded to 32-bit are saved. figure 1.9.7 shows the stack status before an interrupt request is acknowledged and the stack status after an interrupt request is acknowledged. in a high-speed interrupt sequence, the contents of the flag register (flg) are saved to the flag save register (svf) and program counter (pc) are saved to pc save register (svp). if there are any other registers you want to be saved, save them in software at the beginning of the interrupt routine. the pushm instruction allows you to save all registers except the stack pointer (sp) by a single instruction. in high speed interrupt, switch register bank, then register bank 1 is used as high speed interrupt register. in this case, switch register bank mode for high-speed interrupt routine. [sp] stack pointer value before interrupt occurs stack status before interrupt request is acknowledged address stack status after interrupt request is acknowledged m-6 m-5 m C 4 m C 3 m C 2 m C 1 m m+1 lsb msb lsb msb address stack area stack area flag register (flg l ) program counter (pc h ) flag register (flg h ) content of previous stack content of previous stack content of previous stack content of previous stack program counter (pc l ) program counter (pc m ) [sp] new stack pointer value m-6 m-5 m C 4 m C 3 m C 2 m C 1 m m+1 0 0
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 96 return from interrupt routine as you execute the reit instruction at the end of the interrupt routine, the contents of the flag register (flg) and program counter (pc) that have been saved to the stack area immediately preceding the interrupt sequence are automatically restored. in high-speed interrupt, as you execute the freit in- struction at the end of the interrupt routine, the contents of the flag register (flg) and program counter (pc) that have been saved to the save registers immediately preceding the interrupt sequence are auto- matically restored. then control returns to the routine that was under execution before the interrupt request was acknowl- edged, and processing is resumed from where control left off. if there are any registers you saved via software in the interrupt routine, be sure to restore them using an instruction (e.g., popm instruction) before executing the reit or freit instruction. when switching the register bank before executing reit and freit instruction, switched to the register bank immediately before the interrupt sequence. interrupt priority if two or more interrupt requests are sampled active at the same time, the interrupt with the highest priority will be acknowledged. maskable interrupts (peripheral i/o interrupts) can be assigned any desired priority by setting the inter- rupt priority level select bit accordingly. if some maskable interrupts are assigned the same priority level, the priority between these interrupts are resolved by the priority that is set in hardware. certain nonmaskable interrupts such as a reset (reset is given the highest priority) and watchdog timer interrupt have their priority levels set in hardware. figure 1.9.8 lists the hardware priority levels of these interrupts. software interrupts are not subjected to interrupt priority. they always cause control to branch to an interrupt routine whenever the relevant instruction is executed. interrupt resolution circuit interrupt resolution circuit selects the highest priority interrupt when two or more interrupt requests are sampled active at the same time. figure 1.9.9 shows the interrupt resolution circuit. _______ reset > nmi > watchdog > peripheral i/o > single step > address match figure 1.9.8. interrupt priority that is set in hardware
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 97 timer b2 timer b0 timer a0 timer a1 timer b1 uart1 reception/ack uart0 reception/ack intelligent i/o interrupt 1 a-d0 conversion uart1 transmission/nack uart0 transmission/nack intelligent i/o interrupt 0 key input interrupt processor interrupt priority level (ipl) interrupt enable flag (i flag) watchdog timer reset dbc nmi interrupt request accepted. to cpu level 0 (initial value) priority level of each interrupt high low priority of peripheral i/o interrupts (if priority levels are same) uart2 reception/ack address match timer b4 timer b3 dma0 dma1 dma2 dma3 timer a2 timer a3 timer a4 uart2 transmission/nack uart3 reception/ack uart3 transmission/nack uart4 reception/ack uart4 transmission/nack bus collision/start, stop condition/fault error (uart0,3) bus collision/start, stop condition/fault error (uart1,4) instruction fetch stop/wait return interrupt level (rlvl) interrupt request accepted. to clk a-d1 conversion bus collision/start, stop condition(uart2) intelligent i/o interrupt 2 intelligent i/o interrupt 3 intelligent i/o interrupt 4 intelligent i/o interrupt 5 intelligent i/o interrupt 6 intelligent i/o interrupt 7 intelligent i/o interrupt 8 intelligent i/o interrupt 9 /can interrupt 0 intelligent i/o interrupt 10 /can interrupt 1 intelligent i/o interrupt 11 /can interrupt 2 int3 int5 int4 int1 int2 int0 timer b5 figure 1.9.9. interrupt resolution circuit
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 98 external interrupt request cause select register bit name function bit symbol w r symbol address when reset ifsr 031f 16 00 16 ifsr0 b7 b6 b5 b4 b3 b2 b1 b0 a aa aa a int0 interrupt polarity select bit (note) 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges int1 interrupt polarity select bit (note) int2 interrupt polarity select bit (note) int3 interrupt polarity select bit (note) int4 interrupt polarity select bit (note) int5 interrupt polarity select bit (note) 0 : one edge 1 : both edges ifsr1 ifsr2 ifsr3 ifsr4 ifsr5 aa aa a a aa aa a a aa a aa a aa a aa a note :when level sense is selected, set this bit to "0". when both edges are selected, set the corresponding polarity switching bit of int interrupt control register to "0" (falling edge). 0 : uart3 bus collision /start,stop detect/false error detect 1 : uart0 bus collision /start,stop detect/false error detect uart0/3 interrupt cause select bit uart1/4 interrupt cause select bit ifsr6 ifsr7 aa aa a a aa aa a a 0 : uart4 bus collision /start,stop detect/false error detect 1 : uart1 bus collision /start,stop detect/false error detect ______ int interrupts ________ ________ int0 to int5 are external input interrupts. the level sense/edge sense switching bits of the interrupt control register select the input signal level and edge at which the interrupt can be set to occur on input signal level and input signal edge. the polarity bit selects the polarity. with the external interrupt input edge sense, the interrupt can be set to occur on both rising and falling edges by setting the inti interrupt polarity switch bit of the interrupt request select register (address 031f 16 ) to 1 . when you select both edges, set the polarity switch bit of the corresponding interrupt control register to the falling edge ( 0 ). when you select level sense, set the inti interrupt polarity switch bit of the interrupt request select register (address 031f 16 ) to 0 . figure 1.9.10 shows the interrupt request select register. figure 1.9.10. external interrupt request cause select register
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 99 interrupt control circuit key input interrupt control register (address 0093 16 ) key input interrupt request p10 7 /ki 3 p10 6 /ki 2 p10 5 /ki 1 p10 4 /ki 0 port p10 4 -p10 7 pull-up select bit port p10 7 direction register pull-up transistor port p10 7 direction register port p10 6 direction register port p10 5 direction register port p10 4 direction register pull-up transistor pull-up transistor pull-up transistor ______ nmi interrupt ______ ______ ______ an nmi interrupt is generated when the input to the p8 5 /nmi pin changes from h to l . the nmi interrupt is a non-maskable external interrupt. the pin level can be checked in the port p8 5 register (bit 5 at address 03c4 16 ). this pin cannot be used as a normal port input. notes: ______ ______ ______ when not intending to use the nmi function, be sure to connect the nmi pin to v cc (pulled-up). the nmi interrupt is non-maskable. because it cannot be disabled, the pin must be pulled up. key input interrupt if the direction register of any of p10 4 to p10 7 is set for input and a falling edge is input to that port, a key input interrupt is generated. a key input interrupt can also be used as a key-on wakeup function for cancel- ling the wait mode or stop mode. however, if you intend to use the key input interrupt, do not use p10 4 to p10 7 as a-d input ports. figure 1.9.11 shows the block diagram of the key input interrupt. note that if an l level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. setting the key input interrupt disable bit (bit 7 at address 03af 16 ) to 1 disables key input interrupts from occurring, regardless of the setting in the interrupt control register. when 1 is set in the key input interrupt disable register, there is no input via the port pin even when the direction register is set to input. figure 1.9.11. block diagram of key input interrupt
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 100 bit name bit symbol symbol address when reset aier 0009 16 xxxx0000 2 address match interrupt enable register function w r aaaaaaaaaaaaaa a aaaaaaaaaaaa a aaaaaaaaaaaaaa aaaaaaaaaaaaaa a aaaaaaaaaaaa a aaaaaaaaaaaaaa address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 aaaaaaaaaaaaaa aaaaaaaaaaaaaa symbol address when reset rmad0 0012 16 to 0010 16 000000 16 rmad1 0016 16 to 0014 16 000000 16 rmad2 001a 16 to 0018 16 000000 16 rmad3 001e 16 to 001c 16 000000 16 nothing is assigned. when write, set "0". when read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 w r address setting register for address match interrupt function values that can be set address match interrupt register i (i = 0, 1) 000000 16 to ffffff 16 0 : interrupt disabled 1 : interrupt enabled b0 b7 b0 (b16) b7 b0 (b15) (b8) b7 (b23) aa a aa a aa a aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa address match interrupt 2 enable bit 0 : interrupt disabled 1 : interrupt enabled aier2 address match interrupt 3 enable bit aier3 0 : interrupt disabled 1 : interrupt enabled aa a aa aa a a address match interrupt an address match interrupt is generated when the address match interrupt address register contents match the program counter value. four address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. address match interrupts are not affected by the inter- rupt enable flag (i flag) and processor interrupt priority level (ipl). figure 1.9.12 shows the address match interrupt-related registers. set the start address of an instruction to the address match interrupt register. address match interrupt is not generated when address such as the middle of instruction or table data is set. figure 1.9.12. address match interrupt-related registers
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 101 interrupt request bit aaa aaa aaa aaa aaa aaa aaa aaa aaa interrupt request a dq r interrupt enable bit a write "0" to interrupt request flag a interrupt request b dq r interrupt enable bit b write "0" to interrupt request flag b interrupt request n dq r interrupt enable bit n write "0" to interrupt request flag n interrupt request flag n=a to l "0" "1" "0" "1" "0" "1" interrupt request latch bit dq r cleared when an interrupt request received intelligent i/o and can interrupt group 0 to 3 intelligent i/o interrupts and can interrupt are assigned to software interrupt numbers 44 to 54 and 57. as intelligent i/o interrupt request, there are base timer interrupt request signals, time measurement inter- rupt request signals, waveform generation interrupt request signals and interrupt request signals from vari- ous communication circuits. figure 1.9.13 shows the intelligent i/o interrupts and can interrupt block diagram, figure 1.9.14 shows the interrupt request register and figure 1.9.15 shows interrupt enable register. figure 1.9.13. intelligent i/o and can interrupt block diagram when using the intelligent i/o or can interrupt as an starting factor for dma ii, the interrupt latch bit must be set to "0" in order to enable only the interrupt request factor used by the interrupt enable register.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 102 function interrupt request register bit name bit symbol address see below when reset 0000 000x 2 symbol iioiir rw (note) (note) (note) (note) (note) (note) (note) 0 : interrupt request not present 1 : interrupt request present irf1 irf2 irf3 interrupt request flag 1 interrupt request flag 2 interrupt request flag 3 0 : interrupt request not present 1 : interrupt request present 0 : interrupt request not present 1 : interrupt request presence irf4 interrupt request flag 4 0 : interrupt request not present 1 : interrupt request present irf5 interrupt request flag 5 0 : interrupt request not present 1 : interrupt request present irf6 irf7 interrupt request flag 6 interrupt request flag 7 0 : interrupt request not present 1 : interrupt request present 0 : interrupt request not present 1 : interrupt request present note: "0" can be written. nothing is assigned. when write, set "0". when read, the content is indeterminate. symbol iio0ir iio1ir iio2ir iio3ir iio4ir iio5ir iio6ir iio7ir iio8ir iio9ir iio10ir iio11ir address 00a0 16 00a1 16 00a2 16 00a3 16 00a4 16 00a5 16 00a6 16 00a7 16 00a8 16 00a9 16 00aa 16 00ab 16 bit7 (irf7) bit6 (irf6) bit5 (irf5) bit4 (irf4) bit3 (irf3) bit2 (irf2) bit1 (irf1) - - - - bean0 - - ie0 ie1 can0 can1 can2 - - - - bean1 - - - ie2 - - - sio0r sio0t sio1r sio1t - - - - - - - - g0ri g0to g1ri g1to bt1 sio2r sio2t bt0 bt2 - - bt3 - - - po27 po32 po33 po34 po35 po36 po31 po30 po37 po13 po14 tm12/po12 po10 tm17/po17 po21 po20 po22 po23 po24 po25 po26 tm02 tm00/po00 - tm03 tm04/po04 tm05/po05 tm06 tm07 tm11/po11 po15 tm16/po16 tm01/po01 interrupt request register table bti tmij poij sioir/sioit gito/giri beani ie cani - : interrupt request from base timer of intelligent i/o group i : interrupt request from time measurement function ch j of intelligent i/o group i : interrupt request from waveform generator function ch j of intelligent i/o group i : interrupt request from communication function of intelligent i/o group i (r:reception, t:transmission) : interrupt request from hdlc data processing function of intelligent i/o group i (ri:reception input, to:transmission output) : interrupt request from special communication function of intelligent i/o group i (i=0,1) : interrupt request from iebus communication function of intelligent i/o group 2 : interrupt request from an communication function (i=0 to 2) : nothing is assigned in this bit. - - - - - - - - - - - - bit0 - b7 b6 b5 b4 b3 b2 b1 b0 figure 1.9.14. interrupt request registers bit 1 to bit 7: interrupt request flag (irf1 to irf7) to retain respective interrupt requests and judge interrupt kind occurred in the interrupt process rou- tine.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 103 function interrupt enable register bit name bit symbol address see below when reset 00 16 symbol iioiie rw 0: interrupt of corresponding interrupt request flag (irf2) disabled 1: interrupt of corresponding interrupt request flag (irf2) enabled ite1 irlt ite2 ite3 interrupt enable bit 1 interrupt enable bit 2 interrupt enable bit 3 0: interrupt of corresponding interrupt request flag (irf1) disabled 1: interrupt of corresponding interrupt request flag (irf1) enabled 0: interrupt of corresponding interrupt request flag (irf3) disabled 1: interrupt of corresponding interrupt request flag (irf3) enabled ite4 interrupt enable bit 4 0: interrupt of corresponding interrupt request flag (irf4) disabled 1: interrupt of corresponding interrupt request flag (irf4) enabled ite5 interrupt enable bit 5 0: interrupt of corresponding interrupt request flag (irf5) disabled 1: interrupt of corresponding interrupt request flag (irf5) enabled ite6 ite7 interrupt enable bit 6 interrupt enable bit 7 0: interrupt of corresponding interrupt request flag (irf6) disabled 1: interrupt of corresponding interrupt request flag (irf6) enabled 0: interrupt of corresponding interrupt request flag (irf7) disabled 1: interrupt of corresponding interrupt request flag (irf7) enabled symbol iio0ie iio1ie iio2ie iio3ie iio4ie iio5ie iio6ie iio7ie iio8ie iio9ie iio10ie iio11ie address 00b0 16 00b1 16 00b2 16 00b3 16 00b4 16 00b5 16 00b6 16 00b7 16 00b8 16 00b9 16 00ba 16 00bb 16 bit7 (ite7) bit6 (ite6) bit5 (ite5) bit4 (ite4) bit3 (ite3) bit2 (ite2) bit1 (ite1) - - - - bean0 - - ie0 ie1 can0 can1 can2 - - - - bean1 - - - ie2 - - - sio0r sio0t sio1r sio1t - - - - - - - - g0ri g0to g1ri g1to bt1 sio2r sio2t bt0 bt2 - - bt3 - - - po27 po32 po33 po34 po35 po36 po31 po30 po37 po13 po14 tm12/po12 po10 tm17/po17 po21 po20 po22 po23 po24 po25 po26 tm02 tm00/po00 - tm03 tm04/po04 tm05/po05 tm06 tm07 tm11/po11 po15 tm16/po16 tm01/po01 interrupt request register table bti tmij poij sioir/sioit gito/giri beani ie cani - : interrupt request from base timer of intelligent i/o group i is enabled : interrupt request from time measurement function ch j of intelligent i/o group i is enabled : interrupt request from waveform generator function ch j of intelligent i/o group i is enabled : interrupt request from communication function of intelligent i/o group i (r:reception, t:transmission) is enabled : interrupt request from hdlc data processing function of intelligent i/o group i (ri:reception input, to:transmission output) is enabled : interrupt request from special communication function of intelligent i/o group i (i=0,1) is enabled : interrupt request from iebus communication function of intelligent i/o group 2 is enabled : interrupt request from can communication function (i=0 to 2) is enabled : nothing is assigned in this bit. (set "0" to these bits.) interrupt request latch bit 0: interrupt request is not latched(used by dma ii) 1: interrupt request is latched(used by interrupt) bit1 (irlt) irlt irlt irlt irlt irlt irlt irlt irlt irlt irlt irlt irlt b7 b6 b5 b4 b3 b2 b1 b0 figure 1.9.15. interrupt enable registers
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 104 bit 0: interrupt request latch bit (irlt) an interrupt signal or latched signal of the interrupt signal is selected as an interrupt request signal. when the latched signal of an interrupt signal is used, this flag must be set to "0" after interrupt request flag is read in interrupt process routine, . if this flag is not set to "0" and interrupt process is completed, although interrupt request occurs again, interrupt will not occur. bit 1 to bit 7: interrupt enable bit (ite 1 to ite 7) to enable/disable respective interrupts. precautions for interrupts (1) reading addresses 000000 16 and 000002 16 ? when maskable interrupt occurs, cpu reads the interrupt information (the interrupt number and inter- rupt request level) in the interrupt sequence from address 000000 16 . when a high-speed interrupt occurs, cpu reads from address 000002 16 . the interrupt request bit of the certain interrupt will then be set to 0 . however, reading addresses 000000 16 and 000002 16 by software does not set request bit to 0 . (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 000000 16 . accepting an interrupt before setting a value in the stack pointer may cause runaway. be sure to set a value in the stack _______ pointer before accepting an interrupt. when using the nmi interrupt, initialize the stack point at the _______ beginning of a program. any interrupt including the nmi interrupt is generated immediately after ex- ecuting the first instruction after reset. set an even number to the stack pointer. set an even address to the stack pointer so that operating efficiency is increased. _______ (3) the nmi interrupt _______ ? as for the nmi interrupt pin, this interrupt cannot be disabled. connect it to the vcc pin via a pull-up resistor if unused. _______ ? the nmi pin also serves as p8 5 , which is exclusively input. reading the contents of the p8 register allows reading the pin value. use the reading of this pin only for establishing the pin level at the time _______ when the nmi interrupt is input. _______ ? a low level signal with more than 1 clock cycle (bclk) is necessary for nmi pin. (4) external interrupt ? edge sense either a low level or a high level for at least 250 ns is necessary for the signal input to pins int 0 to int 5 regardless of the cpu operation clock. ? level sense either a low level or a high level of 1 cycle of bclk + at least 200 ns width is necessary for the signal input to pins int 0 to int 5 regardless of the cpu operation clock. (when x in =20mhz and no division mode, at least 250 ns width is necessary.)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer interrupts 105 set the polarity select bit clear the interrupt request bit to 0 set the interrupt priority level to level 1 to 7 (enable the accepting of inti interrupt request) set the interrupt priority level to level 0 (disable inti interrupt) ? when the polarity of the int 0 to int 5 pins is changed, the interrupt request bit is sometimes set to "1". after changing the polarity, set the interrupt request bit to "0". figure 1.9.12 shows the procedure for ______ changing the int interrupt generate factor. ______ figure 1.9.16. switching condition of int interrupt request (5) rewrite the interrupt control register ? when an instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset (6) rewrite interrupt request register ? when writing to "0" to this register, the following instructions must be used. instructions : and, bclr
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer watchdog timer 106 watchdog timer the watchdog timer has the function of detecting when the program is out of control. the watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the bclk using the prescaler. whether a watchdog timer interrupt is generated or reset is selected when an underflow occurs in the watchdog timer. watchdog timer interrupt is selected when bit 6 (cm06) of the system control register 0 (address 0008 16 ) is "0" and reset is selected when cm06 is "1". no value other than "1" can be written in cm06. once reset is selected (cm06="1"), watchdog timer interrupt cannot be selected by software. when x in is selected for the bclk, bit 7 (wdc7) of the watchdog timer control register (address 000f 16 ) selects the prescaler division ratio (by 16 or by 128). when x cin is selected as the bclk, the prescaler is set for division by 2 regardless of wdc7. therefore, the watchdog timer cycle can be calculated as follows. however, errors can arise in the watchdog timer cycle due to the prescaler. when x in is selected in bclk watchdog timer cycle = when x cin is selected in bclk watchdog timer cycle = for example, when bclk is 20mhz and the prescaler division ratio is set to 16, the monitor timer cycle is approximately 26.2 ms, and approximately 17.5 ms when bclk is 30mhz. the watchdog timer is initialized by writing to the watchdog timer start register (address 000e 16 ) and when a watchdog timer interrupt request is generated. the prescaler is initialized only when the microcomputer is reset. after a reset is cancelled, the watchdog timer and prescaler are both stopped. the count is started by writing to the watchdog timer start register (address 000e 16 ). cm06 is initialized only at reset. after reset, watchdog timer interrupt is selected. the watchdog timer and the prescaler stop in stop mode, wait mode and hold status. after exiting these modes and status, counting starts from the previous value. in the stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. counting is resumed from the held value when the modes or state are released. figure 1.10.1 shows the block diagram of the watchdog timer. figure 1.10.2 and 1.10.3 show the watchdog timer-related registers. "cm06=0" watchdog timer interrupt request "cm06=1" reset bclk write to the watchdog timer start register (address 000e 16 ) reset watchdog timer set to 7fff 16 1/128 1/16 cm07 = 0 wdc7 = 1 cm07 = 0 wdc7 = 0 cm07 = 1 hold 1/2 prescaler prescaler division ratio (16 or 128) x watchdog timer count (32768) bclk prescaler division ratio (2) x watchdog timer count (32768) bclk figure 1.10.1. block diagram of watchdog timer
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer watchdog timer 107 wdc7 reserved bit prescaler select bit watchdog timer control register high-order bit of watchdog timer 0 : divided by 16 1 : divided by 128 must always be set to "0" symbol address when reset wdc 000f 16 000xxxxx 2 rw bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 watchdog timer start register symbol address when reset wdts 000e 16 indeterminate rw function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to "7fff 16 " regardless of the value written. b7 b0 figure 1.10.2. watchdog timer control and start registers
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer watchdog timer 108 system clock control register 0 (note 1) symbol address when reset cm0 0006 16 0000 x000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p5 3 0 1 : f c output 1 0 : f 8 output 1 1 : f 32 output b1 b0 cm07 cm05 cm04 cm01 cm02 cm00 clock output function select bit (note 2) wait peripheral function clock stop bit 0 : do not stop peripheral clock in wait mode 1 : stop peripheral clock in wait mode (note 3) port x c select bit 0 : i/o port 1 : x cin -x cout generation (note 4) main clock (x in -x out ) stop bit (note 5) 0 : main clock on 1 : main clock off (note 6) system clock select bit (note 8) 0 : x in , x out 1 : x cin , x cout w r a aa a aa a aa a aa a aa a aa a a aa aa cm06 watchdog timer function select bit 0 : watchdog timer interrupt 1 : reset (note 7) nothing is assigned. when write, set "0". when read, their contents are indeterminate. note 1: set bit 0 of the protect register (address 000a 16 ) to 1 before writing to this register. note 2: the port p5 3 dose not function as an i/o port in microprocessor or memory expansion mode. when outputting ale to p5 3 (bits 5 and 4 of processor mode register 0 is "01"), set these bits to "00". the port p5 3 function is not selected, even when you set "00" in microprocessor or memory expansion mode and bit 7 of the processor mode register 0 is "1". note 3: fc 32 is not included. when this bit is set to "1", pll cannot be used in wait. note 4: when xc in -xc out is used, set port p8 6 and p8 7 to no pull-up resistance with the input port. note 5: when entering the power saving mode, the main clock is stopped using this bit. to stop the main clock, set system clock stop bit (cm07) to "1" while an oscillation of sub clock is stable. then set this bit to "1". when x in is used after returning from stop mode, set this bit to "0". when this bit is "1", x out is "h". also, the internal feedback resistance remains on, so x in is pulled up to x out ("h" level) via the feedback resistance. note 6: when the main clock is stopped, the main clock division register (address 000c 16 ) is set to the division by 8 mode. however, in ring oscillator mode, the main clock division register is not set to the division by 8 mode when x in -x out is stopped by this bit. note 7: when "1" has been set once, "0" cannot be written by software. note 8: set this bit "0" to "1" when sub clock oscillation is stable by setting cm04 to "1". set this bit "1" to "0" when main clock oscillation is stable by setting cm05 to "0". do not set cm04 and cm05 simultaneously. figure 1.10.3. system clock control register 0
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dmac 109 dmac this microcomputer has four dmac (direct memory access controller) channels that allow data to be sent to memory without using the cpu. dmac is a function that transmit delete data of a source address (8 bits /16 bits) to a destination address when transmission request occurs. when using three or more dmac channels, the register bank 1 and high-speed interrupt register are used as dmac registers. if you are using three or more dmac channels, you cannot use high-speed interrupts. the cpu and dmac use the same data bus, but the dmac has a higher bus access privilege than the cpu, and because of the use of cycle-steeling, operations are performed at high-speed from the occurrence of a transfer request until one word (16 bits) or 1 byte (8 bits) of data have been sent. figure 1.11.1 shows the mapping of registers used by the dmac. table 1.11.1 shows dmac specifications. figures 1.11.2 to 1.11.5 show the structures of the registers used. as the registers shown in figure 1.11.1 are allocated in the cpu, use ldc instruction when writing. when writing to dct2, dct3, drc2, drc3, dma2 and dma3, set register bank select flag (b flag) to "1" and use mov instruction to set r0 to r3, a0 and a1 registers. when writing to dsa2 and dsa3, set register bank select flag (b flag) to "1" and use ldc instruction to set sb and fb registers. dma mode register 0, 1 dma 0, 1 transfer count register dma 0, 1 transfer count reload register dma 0, 1 memory address register dma 0, 1 sfr address register dma 0, 1 memory address reload register dmd0 dmd1 dct0 dct1 drc0 drc1 dma0 dma1 dsa0 dsa1 dra0 dra1 dmac related registers when using three or more dmac channels the high-speed interrupt register is used as a dmac register dma2 transfer count register dma2 transfer count reload register dma2 memory address register dma2 sfr address register dct2 (r0) dct3 (r1) drc2 (r2) drc3 (r3) dma2 (a0) dma3 (a1) dsa2 (sb) dsa3 (fb) when using dma2 and dma3, use the cpu registers shown in parentheses. when using three or more dmac channels the register bank 1 is used as a dmac register dma3 transfer count register dma3 transfer count reload register dma3 memory address register dma3 sfr address register svf dma2 memory address reload register dra2 (svp) dra1 (vct) flag save register dma3 memory address reload register figure 1.11.1. register map using dmac in addition to writing to the software dma request bit to start dmac transfer, the interrupt request signals output from the functions specified in the dma request factor select bits are also used. however, in contrast to the interrupt requests, repeated dma requests can be received, regardless of the interrupt flag. (note, however, that the number of actual transfers may not match the number of transfer requests if the dma request cycle is shorter than the dmr transfer cycle. for details, see the description of the dmac request bit.)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dmac 110 item specification no. of channels 4 (cycle steal method) transfer memory space ? from any address in the 16 mbytes space to a fixed address (16 mbytes space) ? from a fixed address (16 mbytes space) to any address in the 16 m bytes space maximum no. of bytes transferred 128 kbytes (with 16-bit transfers) or 64 kbytes (with 8-bit transfers) dma request factors (note) ________ ________ falling edge of int0 to int3 or both edge timer a0 to timer a4 interrupt requests timer b0 to timer b5 interrupt requests uart0 to uart4 transmission and reception interrupt requests a-d conversion interrupt requests intelligent i/o interrupt software triggers channel priority dma0 > dma1 > dma2 > dma3 (dma0 is the first priority) transfer unit 8 bits or 16 bits transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) transfer mode ? single transfer transfer ends when the transfer count register is "0000 16 ". ? repeat transfer when the transfer counter is "0000 16 ", the value in the transfer counter reload register is reloaded into the transfer counter and the dma transfer is continued dma interrupt request generation timing when the transfer counter register changes from "0001 16 " to "0000 16 ". dma startup ? single transfer transfer starts when dma transfer count register is more than "0001 16 " and the dma is requested after 01 2 is written to the channel i transfer mode select bits ? repeat transfer transfer starts when the dma is requested after 11 2 is written to the channel i transfer mode select bits dma shutdown ? single transfer when 00 2 is written to the channel i transfer mode select bits and dma transfer count register becomes "0000 16 " by dma transfer or write ? repeat transfer when 00 2 is written to the channel i transfer mode select bits reload timing when the transfer counter register changes from "0001 16 " to "0000 16 " in repeat transfer mode. reading / writing the register registers are always read/write enabled. number of dma transfer cycles between sfr and internal ram : 3 cycles between external i/o and external memory : minimum 3 cycles table 1.11.1. dmac specifications note: dma transfer doed not affect any interrupt.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dmac 111 dmai request cause select register (i=0 to 3) rw dsel0 dsel1 dsel2 dma request cause select bit (note 1) dsel3 dsel4 software dma request bit (note 2) dsr nothing is assigned. when write, set "0". when read, its content is indeterminate. refer to function table drq dma request bit (note 2, 3) 0 : not requested 1 : requested note 1: set dma inhibit before changing the dma request cause. set drq bit to "1" simultaneously. e.g.) mov.b #083h, dmisl ; set timer a0 note 2: when setting dsr to "1", set drq bit to "1" using or instruction etc. simultaneously. e.g.) or.b #0a0h, dmisl note 3: do not write "0" to this bit. there is no need to clear the dma request bit. symbol address when reset dmisl(i=0 to 3) 0378 16, 0379 16, 037a 16, 037b 16 0x000000 2 function bit name bit symbol if software trigger is selected, a dma request is generated by setting this bit to "1" (when read, the value of this bit is always "0") b7 b6 b5 b4 b3 b2 b1 b0 figure 1.11.2. dmac register (1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dmac 112 setting value dma request cause b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 dma0 falling edge of int0 pin both edges of int0 dma1 dma2 falling edge of int2 pin both edges of int2 dma3 falling edge of int3 pin both edges of int3 software trigger timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 timer b3 timer b4 timer b5 uart0 transmit uart0 receive /ack uart1 transmit uart1 receive /ack uart2 transmit uart2 receive /ack uart3 transmit uart3 receive /ack uart4 transmit uart4 receive /ack falling edge of int1 pin both edges of int1 a-d0 intelligent i/o interrupt control register 0 intelligent i/o interrupt control register 1 intelligent i/o interrupt control register 2 intelligent i/o interrupt control register 3 intelligent i/o interrupt control register 4 intelligent i/o interrupt control register 5 intelligent i/o interrupt control register 6 a-d1 intelligent i/o interrupt control register 7 intelligent i/o interrupt control register 8 intelligent i/o interrupt control register 9 intelligent i/o interrupt control register 10 intelligent i/o interrupt control register 11 intelligent i/o interrupt control register 0 intelligent i/o interrupt control register 1 a-d0 intelligent i/o interrupt control register 2 intelligent i/o interrupt control register 3 intelligent i/o interrupt control register 4 intelligent i/o interrupt control register 5 intelligent i/o interrupt control register 6 intelligent i/o interrupt control register 7 intelligent i/o interrupt control register 8 a-d1 intelligent i/o interrupt control register 9 intelligent i/o interrupt control register 10 intelligent i/o interrupt control register 11 intelligent i/o interrupt control register 0 intelligent i/o interrupt control register 1 intelligent i/o interrupt control register 2 intelligent i/o interrupt control register 3 (note 2) (note 2) (note 2) (note 2) (note 2) note 1: when int3 pin is data bus in microprocessor mode, int3 edge cannot be used as dma3 request cause. note 2: uarti receive /ack switched by setting of uarti special mode register and uarti special mode register 2 (i=0 to 3) (note 1) (note 1) table 1.11.2. dmai request cause select register function
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dmac 113 dma mode register 0 (cpu internal register) symbol when reset dmd0 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 channel 0 transfer mode select bit md00 rw md01 bw0 rw0 md11 b1 b0 0 0 : dma inhibit 0 1 : single transfer 1 0 : must not be set 1 1 : repeat transfer a aa a aa a aa a a aa aa bit name md10 channel 0 transfer unit select bit 0 : 8 bits 1 : 16 bits channel 0 transfer direction select bit 0 : fixed address to memory (forward direction) 1 : memory (forward direction) to fixed address channel 1 transfer mode select bit bw1 rw1 b5 b4 0 0 : dma inhibit 0 1 : single transfer 1 0 : must not be set 1 1 : repeat transfer a a aa aa a aa a aa a aa channel 1 transfer unit select bit 0 : 8 bits 1 : 16 bits channel 1 transfer direction select bit dma mode register 1 (cpu internal register) symbol when reset dmd1 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 channel 2 transfer mode select bit md20 rw md21 bw2 rw2 md31 b1 b0 0 0 : dma inhibit 0 1 : single transfer 1 0 : must not be set 1 1 : repeat transfer a aa a aa a aa a aa bit name md30 channel 2 transfer unit select bit 0 : 8 bits 1 : 16 bits channel 2 transfer direction select bit channel 3 transfer mode select bit bw3 rw3 b5 b4 0 0 : dma inhibit 0 1 : single transfer 1 0 : must not be set 1 1 : repeat transfer a aa a aa a a aa aa a a aa aa channel 3 transfer unit select bit 0 : 8 bits 1 : 16 bits channel 3 transfer direction select bit 0 : fixed address to memory (forward direction) 1 : memory (forward direction) to fixed address 0 : fixed address to memory (forward direction) 1 : memory (forward direction) to fixed address 0 : fixed address to memory (forward direction) 1 : memory (forward direction) to fixed address figure 1.11.3. dmac register (2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dmac 114 function rw set transfer number dmai transfer count register (i = 0 to 3) (cpu internal register) setting range 0000 16 to ffff 16 a aa note 1: when "0" is set to this register, data transfer is not done even if dma is requested. note 2: use ldc instruction to write to this register. note 3: when setting dct2 and dct3, set "1" to the register bank select flag (b flag) of flag register (flg), then set desired value to r0 and r1 of register bank 1. use mov instruction to write to this register. b15 b0 function rw set transfer number symbol address when reset drc0 (note 1) (cpu internal register) xxxx 16 drc1 (note 1) (cpu internal register) xxxx 16 drc2 (bank 1;r2) (note 2) (cpu internal register) 0000 16 drc3 (bank 1;r3) (note 2) (cpu internal register) 0000 16 dmai transfer count reload register (i = 0 to 3) (cpu internal register) 0000 16 to ffff 16 a a aa aa note 1: use ldc instruction to write to this register. note 2: when setting drc2 and drc3, set "1" to the register bank select flag (b flag) of flag register (flg), then set desired value to r2 and r3 of register bank 1. use mov instruction to write to this register. b15 b0 symbol address when reset dct0 (note 2) (cpu internal register) xxxx 16 dct1 (note 2) (cpu internal register) xxxx 16 dct2 (bank 1;r0) (note 3) (cpu internal register) 0000 16 dct3 (bank 1;r1) (note 3) (cpu internal register) 0000 16 setting range figure 1.11.4. dmac register (3)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dmac 115 b23 b0 function rw set source or destination memory address dmai memory address register (i = 0 to 3) (cpu internal register) setting range 000000 16 to ffffff 16 (16 mbytes area) a a aa aa note 1: when the transfer direction select bit is "0" (fixed address to memory), this register is destination memory address. when the transfer direction select bit is "1" (memory to fixed address), this register is source memory address. note 2: use ldc instruction to write to this register. note 3: when setting dma2 and dma3, set "1" to the register bank select flag (b flag) of flag register (flg), and set desired value to a0 and a1 of register bank 1. use mov instruction to write to this register. b0 function rw set source or destination fixed address dmai sfr address register (i = 0 to 3) (cpu internal register) 000000 16 to ffffff 16 (16 mbytes area) a aa note 1: when the transfer direction select bit is "0" (fixed address to memory), this register is source fixed address. when the transfer direction select bit is "1" (memory to fixed address), this register is destination fixed address. note 2: use ldc instruction to write to this register. note 3: when setting dsa2, set "1" to the register bank select flag (b flag) of flag register (flg), and set desired value to sb of register bank 1. use ldc instruction to write to this register. note 4: when setting dsa3, set "1" to the register bank select flag (b flag) of flag register (flg), and set desired value to fb of register bank 1. use ldc instruction to write to this register. b0 function rw set source or destination memory address dmai memory address reload register (i = 0 to 3) (note 1) (cpu internal register) 000000 16 to ffffff 16 (16 mbytes area) a aa note 1: use ldc instruction to write to this register. note 2: when setting dra2, set desired value to save pc register (svp). note 3: when setting dra3, set desired value to vector register (vct). b23 b23 setting range setting range symbol address when reset dma0 (note 2) (cpu internal register) xxxxxx 16 dma1 (note 2) (cpu internal register) xxxxxx 16 dma2 (bank 1;a0) (note 3) (cpu internal register) 000000 16 dma3 (bank 1;a1) (note 3) (cpu internal register) 000000 16 symbol address when reset dsa0 (note 2) (cpu internal register) xxxxxx 16 dsa1 (note 2) (cpu internal register) xxxxxx 16 dsa2 (bank 1;sb) (note 3) (cpu internal register) 000000 16 dsa3 (bank 1;fb) (note 4) (cpu internal register) 000000 16 symbol address when reset dra0 (cpu internal register) xxxxxx 16 dra1 (cpu internal register) xxxxxx 16 dra2 (bank 1;svp) (note 2) (cpu internal register) xxxxxx 16 dra3 (bank 1;vct) (note 3) (cpu internal register) xxxxxx 16 (note 1) (note 1) figure 1.11.5. dmac register (4)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dmac 116 (1) transfer cycle the transfer cycle consists of the bus cycle in which data is read from memory or from the sfr area (source read) and the bus cycle in which the data is written to memory or to the sfr area (destination write). the number of read and write bus cycles depends on the source and destination addresses. in memory expansion mode and microprocessor mode, the number of read and write bus cycles also de- pends on the level of the byte pin. also, the bus cycle is longer when software waits are inserted. (a) effect of source and destination addresses when 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) effect of external data bus width control register when in memory expansion mode or microprocessor mode, the transfer cycle changes according to the data bus width at the source and destination. 1. when transferring 16 bits of data and the data bus width at the source and at the destination is 8 bits (data bus width bit = 0 ), there are two 8-bit data transfers. therefore, two bus cycles are required for reading and two cycles for writing. 2. when transferring 16 bits of data and the data bus width at the source is 8 bits (data bus width bit = 0 ) and the data bus width at the destination is 16 bits (data bus width bit = 1 ), the data is read in two 8-bit blocks and written as 16-bit data. therefore, two bus cycles are required for reading and one cycle for writing. 3. when transferring 16 bits of data and the data bus width at the source is 16 bits (data bus width bit = 1 ) and the data bus width at the destination is 8 bits (data bus width bit = 0 ), 16 bits of data are read and written as two 8-bit blocks. therefore, one bus cycle is required for reading and two cycles for writing. (c) effect of software wait when the sfr area or a memory area with a software wait is accessed, the number of cycles is increased for the soffware wait by 1 bus cycle. the length of the cycle is determined by bclk. figure 1.11.6 shows the example of the transfer cycles for a source read. figure 1.11.6 shows the desti- nation is external area, the destination write cycle is shown as two cycle (one bus cycle) and the source read cycles for the different conditions. in reality, the destination write cycle is subject to the same condi- tions as the source read cycle, with the transfer cycle changing accordingly. when calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. for example (2) in figure 1.11.6, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read cycle and the destination write cycle.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dmac 117 bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination (1) when 8-bit data is transferred when 16-bit data is transferred on a 16-bit data bus and the source address is even bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source (3) when one wait is inserted into the source read under the conditions in (1) bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source source + 1 source + 1 (2) when 16-bit data is transferred and the source address is odd when 16-bit data is transferred and the width of data bus at the source is 8-bit (when the width of data bus at the destination is 8-bit, there are also two destination write cycles). bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source source + 1 source + 1 (4) when one wait is inserted into the source read under the conditions in (2) (when 16-bit data is transferred and the width of data but at the destination is 8-bit, there are two destination write cycles). note: the same timing changes occur with the respective conditions at the destination as at the source. destination destination destination destination destination destination destination figure 1.11.6. example of the transfer cycles for a source read
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dmac 118 memory expansion mode microprocessor mode single-chip mode (2) dmac transfer cycles any combination of even or odd transfer read and write addresses is possible. table 1.11.2 shows the number of dmac transfer cycles. the number of dmac transfer cycles can be calculated as follows: no. of transfer cycles per transfer unit = no. of read cycles x j + no. of write cycles x k table 1.11.2. no. of dmac transfer cycles transfer unit bus width access address no. of read no. of write no. of read no. of write cycles cycles cycles cycles 16-bit even 1 1 1 1 8-bit transfers (dsi = 1 ) odd 1 1 1 1 (bwi = 0 ) 8-bit even 11 (dsi = 0 ) odd 11 16-bit even 1 1 1 1 16-bit transfers (dsi = 1 ) odd 2 2 2 2 (bwi = 1 ) 8-bit even 22 (dsi = 0 ) odd 22 coefficient j, k internal memory external memory coefficient j coefficient k internal rom/ram no wait 1 1 internal rom/ram one wait 2 2 sfr area 2 2 separate bus no wait 1 2 separate bus one wait 2 2 separate bus two waits 3 3 separate bus three waits 4 4 multiplex bus 3 3 dma request bit the dmac can issue dma requests using preselected dma request factors for each channel as triggers. the dma transfer request factors include the reception of dma request signals from the internal periph- eral functions, software dma factors generated by the program, and external factors using input from external interrupt signals. see the description of the dmai factor selection register for details of how to select dma request factors. dma requests are received as dma requests when the dmai request bit is set to 1 and the channel i transfer mode select bits are 01 or 11 . therefore, even if the dmai request bit is 1 , no dma request is received if the channel i transfer mode select bit is 00 . in this case, dmai request bit is cleared. because the channel i transfer mode select bits default to 00 after a reset, remember to set the channel i transfer mode select bit for the channel to be activated after setting the dmac related registers. this enables receipt of the dma requests for that channel, and dma transfers are then performed when the dmai request bit is set. the following describes when the dmai request bit is set and cleared.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dmac 119 bclk aaa aaa dma0 aaa aaa dma1 dma0 request bit dma1 request bit aaa aaaaaaa a a a cpu int0 int1 in this example, dma transfer request signals are input simultaneously from external factors and the dma transfers are executed in the minimum cycles. aa aa aa bus priviledge acquired aa aa (1) internal factors the dmai request flag is set to 1 in response to internal factors at the same time as the interrupt request bit of the interrupt control register for each factor is set. this is because, except for software trigger dma factors, they use the interrupt request signals output by each function. the dmai request bit is cleared to "0" when the dma transfer starts or the dma transfer is disabled (channel i transfer mode select bits are "00" and the dmai transfer count register is "0"). (2) external factors ______ these are dma request factors that are generated by the input edge from the inti pin (where i indi- ______ cates the dmac channel). when the inti pin is selected by the dmai request factor select bit as an external factor, the inputs from these pins become the dma request signals. when an external factor is selected, the dmai request bit is set, according to the function specified in the ______ dma request factor select bit, on either the falling edge of the signal input via the inti pins, or both edges. when an external factor is selected, the dmai request bit is cleared, in the same way as the dmai request bit is cleared for internal factors, when the dma transfer starts or the dma transfer is in disable state. (3) relationship between external factor request input and dmai request bits, and dma transfer timing when the request inputs to dmai occur in the same sampling cycle (between the falling edge of bclk and the next falling edge), the dmai request bits are set simultaneously, but if the dmai enable bits are all set, dma0 takes priority and the transfer starts. when one transfer unit is complete, the bus privilege is returned to the cpu. when the cpu has completed one bus access, dma1 transfer starts, and, when one transfer unit is complete, the privilege is again returned to the cpu. the priority is as follows: dma0 > dma1 > dma2 > dma3. figure 1.11.7. dma transfer example by external factors shows what happens when dma0 and dma1 requests occur in the same sampling cycle. figure 1.11.7. dma transfer example by external factors
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dmac 120 at least 8 + 6 x n cycles (n: enabled channel number) precautions for dmac (1) do not clear the dma request bit of the dmai request cause select register. in m32c/83, when a dma request is generated while the channel is disabled (note) , the dma transfer is not executed and the dma request bit is cleared automatically. note :the dma is disabled or the transfer count register is "0". (2) when dma transfer is done by a software trigger, set dsr and drq of the dmai request cause select register to "1" simultaneously using the or instruction. e.g.) or.b #0a0h, dmisl ; dmisl is dmai request cause select register (3) when changing the dmai request cause select bit of the dmai request cause select register, set "1" to the dma request bit, simultaneously. in this case, the corresponding dma channel is set to disabled. at least 8 + 6 x n (n: enabled channel number) clock cycles are needed from the instruction to write to the dmai request cause select bit to enable dma. e.g.) when dma request cause is changed to timer a0 and using dma0 in single transfer after dma initial setting push.w r0 ; store r0 register stc dmd0, r0 ; read dma mode register 0 and.b #11111100b, r0l ; clear dma0 transfer mode select bit to "00" ldc r0, dmd0 ; dma0 disabled mov.b #10000011b, dm0sl ; select timer a0 ; (write "1" to dma request bit simultaneously) nop : ldc r0, dmd0 ; dma0 enabled pop.w r0 ; restore r0 register
dmac ii under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 121 causes to activate dmac ii transfer data unit of transfer direction of transfer transfer space transfer mode chained transfer function interrupt at end of transfer interrupt request from any peripheral i/o whose interrupt priority is set to "level 7" by the interrupt control register (1) memory -> memory (memory-to-memory transfer) (2) immediate data -> memory (immediate data transfer) (3) memory (or immediate data) + memory -> memory (arithmetic transfer) transferred in 8 or 16 bits 64-kbyte space at address up to 0ffff 16 fixed or forward address can be selected individually for the source and the destination of transfer. (1) single transfer (2) burst transfer parameters (transfer count, transfer address, and other information) are switched over when the transfer counter reaches zero. interrupt is generated when the transfer counter reaches zero. item specification multiple transfer function multiple data transfers can be performed by one dma ii transfer request generated. (note) dmac ii when requested by an interrupt from any peripheral i/o, the dmac performs a memory-to-memory trans- fer, an immediate data transfer, or an arithmetic transfer (to transfer the sum of two data added). specifications of dmac ii are shown in table 1.12.1. table 1.12.1 specifications of dmac ii note : when transfer unit is 16 bits and destination address is 0ffff 16 , data is transfered to addresses 0ffff 16 and 10000 16 . when source address is 0ffff 16 , data is transfered as in the previous. settings of dmac ii dmac ii can be enabled for use by setting up the following registers and tables. ? exit priority register (address 009f 16 ) ? dmac ii index ? interrupt control register for the peripheral i/o that requests a transfer by dmac ii ? relocatable vector table for the peripheral i/o that requests a transfer by dmac ii ? when using an intelligent i/o or can interrupt, interrupt enable register s interrupt request latch bit (bit 0) (1) exit priority register (address 009f 16 ) if this register s dmac ii select bit (bit 5) and fast interrupt select bit (bit 3) respectively are set to 1 and 0, dmac ii is activated by an interrupt request from any peripheral i/o whose interrupt priority is set to level 7 by the interrupt priority level select bit. the configuration of the exit priority register is shown in figure 1.12.1.
dmac ii under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 122 exit priority register when reset xx0x0000 2 address 009f 16 symbol rlvl rw rlvl0 rlvl1 rlvl2 interrupt priority set bits for exiting stop/wait state (note 1) fsit high-speed interrupt set bit (note 2) 0: interrupt priority level 7 = normal interrupt 1: interrupt priority level 7 = high-speed interrupt dma ii dma ii select bit (note 3) 0: interrupt priority level 7 = normal interrupt or high-speed interrupt 1: interrupt priority level 7 = dma ii transfer nothing is assigned. when write, set "0". when read, its content is indeterminate. nothing is assigned. when write, set "0". when read, their contents are indeterminate. 0 0 0 : level 0 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 note 1: exits the stop or wait mode when the requested interrupt priority level is higher than that set in the exit priority register. set to the same value as the processor interrupt priority level (ipl) set in the flag register (flg). note 2: the high-speed interrupt can only be specified for interrupts with interrupt priority level 7. specify interrupt priority level 7 for only one interrupt. note 3: do not set this bit to 0 after once setting it to 1. when this bit is 1, do not set the high-speed interrupt select bit to 0. (this cannot be used simultaneously with the high-speed interrupt.) transfers by dmac ii are unaffected by the interrupt enable flag (i flag) and processor interrupt priority level (ipl). figure 1.12.1. exit priority register
dmac ii under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 123 transfer mode (mod) transfer counter (count) transfer source address (or imm data)(sadr) operation address (oadr) transfer destination address (dadr) chained transfer address (cadr0) chained transfer address (cadr1) end-of-transfer interrupt address (iadr0) end-of-transfer interrupt address (iadr1) 16 bits dmac ii index start address (base) base + 2 base + 4 base + 6 base + 8 base + 10 base + 14 base + 16 base + 12 (note1) (note2) (note2) (note3) (note3) transfer mode (mod) transfer counter (count) transfer source address (sadr1) transfer destination address (dadr1) transfer source address (sadr2) transfer destination address (dadr2) transfer source address (sadr7) transfer destination address (dadr7) 16 bits base base + 2 base + 4 base + 6 base + 8 base + 10 base + 28 base + 30 memory-to-memory transfer, immediate transfer, arithmetic transfer multiple transfer note 1: delete this data when not using the arithmetic transfer function. note 2: delete this data when not using the chained transfer function. note 3: delete this data when not using an end-of-transfer interrupt. (2) dmac ii index the dmac ii index is a data table, comprised of 8 to 18 bytes (max. 32 kbytes when multiple transfer function is selected), which contains such parameters as transfer mode, transfer counter, transfer source address (or immediate data), operation address, transfer destination address, chained trans- fer address, and end-of-transfer interrupt address. this dmac ii index is located in the ram area. configuration of the dmac ii index is shown in figure 1.12.2. the configuration of the dmac ii index by transfer mode is shown in table 1.12.2. ? transfer mode (mod) this two-byte data sets dmac ii transfer mode. configuration of transfer modes is shown in figure 1.12.3. ? transfer counter (count) this two-byte data sets the number of times transfer is performed. ? transfer source address (sadr) this two-byte data sets the memory address from which data is transferred or immediate data. ? operation address (oadr) this two-byte data sets the memory address to be operated on for calculation. this data is added to the table only when using the arithmetic transfer function. ? transfer destination address (dadr) this two-byte data sets the memory address to which data is transferred. ? chained transfer address (cadr) this four-byte data sets the dmac ii index start address for the next dmac ii transfer to be per- formed. this data is added to the table only when using the chained transfer function. ? end-of-transfer interrupt address (iadr) this four-byte data sets the jump address for end-of-transfer interrupt processing. this data is added to the table only when using an end-of-transfer interrupt. figure 1.12.2. dmac ii index
dmac ii under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 124 transmit data memory-to-memory transfer /immediate data transfer arithmetic transfer multiple transfer chained transfer interrupt at end of transfer not use not use not use not use use not use not use not use use use not use use use use cannot use cannot use use use dmac ii index count mod sadr dadr count mod sadr dadr cadr0 cadr1 count mod sadr oadr oadr oadr dadr iadr0 iadr1 count mod sadr dadr iadr0 iadr1 count mod sadr dadr cadr0 cadr1 iadr0 iadr1 oadr 8 bytes 12 bytes count mod sadr dadr count mod sadr dadr cadr0 cadr1 10 bytes 14 bytes 12 bytes 14 bytes 18 bytes count mod sadr dadr cadr0 cadr1 iadr0 iadr1 16 bytes count mod sadr1 dadr1 sadri dadri i=1 to 7 max. 32 bytes (when i=7) function (mult=0) function (mult=1) transfer mode(mod) rw size imm upds transfer unit select bit updd inte /cnt2 transfer distination direction select bit 0: fixed address 1: forward address 0: single transfer 1: burst transfer alithmatic transfer function select bit 0: not used 1: used 0: 8 bits 1: 16 bits brst /cnt1 oper /cnt0 chain transfer data select bit transfer source direction select bit burst transfer select bit end of transfer interrupt select bit chained transfer select bit 0: immedeate data 1: memory must set to "1" must set to "0" mult multiple transfer select bit 0: not multiple transfer 1: multiple transfer 0: fixed address 1: forward address 0: interrupt not used 1: interrupt used 0: chained transfer not used 1: chained transfer used b6 b5 b4 0 0 0: do not set this 0 0 1: once 0 1 0: twice : : 1 1 0: 6 times 1 1 1: 7 times nothing is assigned. when write, set "0". when read, their contents are indeterminate. bit name bit symbol b7 b0 b15 (b7) b8 (b0) table 1.12.2. the configuration of the dmac ii index by transfer mode figure 1.12.3. transfer mode
dmac ii under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 125 (3) interrupt control register for peripheral i/o for peripheral i/o interrupts used to request a transfer by dmac ii, set the interrupt control register for each peripheral i/o to select level 7 for their interrupt priority. (4) relocatable vector table for peripheral i/o in the relocatable vector table for each peripheral i/o that requests a transfer by dmac ii, set the dmac ii index start address. (when using chained transfers, the relocatable vector table must be located in the ram.) (5) interrupt enable register s interrupt request latch bit (bit 0) when using an intelligent i/o or can interrupt to activate dmac ii, set to 0 the interrupt enable register s interrupt request latch bit (bit 0) for the intelligent i/o or can interrupt that requests a transfer by dmac ii. operation of dmac ii the dmac ii function is selected by setting the dmac ii select bit (bit 5 at address 009f 16 ) to 1. all peripheral i/o interrupt requests which have had their interrupt priorities set to level 7 by the interrupt control register comprise dmac ii interrupt requests. these interrupt requests (priority level = 7) do not generate an interrupt, however. when an interrupt request is generated by any peripheral i/o whose interrupt priority is set to level 7, dmac ii is activated no matter which state the i flag and processor interrupt priority level(ipl) is in. if an _______ interrupt request with higher priority than that (e.g., nmi or watchdog timer) occurs, this higher priority interrupt has precedence over and is accepted before dmac ii transfers. the pending dmac ii transfer is started after the interrupt processing sequence for that interrupt finishes. transfer data dmac ii transfers data in units of 8 or 16 bits as described below. ? memory-to-memory transfer: data is transferred from any memory location in the 64-kbyte space to any memory location in the same space. ? immediate data transfer: data is transferred as immediate data to any memory location in the 64- kbyte space. ? arithmetic transfer: two 8 or16 bits of data are added together and the result is transferred to any memory location in the 64-kbyte space. when transfer unit is 16 bits and destination address is 0ffff 16 , data is transfered to addresses 0ffff 16 and 10000 16 . when source address is 0ffff 16 , data is transfered as in the previous.
dmac ii under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 126 (1) memory-to-memory transfer data can be transferred from any memory location in the 64-kbyte space to any memory location in the same space in one of the following four ways: ? transfer from a fixed address to another fixed address ? transfer from a fixed address to a variable address ? transfer from a variable address to a fixed address ? transfer from a variable address to another variable address if variable address mode is selected, the transfer address is incremented for the next dma ii transfer to be performed. when transferred in units of 8 bits, the transfer address is incremented by one; when transferred in units of 16 bits, the transfer address is incremented by two. if the transfer source or destination address exceeds 0ffff 16 as a result of address incrementation, the transfer source or destination address recycles back to 00000 16 . (2) immediate data transfer data is transferred as immediate data to any memory location in the 64-kbyte space. a fixed or variable address can be selected for the transfer destination address. store the immediate data in the dmac ii index s transfer source address. when transferring 8-bit immediate data, set the data in the lower byte position of the transfer source address. (the upper byte is ignored.) (3) arithmetic transfer data in two memory locations of the 64-kbyte space or immediate data and data in any memory location of the 64-kbyte space are added together and the result is transferred to any memory location in the 64-kbyte space. set the memory location to be operated on or immediate data in the dmac ii index s transfer source address field and the other memory location to be operated on in the dmac ii index s operation address field. when performing this mode of transfer on two memory locations, a fixed or variable address can be selected for the transfer source and transfer destination addresses. if the transfer source address is chosen to be variable, the operation address also becomes variable. when performing this mode of transfer on immediate data and any memory location, a fixed or vari- able address can be selected for the transfer destination address. transfer modes dmac ii supports single and burst transfers. use the burst transfer select bit (bit 5) for transfer mode setup in the dmac ii index to choose single or burst transfer mode. use the dmac ii index transfer counter to set the number of times a transfer is performed. neither single transfer nor burst transfer is performed if the value 0000 16 is set in the transfer counter. (1) single transfer for a dmac ii transfer request, 8 or 16 bits of data (one transfer unit) is transferred once. if the transfer source or transfer destination address is chosen to be variable, the next dma ii transfer is performed on an incremented memory address. the transfer counter is decremented by each dma ii transfer performed. when using the end-of-transfer interrupt facility, an end-of-transfer interrupt is generated at the time the transfer counter reaches zero.
dmac ii under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 127 (2) burst transfer for a dmac ii transfer request, data transfers are performed in succession a number of times as set by the dmac ii index transfer counter. when using the end-of-transfer interrupt facility, an end-of- transfer interrupt is generated at the time a burst transfer finishes (i.e., when the transfer counter reaches zero after being decremented for each data transfer performed). (3) multiple transfers for multiple transfers, use the multiple transfer select bit (bit 15) for transfer mode setup in the dmac ii index. setting this bit to 1 selects the multiple transfer function. for the multiple transfer function, memory to memory transfer can be performed. multiple transfers are performed for one dmac ii transfer request received. use dmac ii index trans- fer mode bits 4 C 6 to set the number of transfers to be performed. (setting these bits to 001 performs one transfer; setting these bits to 111 performs 7 transfers. setting these bits to 000 is inhibited.) the transfer source and transfer destination addresses are alternately incremented beginning with the dmac ii index base address + 4 (as many times as the number of transfers performed). when using multiple transfer function, arithmetic transfer, burst transfer, end-of-transfer interrupt and chained transfer cannot be used. (4) chained transfer for chained transfers, use the chained transfer select bit (bit 7) for transfer mode setup in the dmac ii index. setting this bit to 1 selects the chained transfer function. the following describes how a chained transfer is performed. 1) when a dma ii transfer request (interrupt request from any peripheral i/o) is received, a dmac ii index transfer is performed corresponding to the received request. 2) when the dmac ii index transfer counter reaches zero, the chained transfer address in the dmac ii index (i.e., the start address of the dmac ii index that contains a description of the next dmac ii transfer to be performed) is written to the relocatable vector table for the peripheral i/o. 3) from the next dma ii transfer request on, transfers are performed based on the dmac ii index indicated by the rewritten relocatable vector table of the peripheral i/o. before the chained transfer function can be used, the relocatable vector table must be located in the ram area. (5) end-of-transfer interrupt for end-of-transfer interrupts, use the end-of-transfer interrupt select bit (bit 6) for transfer mode setup in the dmac ii index. setting this bit to 1 selects the end-of-transfer interrupt function. set the jump address for end-of-transfer interrupt processing in the dmac ii index s end-of-transfer interrupt ad- dress field. an end-of-transfer interrupt is generated when the dmac ii index transfer counter reaches zero.
dmac ii under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 128 a=0 b=1 c=0 d=0 e=0 first dmac ii transfer t=6+27x1+4x1=37 cycle second dmac ii transfer t=6+27x1+4x0=33 cycle transfer counter = 2 down count of transfer counter transfer counter = 1 transfer counter = 1 application program dmac ii transfer (first time) dmac ii transfer (second time) 8 cycles end of transfer interrupt program dmac ii transfer request down count of transfer counter transfer counter = 0 33 cycles 37 cycles dmac ii transfer request when using an end-of-transfer interrupt (transfer counter = 2) after performing a memory to memory single transfer twice from a variable source address to a fixed destination address, with the chained transfer function unselected application program execution time the number of dmac ii execution cycles is calculated by the equation below. for other than multiple transfers, t = 6 + (26 + a + b + c + d) x m + (4 + e) x n (cycles) for multiple transfers, t = 21 + (11 + b + c) x k (cycles) where a: if the source of transfer is immediate data, a = 0; if it is memory, a = C 1 b: if the source address of transfer is a variable address, b = 0; if it is a fixed address, b = 1 c: if the destination address of transfer is a variable address, c = 0; if it is a fixed address, c = 1 d: if the arithmetic function is not selected, d = 0; if the arithmetic function is selected and the source of transfer is immediate data or fixed address memory, d = 7; if the arithmetic function is selected and the source of transfer is variable address memory, d = 8 e: if the chained transfer function is not selected, e = 0; if the chained transfer function is selected, e = 4 m: for single transfer, m = 1; for burst transfer, m = the value set by the transfer counter n: if the transfer count is one, n = 0; if the transfer count is two or greater, n = 1 k: number of transfers set by transfer mode bits 4 C 7 the above equation applies only when all of the following conditions are met, however. ? no bus wait states are inserted. ? the dmac ii index is set to an even address. ? during word transfer, the transfer source address, transfer destination address, and operation address all are set to an even address. note that the first instruction in end-of-transfer interrupt processing is executed 7 cycles after dmac ii transfers are completed. figure 1.12.4. transfer time
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer 129 timer there are eleven 16-bit timers. these timers can be classified by function into timers a (five) and timers b (six). all these timers function independently. figures 1.13.1 and 1.13.2 show the block diagram of timers. ? timer mode ? one-shot mode ? pwm mode ? timer mode ? one-shot mode ? pwm mode ? timer mode ? one-shot mode ? pwm mode ? timer mode ? one-shot mode ? pwm mode ? timer mode ? one-shot mode ? pwm mode ? event counter mode ? event counter mode ? event counter mode ? event counter mode ? event counter mode ta0 in ta1 in ta2 in ta3 in ta4 in timer a0 timer a1 timer a2 timer a3 timer a4 f 1 f 8 f 2n f c32 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt noise filter noise filter noise filter noise filter noise filter 1/32 f c32 1/8 f 1 f 8 f 2n (n = 0 to 15 however, no division when n=0) x in x cin clock prescaler reset flag (bit 7 at address 0341 16 ) set to 1 reset clock prescaler timer b2 overflow 1/2n count source prescaler register figure 1.13.1. timer a block diagram
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer 130 ? event counter mode ? event counter mode ? event counter mode ? timer mode ? pulse width measuring mode ? timer mode ? pulse width measuring mode ? timer mode ? pulse width measuring mode tb0 in tb1 in tb2 in timer b0 timer b1 timer b2 f 1 f 8 f 2n f c32 timer b0 interrupt noise filter noise filter noise filter timer b2 overflow (to timer a count source) ? event counter mode ? event counter mode ? event counter mode ? timer mode ? pulse width measuring mode ? timer mode ? pulse width measuring mode ? timer mode ? pulse width measuring mode tb3 in tb4 in tb5 in timer b3 timer b4 timer b5 timer b3 interrupt noise filter noise filter noise filter timer b1 interrupt timer b2 interrupt timer b4 interrupt timer b5 interrupt 1/32 f c32 1/8 f 1 f 8 f 2n (n = 0 to 15 however, no division when n=0) x in x cin clock prescaler reset flag (bit 7 at address 0341 16 ) set to 1 reset clock prescaler 1/2n count source prescaler register figure 1.13.2. timer b block diagram
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 131 timer a figure 1.14.1 shows the block diagram of timer a. figures 1.14.2 to 1.14.6 show the timer a-related registers. except in event counter mode, timers a0 through a4 all have the same function. use the timer ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. timer a has the four operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer over flow. ? one-shot timer mode: the timer outputs one effective pulse until the count reaches 0000 16 . ? pulse width modulation (pwm) mode: the timer outputs pulses of a given width. count start flag (address 0340 16 ) up count/down count tai addresses taj tak timer a0 0347 16 0346 16 timer a4 timer a1 timer a1 0349 16 0348 16 timer a0 timer a2 timer a2 034b 16 034a 16 timer a1 timer a3 timer a3 034d 16 034c 16 timer a2 timer a4 timer a4 034f 16 034e 16 timer a3 timer a0 always down count except in event counter mode reload register (16) counter (16) low-order 8 bits aaaa aaaa high-order 8 bits clock source selection ? timer (gate function) ? timer ? one shot ? pwm f 1 f 8 f 32 external trigger tai in (i = 0 to 4) tb2 overflow ? event counter f c32 clock selection taj overflow (j = i C 1. note, however, that j = 4 when i = 0) pulse output toggle flip-flop tai out (i = 0 to 4) data bus low-order bits data bus high-order bits a a a up/down flag down count (address 0344 16 ) tak overflow (k = i + 1. note, however, that k = 0 when i = 4) polarity selection figure 1.14.1. block diagram of timer a
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 132 timer ai register (i = 0 to 4) (note 1) symbol address when reset tai (i = 0 to 2) 0347 16 ,0346 16 , 0349 16 ,0348 16 , 034b 16 ,034a 16 indeterminate tai (i = 3, 4) 034d 16 ,034c 16 , 034f 16 ,034e 16 indeterminate b7 b0 b7 b0 (b15) (b8) w r timer mode function values that can be set event counter mode one-shot timer mode 00 16 to fe 16 (high-order address) 00 16 to ff 16 (low-order address) 0000 16 to fffe 16 0000 16 to ffff 16 0000 16 to ffff 16 0000 16 to ffff 16 16-bit counter (set to dividing ratio) 16-bit counter (set to dividing ratio) 16-bit counter (set to one shot width) pulse width modulation mode (16-bit pwm) 16-bit pulse width modulator (set to pwm pulse h width) pulse width modulation mode (8-bit pwm) (note 2) (note 6) (note 4, 7) low-order 8 bits : 8-bit prescaler (set to pwm period) high-order 8 bits : 8-bit pulse width modulator (set to pwm pulse h width) (note 5, 7) (note 3) (note 3) (note 3) note 1: read and write data in 16-bit units. note 2: counts pulses from an external source or timer overflow. note 3: use mov instruction to write to this register. note 4: when setting value is n, pwm period and h width of pwm pulse are as follows: pwm period : (2 - 1) / fi pwm pulse h width : n / fi note 5: when setting value of high-order address is n and setting value of low-order address is m, pwm period and h width of pwm pulse are as follows: pwm period : (2 - 1) x (m + 1) / fi pwm pulse h width : (m + 1)n / fi note 6: when the timer ai register is set to "0000 16 ", the counter does not operate and the timer ai interrupt request is not generated. when the pulse is set to output, the pulse does not output from the tai out pin. note 7: when the timer ai register is set to "0000 16 ", the pulse width modulator does not operate and the output level of the tai out pin remains "l" level, therefore the timer ai interrupt request is not generated. this also occurs in the 8-bit pulse width modulator mode when the significant 8 high-order bits in the timer ai register are set to "00 16 ". 16 8 figure 1.14.2. timer a-related registers (1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 133 figure 1.14.3. timer a-related registers (2) timer ai mode register (i = 0 to 4) symbol address when reset taimr(i=0 to 4) 0356 16 , 0357 16 , 0358 16 , 0359 16 , 035a 16 00000x00 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit operation mode select bit this bit is invalid in m32c/80 series. port output control is set by the function select registers a, b and c. function varies with each operation mode symbol address when reset tabsr 0340 16 00 16 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 134 figure 1.14.4. timer a-related registers (3) timer a4 up/down flag timer a3 up/down flag timer a2 up/down flag timer a1 up/down flag timer a0 up/down flag timer a2 two-phase pulse signal processing select bit timer a3 two-phase pulse signal processing select bit timer a4 two-phase pulse signal processing select bit symbol address when reset udf 0344 16 00 16 ta4p ta3p ta2p up/down flag (note 1) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ta4ud ta3ud ta2ud ta1ud ta0ud 0 : down count 1 : up count 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled note 1: use mov instruction to write to this register. note 2: this specification becomes valid when the up/down flag content is selected for up/down switching cause. note 3: when not using the two-phase pulse signal processing function, set the select bit to 0 . 0 : down count 1 : up count 0 : down count 1 : up count 0 : down count 1 : up count 0 : down count 1 : up count 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled w r aa a aa a aa a aa aa a a aa a a a a (note 2) (note 2) (note 2) (note 2) (note 2) (note 3) (note 3) (note 3) ta1os ta2os ta0os one-shot start flag symbol address when reset onsf 0342 16 00 16 timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag ta3os ta4os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ta0tgl ta0tgh 0 0 : input on ta 0in is selected 0 1 : tb2 overflow is selected 1 0 : ta4 overflow is selected 1 1 : ta1 overflow is selected timer a0 event/trigger select bit b7 b6 note 1: when read, the value is 0 . note 2: set the corresponding pin output function select register to i/o port, and port direction register to 0 . w r 0 : invalid 1 : timer start z phase input enable bit tazie 0 : invalid 1 : valid 0 : invalid 1 : timer start 0 : invalid 1 : timer start 0 : invalid 1 : timer start 0 : invalid 1 : timer start aa a aa a aa a aa a aa a aa a aa aa a a aa a (note 1) (note 2) (note 1) (note 1) (note 1) (note 1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 135 symbol address when reset cpsrf 0341 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 clock prescaler reset flag 0 : ignored 1 : prescaler is reset (when read, the value is 0 ) cpsr w r nothing is assigned. when write, set 0 . when read, their contents are indeterminate. ta1tgl symbol address when reset trgsr 0343 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on ta2 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit w r ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 a a a a a a a a a a a a a a a a a a a a a a a a note: set the corresponding port function select register a to i/o port, and port direction register to 0 . a a a a figure 1.14.5. timer a-related registers (4)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 136 symbol address when reset tcspr 035f 16 0xxxxxxx 2 count source prescaler register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 count start bit 0 : stops counting 1 : starts counting cst w r nothing is assigned. when write, set 0 . when read, their contents are indeterminate. a a note 1: set count start bit to 0 before writing to count value set bits. note 2: when this bit is set to 0 , divider circuit is inactive. a a a a a a a a cnt0 cnt1 cnt2 cnt3 count value set bits 0 0 0 0 : no division 0 0 0 1 : division by 2 0 0 1 0 : division by 4 0 0 1 1 : division by 6 1 1 0 1 : division by 26 1 1 1 0 : division by 28 1 1 1 1 : division by 30 (note 1) (note 2) b3 b2 b1 b0 figure 1.14.6. timer a-related registers (5)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 137 (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.14.1.) figure 1.14.7 shows the timer ai mode register in timer mode. table 1.14.1. specifications of timer mode item specification count source f 1 , f 8 , f 2n , f c32 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(m+1)m : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing when the timer underflows tai in pin function programmable i/o port or gate input tai out pin function programmable i/o port or pulse output (setting by corresponding function select registers a, b and c) read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ? gate function counting can be started and stopped by the tai in pin s input signal ? pulse output function each time the timer underflows, the tai out pin s polarity is reversed figure 1.14.7. timer ai mode register in timer mode timer ai mode register (i = 0 to 4) (timer mode) symbol address when reset taimr(i=0 to 4) 0356 16 , 0357 16 , 0358 16 , 0359 16 , 035a 16 00000x00 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 count source select bit operation mode select bit this bit is invalid in m32c/80 series. port output control is set by the function select registers a, b and c. note 1: x value can be 0 or 1 . note 2: set the corresponding function select register a to i/o port, and port direction register to 0 . note 3: n = 0 to 15. n is set by the count source prescaler register (address 035f 16 ). gate function select bit 0 x : gate function not available (tai in pin is a normal port pin) 1 0 : timer counts only when ta iin pin is held l 1 1 : timer counts only when ta iin pin is held h 0 (set to 0 in timer mode) (note 2) (note 2) (note 1) (note 3) b4 b3 0 0 : f 1 0 1 : f 8 1 0 : f 2n 1 1 : f c32 b7 b6
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 138 note: this does not apply when the free-run function is selected. (2) event counter mode in this mode, the timer counts an external signal or an internal timer s overflow. timers a0 and a1 can count a single-phase external signal. timers a2, a3, and a4 can count a single-phase and a two-phase external signal. table 1.14.2 lists timer specifications when counting a single-phase external signal. table 1.14.3 lists timer specifications when counting a two-phase external signal. figure 1.14.8 shows the timer ai mode register in event counter mode. table 1.14.2. timer specifications in event counter mode (when not processing two-phase pulse signal) item specification count source ? external signals input to tai in pin (effective edge can be selected by software) ? tb2 overflows or underflows, taj overflows or underflows count operation ? up count or down count can be selected by external signal or software ? when the timer overflows or underflows, it reloads the reload register contents before continuing counting (note) divide ratio ? 1/ (ffff 16 - n + 1) for up count ? 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer overflows or underflows tai in pin function programmable i/o port or count source input tai out pin function programmable i/o port, pulse output, or up/down count select input (setting by corre- sponding function select registers a, b and c) read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ? free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it ? pulse output function each time the timer overflows or underflows, the tai out pin s polarity is reversed
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 139 timer ai mode register (i = 0 to 4) (event counter mode) symbol address when reset taimr(i=0 to 4) 0356 16 , 0357 16 , 0358 16 , 0359 16 , 035a 16 00000x00 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 1 : event counter mode b1 b0 tck1 mr3 mr2 mr1 tmod1 tmod0 tck0 operation mode select bit this bit is invalid in m32c/80 series. port output control is set by the function select registers a, b and c. note 1: count source is select by the event/trigger select bit (addresses 0342 16 , 0343 16 ) in event counter mode. note 2: this bit is valid when only counting an external signal. note 3: set the corresponding function select register a to i/o port, and port direction register to 0 . signal of tai out pin counts down at the time of l and counts up at the time of h . note 4: this bit is valid for timer a3 mode register. timer a0 and a1 can be 0 or 1 . timer a2 is fixed to normal processing operation and timer a4 is fixed to multiply-by-4 processing operation. note 5: when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0344 16 ) is set to 1 . also, always be sure to set the event/trigger select bit (address 0343 16 ) to 00 . 0 (set to 0 in event counter mode) (note 1) 0 (set to 0 when using two-phase pulse signal processing) (when not using two-phase pulse signal processing) (when using two-phase pulse signal processing) function count polarity select bit (note 2) 0 : counts external signal's falling edges 1 : counts external signal's rising edges up/down switching cause select bit 0 : up/down flag's content 1 : taiout pin's input signal (note 3) 1 (set to 1 when using two-phase pulse signal processing) count operation type select bit 0 : reload type 1 : free-run type two-phase pulse signal processing operation select bit (note 4,note 5) 0 : normal processing operation 1 : multiply-by-4 processing operation 0 (set to 0 when not using two-phase pulse signal processing) mr0 figure 1.14.8. timer ai mode register in event counter mode
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 140 item specification count source two-phase pulse signals input to tai in or tai out pin count operation ? up count or down count can be selected by two-phase pulse signal ? when the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (note 1) divide ratio ? 1/ (ffff 16 - n + 1) for up count ? 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing timer overflows or underflows tai in pin function two-phase pulse input tai out pin function two-phase pulse input (set corresponding function select register a for i/o port) read from timer count value can be read out by reading timer a2, a3, or a4 register write to timer ? when counting stopped when a value is written to timer a2, a3, or a4 register, it is written to both reload register and counter ? when counting in progress when a value is written to timer a2, a3, or a4 register, it is written to only reload register. (transferred to counter at next reload time.) select function (note 2) ? normal processing operation (timera2 and timer a3) the timer counts up rising edges or counts down falling edges on the tai in pin when input signal on the tai out pin is h ? multiply-by-4 processing operation (timera3 and timer a4) if the phase relationship is such that the tai in pin goes h when the input signal on the tai out pin is h , the timer counts up rising and falling edges on the tai out and tai in pins. if the phase relationship is such that the tai in pin goes l when the input signal on the tai out pin is h , the timer counts down rising and falling edges on the tai out and tai in pins. tai out up count up count up count down count down count down count tai in (i=2,3) tai out tai in (i=3,4) count up all edges count up all edges count down all edges count down all edges (when processing two-phase pulse signal with timers a2, a3, and a4) note 1: this does not apply when the free-run function is selected. note 2: timer a3 is selectable. timer a2 is fixed to normal processing operation and timer a4 is fixed to multiply-by-4 operation. table 1.14.3. timer specifications in event counter mode
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 141 the pulse must be wider than this width. note: when the rising edge of int2 is selected. ta3 out (a phase) count source ta3 in (b phase) int2 (note) (z phase) ta3 out (a phase) count source ta3 in (b phase) becoming 0 at this timing. count value mm+1 1 2 3 4 5 int2 (z phase) (note) note: when the rising edge of int2 is selected. counter resetting by two-phase pulse signal processing this function resets the timer counter to 0 when the z-phase (counter reset) is input during two- phase pulse signal processing. this function can only be used in timer a3 event counter mode, two-phase pulse signal processing, free-run type, and multiply-by-4 processing. the z phase is input to the int2 pin. when the z-phase input enable bit (bit 5 at address 0342 16 ) is set to 1 , the counter can be reset by z-phase input. for the counter to be reset to 0 by z-phase input, you must first write 0000 16 to the timer a3 register (addresses 034d 16 and 034c 16 ). the z-phase is input when the int2 input edge is detected. the edge polarity is selected by the int2 polarity switch bit (bit 4 at address 009c 16 ). the z-phase must have a pulse width greater than 1 cycle of the timer a3 count source. figure 1.14.9 shows the relationship between the two-phase pulse (a phase and b phase) and the z phase. the counter is reset at the count source following z-phase input. figure 1.14.10 shows the timing at which the counter is reset to 0 . note that timer a3 interrupt requests occur successively two times when timer a3 underflow and int2 input reload occures at the same time. do not use timer a3 interrupt request when this function is used. figure 1.14.9. the relationship between the two-phase pulse (a phase and b phase) and the z phase figure 1.14.10. the counter reset timing
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 142 (3) one-shot timer mode in this mode, the timer operates only once. (see table 1.14.4.) when a trigger occurs, the timer starts up and continues operating for a given period. figure 1.14.11 shows the timer ai mode register in one- shot timer mode. table 1.14.4. timer specifications in one-shot timer mode item specification count source f 1 , f 8 , f 2n , f c32 count operation ? the timer counts down ? when the count reaches 0000 16 , the timer stops counting after reloading a new count ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value count start condition ? an external trigger is input ? the timer overflows ? the one-shot start flag is set (= 1) count stop condition ? a new count is reloaded after the count has reached 0000 16 ? the count start flag is reset (= 0) interrupt request generation timing the count reaches 0000 16 tai in pin function programmable i/o port or trigger input tai out pin function programmable i/o port or pulse output (setting by corresponding function select regis- ters a, b and c) read from timer when timer ai register is read, it indicates an indeterminate value write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 143 figure 1.14.11. timer ai mode register in one-shot timer mode bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 (set to 0 in one-shot timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 2n 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 0 : one-shot start flag is valid 1 : selected by event/trigger select register trigger select bit external trigger select bit 0 : falling edge of tai in pin's input signal (note 2) 1 : rising edge of tai in pin's input signal (note 2) note 1: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0342 16 and 0343 16 ). if timer overflow is selected, this bit can be 1 or 0 . note 2: set the corresponding function select register a to i/o port, and port direction register to 0 . note 3: n = 0 to 15. n is set by the count source prescaler register (address 035f 16 ). w r aa a aa a aa a aa a aa aa a a aa aa a a aa aa a a this bit is invalid in m32c/80 series. port output control is set by the function select registers a, b and c. C C timer ai mode register (i = 0 to 4) (one-shot timer mode) symbol address when reset taimr(i=0 to 4) 0356 16 , 0357 16 , 0358 16 , 0359 16 , 035a 16 00000x00 2 (note 1) (note 3)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 144 (4) pulse width modulation (pwm) mode in this mode, the timer outputs pulses of a given width in succession. (see table 1.14.5.) in this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. figure 1.14.12 shows the timer ai mode register in pulse width modulation mode. figure 1.14.13 shows the example of how a 16-bit pulse width modulator operates. figure 1.14.14 shows the example of how an 8- bit pulse width modulator operates. table 1.14.5. timer specifications in pulse width modulation mode item specification count source f 1 , f 8 , f 2n , f c32 count operation ? the timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new count at a rising edge of pwm pulse and continues counting ? the timer is not affected by a trigger that occurs when counting 16-bit pwm ? high level width n / fi n : set value ? cycle time (2 16 -1) / fi fixed 8-bit pwm ? high level width n (m+1) / fi n : values set to timer ai register s high-order address ? cycle time (2 8 -1) (m+1) / fi m:values set to timer ai register s low-order address count start condition ? external trigger is input ? the timer overflows ? the count start flag is set (= 1) count stop condition ? the count start flag is reset (= 0) interrupt request generation timing pwm pulse goes l tai in pin function programmable i/o port or trigger input tai out pin function pulse output (tai out is selected by corresponding function select registers a, b and c) read from timer when timer ai register is read, it indicates an indeterminate value write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 145 bit name timer ai mode register (i = 0 to 4) (pulse width modulator mode) function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 1 : pulse width modulator (pwm) mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 2n 1 1 : f c32 b7 b6 tck1 tck0 count source select bit w r 16/8-bit pwm mode select bit 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator trigger select bit external trigger select bit 0: falling edge of tai in pin's input signal (note 2) 1: rising edge of tai in pin's input signal (note 2) 0: count start flag is valid 1: selected by event/trigger select register note 1: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0342 16 and 0343 16 ). if timer overflow is selected, this bit can be 1 or 0 . note 2: set the corresponding function select register a to i/o port, and port direction register to 0 . note 3: n = 0 to 15. n is set by the count source prescaler register (address 035f 16 ). aa aa a a aa a aa a aa a aa a aa a aa aa a a this bit is invalid in m32c/80 series. port output control is set by the function select registers a, b and c. CC symbol address when reset taimr(i=0 to 4) 0356 16 , 0357 16 , 0358 16 , 0359 16 , 035a 16 00000x00 2 (note 3) (note 1) figure 1.14.12. timer ai mode register in pulse width modulation mode
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer a 146 1 / f i x (2 C 1) 16 count source ta iin pin input signal pwm pulse output from ta iout pin condition : reload register = 0003 16 , when external trigger (rising edge of ta iin pin input signal) is selected trigger is not generated by this signal h h l l timer ai interrupt request bit 1 0 cleared to 0 when interrupt request is accepted, or cleared by software f i : frequency of count source (f 1 , f 8 , f 2n , f c32 ) note: n = 0000 16 to fffe 16 . 1 / f i x n count source (note1) ta iin pin input signal underflow signal of 8-bit prescaler (note2) pwm pulse output from ta iout pin h h h l l l 1 0 timer ai interrupt request bit cleared to 0 when interrupt request is accepted, or cleaerd by software f i : frequency of count source (f 1 , f 8 , f 2n , f c32 ) note 1: the 8-bit prescaler counts the count source. note 2: the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. note 3: m = 00 16 to ff 16 ; n = 00 16 to fe 16 . aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa condition : reload register high-order 8 bits = 02 16 reload register low-order 8 bits = 02 16 external trigger (falling edge of ta iin pin input signal) is selected 1 / f i x (m + 1) x (2 C 1) 8 1 / f i x (m + 1) x n 1 / f i x (m + 1) figure 1.14.13. example of how a 16-bit pulse width modulator operates figure 1.14.14. example of how an 8-bit pulse width modulator operates
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer b 147 timer b figure 1.15.1 shows the block diagram of timer b. figures 1.15.2 and 1.15.4 show the timer b-related registers. use the timer bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode. timer b has three operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer overflow. ? pulse period/pulse width measuring mode: the timer measures an external signal's pulse period or pulse width. figure 1.15.1. block diagram of timer b figure 1.15.2. timer b-related registers (1) clock source selection (address 0340 16 ) ? event counter ? timer ? pulse period/pulse width measurement reload register (16) low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 1 f 8 f 32 tbj overflow (j = i C 1. note, however, j = 2 when i = 0, j = 5 when i = 3) can be selected in only event counter mode count start flag f c32 polarity switching and edge pulse tbi in (i = 0 to 5) counter reset circuit counter (16) tbi address tbj timer b0 0351 16 0350 16 timer b2 timer b1 0353 16 0352 16 timer b0 timer b2 0355 16 0354 16 timer b1 timer b3 0311 16 0310 16 timer b5 timer b4 0313 16 0312 16 timer b3 timer b5 0315 16 0314 16 timer b4 note 1: read and write data in 16-bit units. note 2: counts external pulses input or a timer overflow. timer bi register (i = 0 to 6) (note 1) symbol address when reset tbi (i = 0 to 2) 0351 16 ,0350 16 , 0353 16 ,0352 16 , 0355 16 ,0354 16 indeterminate tbi (i = 3 to 5) 0311 16 ,0310 16 , 0313 16 ,0312 16 , 0315 16 ,0314 16 indeterminate b7 b0 b7 b0 (b15) (b8) w r timer mode function values that can be set event counter mode pulse period / pulse width measurement mode 0000 16 to ffff 16 0000 16 to ffff 16 16-bit counter (set to dividing ratio) 16-bit counter (set to dividing ratio) measures a pulse period or width (note 2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer b 148 figure 1.15.3. timer b-related registers (2) timer bi mode register (i = 0 to 5) symbol address when reset tbimr(i=0 to 5) 035b 16 , 035c 16 , 035d 16 , 031b 16 , 031c 16 , 031db 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode 1 1 : don't set it up b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit operation mode select bit function varies with each operation mode note 1: bit 4 is valid only by timer b0 and timer b3. note 2: in timer b1, timer b2, timer b4 and timer b5, nothing is assigned by bit 4(there is not r/w). when write, set 0 . when read, its content is indeterminate. (note 1) (note 2) symbol address when reset tabsr 0340 16 00 16 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer b 149 symbol address when reset cpsrf 0341 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 clock prescaler reset flag 0 : ignored 1 : prescaler is reset (when read, the value is 0 ) cpsr w r nothing is assigned. when write, set 0 . when read, their contents are indeterminate. a a a a symbol address when reset tbsr 0300 16 000xxxxx 2 timer b3, b4,b5 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b5 count start flag timer b4 count start flag timer b3 count start flag tb5s tb4s tb3s 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting nothing is assigned. when write, set "0". when read, its content is indeterminate. figure 1.15.4. timer b-related registers (3)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer b 150 (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.15.1.) figure 1.15.5 shows the timer bi mode register in timer mode. table 1.15.1. timer specifications in timer mode item specification count source f 1 , f 8 , f 2n , f c32 count operation ? counts down ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(m+1)m : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbiin pin function programmable i/o port read from timer count value is read out by reading timer bi register write to timer ? when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) figure 1.15.5. timer bi mode register in timer mode timer bi mode register (i = 0 to 5) (timer mode) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode. can be 0 or 1 . mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 2n 1 1 : f c32 tck1 tck0 count source select bit nothing is assigned. (i = 1, 2, 4, 5) when write, set "0". when read, its content is indeterminate. 0 (set to 0 in timer mode) b7 b6 a a a a a a a a a a a a a a a a a a symbol address when reset tbimr(i=0 to 5) 035b 16 , 035c 16 , 035d 16 , 031b 16 , 031c 16 , 031d 16 00xx0000 2 note 1: r/w is valid only in timer b0 and timer b3. note 2: in timer b1, timer b2, timer b4 and timer b5, nothing is assigned by bit 4(there is not r/w). when write, set 0 . when read, its content is indeterminate. note 3: n = 0 to 15. n is set by the count source prescaler register (address 035f 16 ). (note 3) (note 1) invalid in timer mode. when write, set "0". when read in timer mode, its content is indeterminate. (note 2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer b 151 (2) event counter mode in this mode, the timer counts an external signal or an internal timer's overflow. (see table 1.15.2.) figure 1.15.6 shows the timer bi mode register in event counter mode. table 1.15.2 . timer specifications in event counter mode item specification count source ? external signals input to tbi in pin effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software ? tbj overflows or underflows count operation ? counts down ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbiin pin function count source input (set the corresponding function select register a to i/o port.) read from timer count value can be read out by reading timer bi register write to timer ? when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) timer bi mode register (i = 0 to 5) (event counter mode) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aa aa operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 count polarity select bit mr2 mr1 mr3 nothing is assigned. (i = 1, 2, 4, 5) when write, set 0 . when read, its content is indeterminate. tck1 tck0 0 0 : counts external signal's falling edges 0 1 : counts external signal's rising edges 1 0 : counts external signal's falling and rising edges 1 1 : inhibited b3 b2 note 1: valid only when input from the tbi in pin is selected as the event clock. if timer's overflow is selected, this bit can be 0 or 1 . note 2: r/w is valid only in timer b0 and timer b3. note 3: in timer b1, timer b2, timer b4 and timer b5, nothing is assigned by bit 4(there is not r/w). when write, set 0 . when read, its content is indeterminate. note 4: set the corresponding function select register a to i/o port, and port direction register to 0 . note 5: j = i C 1; however, j = 2 when i = 0, j = 5 when i = 3. invalid in event counter mode. can be 0 or 1 . event clock select bit 0 : input from tbi in pin 1 : tbj overflow 0 (set to 0 in event counter mode) a a a a a a a a a a a a a a a a symbol address when reset tbimr(i=0 to 5) 035b 16 , 035c 16 , 035d 16 , 031b 16 , 031c 16 , 031d 16 00xx0000 2 (note 1) (note 3) (note 4) (note 5) invalid in event counter mode. when write, set "0". when read in event counter mode, its content is indeterminate. (note 2) figure 1.15.6. timer bi mode register in event counter mode
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer b 152 (3) pulse period/pulse width measurement mode in this mode, the timer measures the pulse period or pulse width of an external signal. (see table 1.15.3.) figure 1.15.7 shows the timer bi mode register in pulse period/pulse width measurement mode. figure 1.15.8 shows the operation timing when measuring a pulse period. figure 1.15.9 shows the operation timing when measuring a pulse width. table 1.15.3. timer specifications in pulse period/pulse width measurement mode item specification count source f 1 , f 8 , f 2n , f c32 count operation ? count up ? counter value 0000 16 is transferred to reload register at measurement pulse's effective edge and the timer continues counting count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing ? when measurement pulse's effective edge is input (note 1) ? when an overflow occurs. (simultaneously, the timer bi overflow flag changes to 1 . the timer bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer bi mode register.) tbiin pin function measurement pulse input (set the corresponding function select register a to i/o port.) read from timer when timer bi register is read, it indicates the reload register s content (measurement result) (note 2) write to timer cannot be written to note 1: an interrupt request is not generated when the first effective edge is input after the timer has started counting. note 2: the value read out from the timer bi register is indeterminate until the second effective edge is input after the timer.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer b 153 timer bi mode register (i = 0 to 5) (pulse period / pulse width measurement mode) bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : pulse period / pulse width measurement mode b1 b0 tmod1 tmod0 mr0 measurement mode select bit mr2 mr1 mr3 tck1 tck0 0 0 : pulse period measurement 1 0 1 : pulse period measurement 2 1 0 : pulse width measurement 1 1 : must not be set function b3 b2 count source select bit timer bi overflow flag 0 : timer did not overflow 1 : timer has overflowed 0 0 : f 1 0 1 : f 8 1 0 : f 2n 1 1 : f c32 b7 b6 0 (set to 0 in pulse period/pulse width measurement mode) aa aa a a aa a aa aa a a aa a aa a aa a aa a note 1: do the next measurement, in the measurement mode select bit. pulse period measurement 1 (bit 3, bit 2= 0 0 ) : interval between measurement pulse's falling edge to falling edge. pulse period measurement 2 (bit 3, bit 2= 0 1 ) : interval between measurement pulse's rising edge to rising edge. pulse width measurement (bit 3, bit 2= 1 0 ) : interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge. note 2: r/w is valid only in timer b0 and timer b3. note 3: in timer b1, timer b2, timer b4 and timer b5, nothing is assigned by bit 4(there is not r/w). when write, set 0 . when read, its content is indeterminate. note 4: it is indeterminate when reset. the timer bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer bi mode register. this flag cannot be set to 1 by software. note 5: n = 0 to 15. n is set by the count source prescaler register (address 035f 16 ). symbol address when reset tbimr(i=0 to 5) 035b 16 , 035c 16 , 035d 16 , 031b 16 , 031c 16 , 031d 16 00xx0000 2 (note 4) (note 1) (note 3) nothing is assigned (i = 1, 2, 4, 5). when write, set "0". when read, its content is indeterminate. (note 2) (note 5) figure 1.15.7. timer bi mode register in pulse period/pulse width measurement mode
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timer b 154 measurement pulse h count source count start flag timer bi interrupt request bit timing at which counter reaches 0000 16 1 1 transfer (measured value) transfer (measured value) l 0 0 timer bi overflow flag 1 0 note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) (note 1) transfer (measured value) (note 1) cleared to 0 when interrupt request is accepted, or cleared by software. (note 2) transfer (indeterminate value) reload register counter transfer timing count source measurement pulse count start flag timer bi interrupt request bit timing at which counter reaches 0000 16 h 1 transfer (indeterminate value) l 0 0 timer bi overflow flag 1 0 note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) when measuring measurement pulse time interval from falling edge to falling edge (note 2) cleared to 0 when interrupt request is accepted, or cleared by software. transfer (measured value) 1 reload register counter transfer timing figure 1.15.8. operation timing when measuring a pulse period figure 1.15.9. operation timing when measuring a pulse width
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 155 three-phase motor control timers functions use of more than one built-in timer a and timer b provides the means of outputting three-phase motor driving waveforms. figures 1.16.1 through 1.16.5 show registers related to timers for three-phase motor control. three-phase pwm control register 0 (note 4) symbol address when reset invc0 0308 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 effective interrupt output polarity select bit inv00 bit symbol bit name description rw inv01 effective interrupt output specification bit inv02 mode select bit inv04 positive and negative phases concurrent l output disable function enable bit inv07 software trigger bit inv06 modulation mode select bit inv05 positive and negative phases concurrent l output detect flag inv03 output control bit 0: a timer b2 interrupt occurs when the timer a1 reload control signal is 1 . 1: a timer b2 interrupt occurs when the timer a1 reload control signal is 0 . 0: not specified. 1: selected by the inv00 bit. 0: normal mode 1: three-phase pwm output mode 0: output disabled 1: output enabled 0: feature disabled 1: feature enabled 0: not detected yet 1: already detected 0: triangular wave modulation mode 1: sawtooth wave modulation mode 0: ignored 1: trigger generated (note 6) (note 7) (note 3) (note 3) (note 8) (note 5) (note 2) note 1: set bit 1 of the protect register (address 000a 16 ) to 1 before writing to this register. note 2: set bit 1 of this register to 1 after setting timer b2 interrupt occurrences frequency set counter. note 3: effective only in three-phase mode 1(three-phase pwm control register's bit 1 = 1 ). note 4: selecting three-phase pwm output mode causes the dead time timer, the u, v, w phase output control circuits, and the timer b2 interrupt frequency set circuit works. for u, u, v, v, w and w output from p8 0 , p8 1 , and p7 2 through p7 5 , setting of function select registers a, b and c is required. note 5: no value other than 0 can be written. note 6: the dead time timer starts in synchronization with the falling edge of timer ai output. the data transfer from the three-phase buffer register to the three-phase output shift register is made only once in synchronization with the transfer trigger signal after writing to the three-phase output buffer register. note 7: the dead time timer starts in synchronization with the falling edge of timer a output and with the transfer trigger signal. the data transfer from the three-phase output buffer register to the three-phase output shift register is made with respect to every transfer trigger. note 8: the value, when read, is 0 . (note 4) figure 1.16.1. registers related to timers for three-phase motor control
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 156 three-phase pwm control register 1 (note 1) symbol address when reset invc1 0309 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 timer ai start trigger signal select bit inv10 bit symbol bit name description rw inv11 timer a1-1, a2-1, a4-1 control bit inv12 dead time timer count source select bit inv14 output polarity control bit inv17 waveform reflect timing select bit inv16 dead time timer trigger select bit inv15 dead time invalid bit inv13 carrier wave detect flag 0: timer b2 overflow signal 1: timer b2 overflow signal, signal for writing to timer b2 0: three-phase mode 0 1: three-phase mode 1 0 : f 1 1 : f 1 /2 0: rising edge of triangular waveform 1: falling edge of triangular waveform 0 : low active 1 : high active 0: dead time valid bit 1: dead time invalid bit 0: triggers from corresponding timer 1: rising edge of corresponding phase output 0: synchronized with raising edge of triangular waveform 1: synchronized with timer b2 overflow (note 4) note 1: set bit 1 of the protect register (address 000a 16 ) to 1 before writing to this register. note 2: inv13 is valid only in triangular waveform mode (inv06=0) and three-phase mode (inv11=1). note 3:usually set to 1 . note 4:inv17 is valid only in three-phase mode 1. three-phase output buffer register i (i=0, 1) (note) symbol address when reset idbi (i=0,1) 030a 16 , 030b 16 xx00 0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. when write, set 0 . when read, their contents are 0 . dui dubi dvi dwi dvbi dwbi u phase output buffer i setting in u phase output buffer i v phase output buffer i w phase output buffer i u phase output buffer i v phase output buffer i w phase output buffer i setting in v phase output buffer i setting in w phase output buffer i setting in w phase output buffer i setting in v phase output buffer i setting in u phase output buffer i note: when executing read instruction of this register, the contents of three-phase shift register is read out. (note 3) (note 2) figure 1.16.2. registers related to timers for three-phase motor control
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 157 dead time timer (note) symbol address when reset dtt 030c 16 indeterminate function values that can be set w r b7 b0 8-bits counter (set dead time timer) 1 to 255 note: use mov instruction to write to this register. timer b2 interrupt occurrences frequency set counter (note 1 to 4) symbol address when reset ictb2 030d 16 indeterminate function values that can be set w r b7 b0 set occurrence frequency of timer b2 interrupt request 1 to 15 note 1: use mov instruction to write to this register. note 2: when the effective interrupt output specification bit (inv01: bit 1 at 0308 16 ) is set to 1 and three-phase motor control timer is operating, do not rewrite to this register. note 3: do not write to this register at the timing of timer b2 overflow. note 4: setting of this register is valid only when bit 2 (inv02) of three-phase pwm control register 0 is set to "1". nothing is assigned. when write, set to 0 . symbol address when reset tai (i 1, 2, 4) 0349 16 ,0348 16 , 034b 16 ,034a 16 , 034f 16 ,034e 16 indeterminate tai1 (i 1, 2, 4) 0303 16 ,0302 16 , 0305 16 ,0304 16 , 0307 16 ,0306 16 indeterminate b7 b0 b7 b0 (b15) (b8) w r 0000 16 to ffff 16 function values that can be set timer ai, ai-1 register (note 1 to 3) note 1: read and write data in 16-bit units. note 2: when set 0000 16 to the timer ai register, counter doesn't move, and timer ai interrupt isn't generated. note 3: use mov instruction to write to this register. three-phase pwm pulse width modulator (decide pwm output pulse width) symbol address when reset tb2 0355 16 ,0354 16 indeterminate b7 b0 b7 b0 (b15) (b8) w r 0000 16 to ffff 16 function values that can be set timer b2 register (note) note : read and write data in 16-bit units. set the period of carrier wave figure 1.16.3. registers related to timers for three-phase motor control
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 158 pwcom symbol address when reset tb2sc 035e 16 xxxxxxx0 2 timer b2 reload timing switching bit 0 : next underflow 1 : synchronized rising edge of triangular wave timer b2 special mode register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 w r a aa nothing is assigned. when write, set 0 . when read, its content is 0 . ta1tgl symbol address when reset trgsr 0343 16 00 16 timer a1 event/trigger select bit set bit 1 and bit 0 to 0 1 before using to the v phase output control circuit. trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 w r ta1tgh a aa a aa note: set the corresponding port function select register a to i/o port, and port direction register to 0 . ta2tgl timer a2 event/trigger select bit set bit 3 and bit 2 to 0 1 before using to the w phase output control circuit. ta2tgh a a aa aa a a aa aa ta4tgl timer a4 event/trigger select bit set bit 7 and bit 6 to 0 1 before using to the u phase output control circuit. ta4tgh a aa a aa ta3tgl ta3tgh (note) (note) (note) inhibited in three-phase pwm mode. symbol address when reset tabsr 0340 16 00 16 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting 0 : stops counting 1 : starts counting figure 1.16.4. registers related to timers for three-phase motor control
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 159 three-phase motor driving waveform output mode (three-phase pwm output mode) setting 1 in the mode select bit (bit 2 at 0308 16 ) shown in figure 1.16.1 causes three-phase pwm output mode that uses four timers a1, a2, a4, and b2. as shown in figure 1.16.4 and 1.16.5 set timers a1, a2, and a4 in one-shot timer mode, set the trigger in timer b2, and set timer b2 in timer mode using the respective timer mode registers. timer ai mode register (i = 1, 2, 4) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 (set to 0 in one-shot timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 2n 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 1 : selected by event/trigger select register trigger select bit external trigger select bit w r a a aa aa a aa a aa a a aa aa a a aa aa a a aa aa a aa this bit is invalid in m32c/80 series. port output control is set by the function select registers a, b and c. symbol address when reset taimr(i=1, 2, 4) 0357 16 , 0358 16 , 035a 16 00000x00 2 invalid in three-phase pwm output mode. 0 1 01 timer b2 mode register bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode can be 0 or 1 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 2n 1 1 : f c32 tck1 tck0 count source select bit invalid in timer mode. when write, set 0 . when read in timer mode, its content is indeterminate. 0 (set to 0 in timer mode) b7 b6 symbol address when reset tb2mr 035d 16 00xx0000 2 a aa a aa a aa a a aa aa a aa a aa a aa 0 0 0 (note) note: n = 0 to 15. n is set by the count source prescaler register (address 035f 16 ). note: n = 0 to 15. n is set by the count source prescaler register (address 035f 16 ). (note) figure 1.16.5. timer mode registers in three-phase pwm output mode
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 160 figure 1.16.6 shows the block diagram for three-phase waveform mode. the low active output polarity in three-phase waveform mode, the positive-phase waveforms (u phase, v phase, and w phase) and ___ ___ ___ negative waveforms (u phase, v phase, and w phase), six waveforms in total, are output from p8 0 , p8 1 , p7 2 , p7 3 , p7 4 , and p7 5 as active on the l level. of the timers used in this mode, timer a4 controls the ___ ___ u phase and u phase, timer a1 controls the v phase and v phase, and timer a2 controls the w phase ___ and w phase respectively; timer b2 controls the periods of one-shot pulse output from timers a4, a1, and a2. in outputting a waveform, dead time can be set so as to cause the l level of the positive waveform ___ output (u phase, v phase, and w phase) not to lap over the l level of the negative waveform output (u ___ ___ phase, v phase, and w phase). to set short circuit time, use three 8-bit timers, sharing the reload register, for setting dead time. a value from 1 through 255 can be set as the count of the timer for setting dead time. the timer for setting dead time works as a one-shot timer. if a value is written to the dead timer (030c 16 ), the value is written to the reload register shared by the three timers for setting dead time. any of the timers for setting dead time takes the value of the reload register into its counter, if a start trigger comes from its corresponding timer, and performs a down count in line with the clock source selected by the dead time timer count source select bit (bit 2 at 0309 16 ). the timer can receive another trigger again before the workings due to the previous trigger are completed. in this instance, the timer performs a down count from the reload register s content after its transfer, provoked by the trigger, to the timer for setting dead time. since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger comes; it stops outputting pulses as soon as its content becomes 00 16 , and waits for the next trigger to come. ___ ___ the positive waveforms (u phase, v phase, and w phase) and the negative waveforms (u phase, v ___ phase, and w phase) in three-phase waveform mode are output, from respective ports by means of setting 1 in the output control bit (bit 3 at 0308 16 ). setting 0 in this bit causes the ports to be the high- impedance state. this bit can be set to 0 not only by use of the applicable instruction, but by entering _______ a falling edge in the nmi terminal or by resetting. also, if 1 is set in the positive and negative phases concurrent l output disable function enable bit (bit 4 at 0308 16 ) causes one of the pairs of u phase and ___ ___ ___ u phase, v phase and v phase, and w phase and w phase concurrently go to l , as a result, the output control bit becomes the high-impedance state.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 161 timer b2 (timer mode) overflow interrupt occurrence frequency set counter interrupt request bit u(p8 0 ) u(p8 1 ) v(p7 2 ) v(p7 3 ) w(p7 4 ) w(p7 5 ) nmi reset r d d t q d t q d t q d t q for short circuit prevention d t q d t q q inv0 3 inv0 5 diagram for switching to p8 0 , p8 1 and p7 2 - p7 5 is not shown. inv0 4 timer a4 counter (one-shot timer mode) (one-shot timer mode) (one-shot timer mode) trigger timer a4 reload timer a4-1 timer a1 counter trigger timer a1 reload timer a1-1 timer a2 counter trigger timer a2 reload timer a2-1 inv0 7 t q inv1 1 dead time timer setting (8) inv0 0 1 0 inv0 1 inv1 1 du0 du1 t dq t dq dub0 dub1 t dq t dq u phase output control circuit u phase output signal u phase output signal v phase output control circuit to be set to 0 when timer a4 stops t q inv1 1 to be set to 0 when timer a1 stops t q inv1 1 to be set to 0 when timer a2 stops w phase output control circuit v phase output signal w phase output signal v phase output signal w phase output signal signal to be written to b2 trigger signal for timer ai start trigger signal for transfer inv1 0 circuit for interrupt occurrence frequency set counter bit 0 at 030b 16 bit 0 at 030a 16 three-phase output shift register (u phase) a f 1 0 1 1/2 n = 1 to 15 reload register dead time timer setting (8) n = 1 to 255 dead time timer setting (8) n = 1 to 255 n = 1 to 255 trigger inv0 6 trigger trigger trigger trigger trigger inv0 6 inv0 6 inv1 4 inv1 3 figure 1.16.6. block diagram for three-phase waveform mode
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 162 triangular wave modulation to generate a pwm waveform of triangular wave modulation, set 0 in the modulation mode select bit (bit 6 at 0308 16 ). also, set 1 in the timers a4-1, a1-1, a2-1 control bit (bit 1 at 0309 16 ). in this mode, each of timers a4, a1, and a2 has two timer registers, and alternately reloads the timer register s con- tent to the counter every time timer b2 counter s content becomes 0000 16 . if 0 is set to the effective interrupt output specification bit (bit 1 at 0308 16 ), the frequency of interrupt requests that occur every time the timer b2 counter s value becomes 0000 16 can be set by use of the timer b2 counter (030d 16 ) for setting the frequency of interrupt occurrences. the frequency of occurrences is given by (setting; setting 0). setting 1 in the effective interrupt output specification bit (bit 1 at 0308 16 ) provides the means to choose which value of the timer a1 reload control signal to use, 0 or 1 , to cause timer b2 s interrupt request to occur. to make this selection, use the effective interrupt output polarity selection bit (bit 0 at 0308 16 ). an example of u phase waveform is shown in figure 1.16.7, and the description of waveform output workings is given below. set 1 in du0 (bit 0 at 030a 16 ). and set 0 in dub0 (bit 1 at 030a 16 ). in addition, set 0 in du1 (bit 0 at 030b 16 ) and set 1 in dub1 (bit 1 at 030b 16 ). also, set 0 in the effective interrupt output specification bit (bit 1 at 0308 16 ) to set a value in the timer b2 interrupt occur- rence frequency set counter. by this setting, a timer b2 interrupt occurs when the timer b2 counter s content becomes 0000 16 as many as (setting) times. furthermore, set 1 in the effective interrupt output specification bit (bit 1 at 0308 16 ), set in the effective interrupt polarity select bit (bit 0 at 0308 16 ) and set 1 in the interrupt occurrence frequency set counter (030d 16 ). these settings cause a timer b2 interrupt to occur every other interval when the u phase output goes to h . when the timer b2 counter s content becomes 0000 16 , timer a4 starts outputting one-shot pulses. in this instance, the content of du1 (bit 0 at 030b 16 ) and that of du0 (bit 0 at 030a 16 ) are set in the three-phase output shift register (u phase), the content of dub1 (bit 1 at 030b 16 ) and that of dub0 (bit 1 at 030a 16 ) ___ are set in the three-phase shift register (u phase). after triangular wave modulation mode is selected, however, no setting is made in the shift register even though the timer b2 counter s content becomes 0000 16 . ___ the value of du0 and that of dub0 are output to the u terminal (p8 0 ) and to the u terminal (p8 1 ) respectively. when the timer a4 counter counts the value written to timer a4 (034f 16 , 034e 16 ) and when timer a4 finishes outputting one-shot pulses, the three-phase shift register s content is shifted one posi- ___ tion, and the value of du1 and that of dub1 are output to the u phase output signal and to u phase output signal respectively. at this time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the l level of the u phase waveform doesn t overlap the low level ___ of the u phase waveform, which has the opposite phase of the former. the u phase waveform output that started from the h level keeps its level until the timer for setting dead time finishes outputting one- shot pulses even though the three-phase output shift register s content changes from 1 to 0 by the effect of the one-shot pulses. when the timer for setting dead time finishes outputting one-shot pulses, 0 already shifted in the three-phase shift register goes active, and the u phase waveform changes to the low level. when the timer b2 counter s content becomes 0000 16 , the timer a4 counter starts count- ing the value written to timer a4-1 (0307 16 , 0306 16 ), and starts outputting one-shot pulses. when timer a4 finishes outputting one-shot pulses, the three-phase shift register s content is shifted one position, but if the three-phase output shift register s content changes from 0 to 1 as a result of the shift, the output level changes from l to h without waiting for the timer for setting dead time to finish outputting one-shot pulses. a u phase waveform is generated by these workings repeatedly. with the exception that the three-phase output shift register on the u phase side is used, the workings in generating a u
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 163 timer a4 output trigger signal for timer ai start (timer b2 overflow signal) timer b2 u phase a carrier wave of triangular waveform carrier wave signal wave u phase output signal control signal for timer a4 reload u phase u phase output signal mn nmpo note 1: when inv14="0" (output wave low active) note 2: when inv14="1" (output wave high active) note 3: set to trian g ular wave modulation mode and to three- p hase mode 1. m inv13(triangular wave modulation detect flag) (note 1) (note 2) (note 3) u phase u phase dead time dead time timber b2 interrupt occurres rewriting timer a4 and timer a4-1. possible to set the number of overflows to generate an interrupt by use of the interrupt occurrences frequency set circuit the three-phase shift register shifts in synchronization with the falling edge of the a4 output. phase waveform, which has the opposite phase of the u phase waveform, are the same as in generating a u phase waveform. in this way, a waveform can be picked up from the applicable terminal in a manner in which the l level of the u phase waveform doesn t lap over that of the u phase waveform, which has the opposite phase of the u phase waveform. the width of the l level too can be adjusted by varying ___ ___ the values of timer b2, timer a4, and timer a4-1. in dealing with the v and w phases, and v and w phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to ___ dealing with the u and u phases to generate an intended waveform. figure 1.16.7. timing chart of operation (1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 164 timer a4 output trigger signal for timer ai start (timer b2 overflow signal) timer b2 u phase dead time a carrier wave of triangular waveform carrier wave signal wave rewriting timer a4 every timer b2 interrupt occurres. u phase output signal m nn mp o note: set to triangular wave modulation mode and to three-phase mode 1. control signal for timer a4 reload m u phase u phase output signal timer b2 interrupt occurres. rewriting three-phase buffer register. assigning certain values to du0 (bit 0 at 030a 16 ) and dub0 (bit 1 at 030a 16 ), and to du1 (bit 0 at 030b 16 ) and dub1 (bit 1 at 030b 16 ) allows you to output the waveforms as shown in figure 1.16.8, that ___ ___ is, to output the u phase alone, to fix u phase to h , to fix the u phase to h, or to output the u phase alone. figure 1.16.8. timing chart of operation (2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 165 sawtooth modulation to generate a pwm waveform of sawtooth wave modulation, set 1 in the modulation mode select bit (bit 6 at 0308 16 ). also, set 0 in the timers a4, a1, and a2-1 control bit (bit 1 at 0309 16 ). in this mode, the timer registers of timers a4, a1, and of a2 comprise conventional timers a4, a1, and a2 alone, and reload the corresponding timer register s content to the counter every time the timer b2 counter s con- tent becomes 0000 16 . the effective interrupt output specification bit (bit 1 at 0308 16 ) and the effective interrupt output polarity select bit (bit 0 at 0308 16 ) go nullified. an example of u phase waveform is shown in figure 1.16.9, and the description of waveform output workings is given below. set 1 in du0 (bit 0 at 030a 16 ), and set 0 in dub0 (bit 1 at 030a 16 ). in addition, set 0 in du1 (bit 0 at 030b 16 ) and set 1 in dub1 (bit 1 at 030b 16 ). when the timber b2 counter s content becomes 0000 16 , timer b2 generates an interrupt, and timer a4 starts outputting one-shot pulses at the same time. in this instance, the contents of the three-phase buffer registers du1 and du0 are set in the three-phase output shift register (u phase), and the contents of dub1 and dub0 are set in the three-phase output register (u phase). after this, the three-phase buffer register s content is set in the three-phase shift register every time the timer b2 counter s content becomes 0000 16 . ___ the value of du0 and that of dub0 are output to the u terminal (p8 0 ) and to the u terminal (p8 1 ) respectively. when the timer a4 counter counts the value written to timer a4 (034f 16 , 034e 16 ) and when timer a4 finishes outputting one-shot pulses, the three-phase output shift register s content is shifted one position, and the value of du1 and that of dub1 are output to the u phase output signal and to the ___ u output signal respectively. at this time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the l level of the u phase waveform doesn t lap over the l level ___ of the u phase waveform, which has the opposite phase of the former. the u phase waveform output that started from the h level keeps its level until the timer for setting dead time finishes outputting one- shot pulses even though the three-phase output shift register s content changes from 1 to 0 by the effect of the one-shot pulses. when the timer for setting dead time finishes outputting one-shot pulses, 0 already shifted in the three-phase shift register goes effective, and the u phase waveform changes to the l level. when the timer b2 counter s content becomes 0000 16 , the contents of the three-phase buffer registers du1 and du0 are set in the three-phase shift register (u phase), and the contents of ___ dub1 and dub0 are set in the three-phase shift register (u phase) again. a u phase waveform is generated by these workings repeatedly. with the exception that the three- ___ ___ phase output shift register on the u phase side is used, the workings in generating a u phase waveform, which has the opposite phase of the u phase waveform, are the same as in generating a u phase waveform. in this way, a waveform can be picked up from the applicable terminal in a manner in which the l level of the u phase waveform doesn t lap over that of the u phase waveform, which has the opposite phase of the u phase waveform. the width of the l level can also be adjusted by varying the ___ ___ values of timer b2 and timer a4. in dealing with the v and w phases, and v and w phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with the u and ___ u phases to generate an intended waveform.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 166 timer b2 timer a4 output u phase u phase dead time carrier wave signal wave a carrier wave of sawtooth waveform m n o p note: set to sawtooth modulation mode and to three-phase mode 0. interrupt occurres. rewriting the value of timer a4. u phase output signal u phase output signal the three-phase shift registers shifts in synchronization with the falling edge of timer a4. data transfer is made from the three- phase buffer registers to the three- phase shift registers in step with the timing of the timer b overflow. trigger signal for timer ai start (timer b2 overflow signal) figure 1.16.9. timing chart of operation (3)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 167 timer b2 timer a4 output u phase u phase dead time carrier wave signal wave a carrier wave of sawtooth waveform mn p note: set to sawtooth modulation mode and to three- p hase mode 0. u phase output signal u phase output signal the three-phase shift registers shifts in synchronization with the falling edge of timer a4. trigger signal for timer ai start (timer b2 overflow signal) interrupt occurres. rewriting the value of timer a4. rewriting three-phase output buffer register data transfer is made from the three- phase buffer registers to the three- phase shift registers in step with the timing of the timer b overflow. interrupt occurres. rewriting the value of timer a4. ___ setting 1 both in dub0 and in dub1 provides a means to output the u phase alone and to fix the u phase output to h as shown in figure 1.16.10. figure 1.16.10. timing chart of operation (4)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer serial i/o 168 serial i/o serial i/o is configured as five channels: uart0 to uart4. uarti (i=0 to 4) each have an exclusive timer to generate a transfer clock, so they operate independently of each other. figure 1.17.1 shows the block diagram of uarti. uarti has two operation modes: a clock synchronous serial i/o mode and a clock asynchronous serial i/o mode (uart mode). the contents of the serial i/o mode select bits (bits 0 to 2 at addresses 0368 16 , 02e8 16 , 0338 16 , 0328 16 and 02f8 16 ) determine whether uarti is used as a clock synchronous serial i/o or as a uart. it has the bus collision detection function that generates an interrupt request if the txd pin and the rxd pin are different in level. figures 1.17.2 through 1.17.8 show the registers related to uarti.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer serial i/o 169 ni : values set to uarti bit rate generator (uibrg) rxdi reception control circuit transmission control circuit 1 / (ni+1) 1/16 1/16 1/2 bit rate generator clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clki ctsi / rtsi f 1 f 8 f 2n vcc rts 2 cts 2 txdi rxd polarity reversing circuit txd polarity reversing circuit cts/rts disabled cts/rts disabled cts/rts selected clk polarity reversing circuit internal external clock source selection transmit/ receive unit (note) note :uart 2 is not cmos output but n channel open drain output. sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type data bus low-order bits txdi uarti transmit register par disabled par enabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 uarti transmit buffer register uart (8 bits) uart (9 bits) clock synchronous type uarti receive buffer register uarti receive register 2sp 1sp uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type rxdi uart (8 bits) uart (9 bits) address 036e 16 address 036f 16 address 02ee 16 address 02ef 16 address 033e 16 address 033f 16 address 032e 16 address 032f 16 address 02fe 16 address 02ff 16 address 036a 16 address 036b 16 address 02ea 16 address 02eb 16 address 033a 16 address 033b 16 address 032a 16 address 032b 16 address 02fa 16 address 02fb 16 data bus high-order bits d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par 0 reverse no reverse error signal output circuit rxd data reverse circuit error signal output enable error signal output disable reverse no reverse logic reverse circuit + msb/lsb conversion circuit logic reverse circuit + msb/lsb conversion circuit par enabled par disabled uart clock synchronous type txd data reverse circuit sp : stop bit par : parity bit i : 0 to 4 figure 1.17.1. block diagram of uarti
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer serial i/o 170 uarti transmit buffer register (i=0 to 4) (note) symbol address when reset uitb(i=0,1,2) 036b 16 , 036a 16 , 02eb 16 , 02ea 16 , 033b 16 , 033a 16 indeterminate uitb(i=3,4) 032b 16 , 032a 16 , 02fb 16 , 02fa 16 indeterminate rw function (clock synchronous serial i/o mode) transmit data transmit data nothing is assigned. when write, set "0". when read, their contents are indeterminate. function (uart mode) transmit data (9th bit) note: use mov instruction to write to this register. b7 b0 b15 (b7) b8 (b0) bit symbol uarti receive buffer register (i = 0 to 4) bit name bit symbol symbol address when reset uirb(i=0,1,2) 036f 16, 036e 16, 02ef 16, 02ee 16, 033f 16, 033e 16 indeterminate uirb(i=3,4) 032f 16, 032e 16, 02ff 16, 02fe 16 indeterminate rw note 1: arbitration lost detecting flag must always write "0". note 2: bits 15 through 12 are set to 000 2 when the serial i/o mode select bit (bits 2 to 0 at addresses 0368 16 , 02e8 16 , 0338 16 , 0328 16 , 02f8 16 ) are set to "000 2 " or the receive enable bit is set to "0". (bit 15 is set to "0" when bits 14 to 12 all are set to "0".) bits 14 and 13 are also set to "0" when the lower byte of the uarti receive buffer register (addresses 036e 16 , 02ee 16 , 033e 16 , 032e 16 , 02fe 16 ) is read. receive data receive data abt oer fer sum function (clock synchronous serial i/o mode) per function (uart mode) overrun error flag (note 2) arbitration lost detecting flag (note 1) framing error flag (note 2) parity error flag (note 2) (note 2) error sum flag receive data (9th bit) 0: not detectet 1: detected 0: no overrun error 1: overrun error found invalid invalid 0: no overrun error 1: overrun error found 0: no framing error 1: framing error found 0: no parity error 1: parity error found 0: no error 1: error found invalid invalid b7 b0 b15 (b7) b8 (b0) nothing is assigned. when write, set "0". when read, their contents are indeterminate. figure 1.17.2. serial i/o-related registers (1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer serial i/o 171 function uarti bit rate generator (i=0 to 4) (note 1, 2) values that can be set symbol address when reset uibrg(i=0 to 4) 0369 16, 02e9 16, 0339 16, 0329 16, 02f9 16 indeterminate rw assuming that set value = n, brgi divides the count source by n+1 00 16 to ff 16 note 1: use mov instruction to write to this register. note 2: write a value to this register while transmit/receive halts. b7 b0 uarti transmit/receive mode register (i=0 to 4) symbol address when reset uimr(i=0 to 4) 0368 16, 02e8 16, 0338 16, 0328 16, 02f8 16 00 16 rw ckdir stps pry iopol prye smd0 smd2 smd1 serial i/o mode select bit internal/external clock select bit stop bit length select bit odd/even parity select bit parity enable bit txd,rxd input/ output polarity switch bit 0 0 0: serial i/o invalid 0 0 1: serial i/o mode 0 1 0: i 2 c mode b2 b1 b0 must not be set except above 0 0 0: serial i/o invalid 1 0 0: transfer data 7 bits long 1 0 1: transfer data 8 bits long 1 1 0: transfer data 9 bits long b2 b1 b0 0 : internal clock 1 : external clock (note 2) (note 1) (note 2) invalid invalid invalid 0: no reversed 1: reversed 0 : one stop bit 1 : two stop bits valid when bit 6 = "1" 0 : odd parity 1 : even parity 0 : parity disabled 1 : parity enabled (note 3) note 1: select clk output by the corresponding function select registers a, b and c. note 2: set the corresponding function select register a to the i/o port. note 3: normally set "0". 0 : internal clock 1 : external clock bit name bit symbol function (clock synchronous serial i/o mode) function (uart mode) must not be set except above b7 b6 b5 b4 b3 b2 b1 b0 figure 1.17.3. serial i/o-related registers (2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer serial i/o 172 uarti transmit/receive control register 0 (i=0 to 4) symbol address when reset uic0(i=0 to 4) 036c 16, 02ec 16, 033c 16, 032c 16, 02fc 16 08 16 rw txept crd nch (note 3) uform ckpol b1 b0 clk0 crs clk1 brg count source select bit cst/rts function select bit transmit register empty flag cts/rts disable bit data output select bit clk polarity select bit transfer format select bit ( note 4) ( note 2) ( note 1) valid when bit 4 = 0 0 : cts function is selected 1 : rts function is selected 0 0: f 1 is selected 0 1: f 8 is selected 1 0: f 2n is selected 1 1: must not be set 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled 0 : txdi pin is cmos output 1 : txdi pin is n-channel open drain output 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge 0 : lsb first 1 : msb first set to 0 bit name bit symbol function (clock synchronous serial i/o mode) function (uart mode) note 1: set the corresponding function select register a to i/o port, and port direction register to 0 note 2: select rts output using the corresponding function select registers a, b and c. note 3: uart2 transfer pin (txd2:p7 0 ) is n-channel open drain output. it is not set to cmos output. note 4: valid only in clock syncronous serial i/o mode and 8 bits uart mode. b7 b6 b5 b4 b3 b2 b1 b0 figure 1.17.4. serial i/o-related registers (3)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer serial i/o 173 uarti transmit/receive control register 1 (i=0 to 4) symbol address when reset uic1(i=0 to 4) 036d 16, 02ed 16, 033d 16, 032d 16, 02fd 16 02 16 rw ri uiirs uirrm uilch te re ti transmit enable bit transmit buffer empty flag receive enable bit receive complete flag clock divide synchronizing stop bit /e rror signal output enable bit sclkstpb /uiere uarti transmit interrupt cause select bit uarti continuous receive mode enable bit data logic select bit 0: transmission disabled 1: transmission enabled 0: data present in transmit buffer register 0: no data present in transmit buffer register 0: reception disabled 1: reception enabled 0: data present in receive buffer register 0: no data present in receive buffer register 0: transmit buffer empty (ti = 1) 1: transmit is completed (txept = 1) set to 0 0: continuous receive mode disabled 1: continuous receive mode enabled 0: no reverse 1: reverse clock divide synchronizing stop bit 0: synchronizing stop 1: synchronous start (note) note :when this bit and bit 7 of uarti special mode register 2 are set, clock synchronizing function is used. bit name bit symbol function (clock synchronous serial i/o mode) function (uart mode) set to 0 b7 b6 b5 b4 b3 b2 b1 b0 uarti special mode register (i=0 to 4) symbol address when reset uismr(i=0 to 4) 0367 16, 02e7 16, 0337 16, 0327 16, 02f7 16 00 16 rw lsyn abscs acse sss iicm bbs abc 0: normal mode 1: iic mode 0: update per bit 1: update per byte 0: stop condition detected 1: start condition detected 0: disabled 1: enabled set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" 0: ordinary 1: falling edge of rxdi 0: rising edge of transfer clock 1: underflow signal of timer ai (note 2) bit name bit symbol function (clock synchronous serial i/o mode) function (uart mode) iic mode select bit bus busy flag note 1: nothing but "0" may be written. note 2: uart0: timer a3 underflow signal, uart1: timer a4 underflow signal, uart2: timer a0 underflow signal, uart3: timer a3 underflow signal, uart4: timer a4 underflow signal. note 3: when this bit and bit 7 of uarti transmit/receive control register 1 are set, clock synchronizing function is used. auto clear function select bit of transmit enable bit scll sync output enable bit arbitration lost detecting flag control bit bus collision detect sampling clock select bit transmit start condition select bit 0: no auto clear function 1: auto clear at occurrence of bus (note 1) sclkdiv clock divide set bit 0: divided-by-2 1: no divided (note 3) b7 b6 b5 b4 b3 b2 b1 b0 figure 1.17.5. serial i/o-related registers (4)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer serial i/o 174 uarti special mode register 2 (i=0 to 4) symbol address when reset uismr2(i=0 to 4) 0366 16, 02e6 16, 0336 16, 0326 16, 02f6 16 00 16 rw als stc swc2 sdhi iicm2 swc csc clock synchronous bit iic mode select bit 2 scl wait output bit sda output stop bit uarti initialize bit scl wait output bit 2 sda output inhibit bit 0: disabled 1: enabled 0: disabled 1: enabled 0: disabled 1: enabled 0: disabled 1: enabled 0: uarti clock 1: 0 output 0: disabled 1: enabled (high impedance) bit name bit symbol function 0: nack/ack interrupt (dma source - ack) transfer to receive buffer at the rising edge of last bit of receive clock receive interrupt occurs at the rising edge of last bit of receive clock 1: uart transfer/receive interrupt (dma source - uart receive) transfer to receive buffer at the falling edge of last bit of receive clock receive interrupt occurs at the falling edge of last bit of receive clock su1him clock divide synchronizing enable bit 0: synchronous disabled 1: synchronous enabled b7 b6 b5 b4 b3 b2 b1 b0 figure 1.17.6. serial i/o-related registers (5)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer serial i/o 175 uarti special mode register 3 (i=0 to 4) symbol address when reset uismr3(i=0 to 4) 0365 16, 02e5 16, 0335 16, 0325 16, 02f5 16 00 16 rw nodc err dl0 dl1 sse dinc ckph dl2 (note 4) ss port function enable bit clock phase set bit serial input port set bit clock output select bit fault error flag sdai(txdi) digital delay time set bit (note 1) 0: ss function disabled 1: ss function enabled 0: without clock delay 1: with clock delay 0: select txdi and rxdi (master mode) 0: select stxdi and srxdi (slave mode) 0: clki is cmos output 1: clki is n-channel open drain output 0: without fault error 1: with fault error 000 :without delay 001 :2-cycle of brg count source 010 :3-cycle of brg count source 011 :4-cycle of brg count source 100 :5-cycle of brg count source 101 :6-cycle of brg count source 110 :7-cycle of brg count source 111 :8-cycle of brg count source b7 b6 b5 (note 2) (note 3) (note 5,6) bit name bit symbol function note 1: set ss function after setting cts/rts disable bit (bit 4 of uarti transfer/receive control register 0) to "1". note 2: set clki and txdi both for output using the clki and txdi function select register a. set the rxdi function select register a for input/output port and the port direction register to "0". note 3: set stxdi for output using the stxdi function select registers a and b. set the clki and srxdi function select register a for input/output port and the port direction register to "0". note 4: nothing but "0" may be written. note 5: these bits are used for sdai (txdi) output digital delay when using uarti for iic interface. otherwise, must set to "000". note 6: when external clock is selected, delay is increased approximately 100ns. b7 b6 b5 b4 b3 b2 b1 b0 figure 1.17.7. serial i/o-related registers (6)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer serial i/o 176 uarti special mode register 4 (i=0 to 4) symbol address when reset uismr4(i=0 to 4) 0364 16, 02e4 16, 0334 16, 0324 16, 02f4 16 00 16 rw start condition generate bit restart condition generate bit stop condition generate bit scl, sda output select bit ack data bit ack data output enable bit (note) 0: clear 1: start 0: clear 1: start 0: clear 1: start 0: ordinal block 1: start/stop condition generate block 0: ack 1: nack bit name bit symbol function note :when start condition is generated, these bits automatically become "0". scl wait output bit 3 scl output stop enable bit 0: scl "l" hold disabled 1: scl "l" hold enabled 0: disabled 1: enabled 0: si/o data output 1: ackd output (note) (note) stspsel ackd ackc sclhi stareq stpreq rstareq swc9 b7 b6 b5 b4 b3 b2 b1 b0 external interrupt request cause select register bit name function bit symbol w r symbol address when reset ifsr 031f 16 00 16 ifsr0 b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a aa aa a a int0 interrupt polarity select bit (note) 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges int1 interrupt polarity select bit (note) int2 interrupt polarity select bit (note) int3 interrupt polarity select bit (note) int4 interrupt polarity select bit (note) int5 interrupt polarity select bit (note) 0 : one edge 1 : both edges ifsr1 ifsr2 ifsr3 ifsr4 ifsr5 a a a a a a a a a a a a a a a a note :when level sense is selected, set this bit to "0". when both edges are selected, set the corresponding polarity switching bit of int interrupt control register to "0" (falling edge). 0 : uart3 bus collision /start,stop detect/false error detect 1 : uart0 bus collision /start,stop detect/false error detect uart0/3 interrupt cause select bit uart1/4 interrupt cause select bit ifsr6 ifsr7 a a a a 0 : uart4 bus collision /start,stop detect/false error detect 1 : uart1 bus collision /start,stop detect/false error detect figure 1.17.8. serial i/o-related registers (7)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 177 (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. tables 1.18.1 and 1.18.2 list the specifications of the clock synchronous serial i/o mode. table 1.18.1. specifications of clock synchronous serial i/o mode (1/2) item specification transfer data format ? transfer data length: 8 bits transfer clock ? when internal clock is selected (bit 3 at addresses 0368 16 , 02e8 16 , 0338 16 , 0328 16 , 02f8 16 = 0 ) : fi/ 2(m+1) (note 1) fi = f 1 , f 8 , f 2n (note 2) _ clk is selected by the corresponding peripheral function select register a, b and c. ? when external clock is selected (bit 3 at addresses 0368 16 , 02e8 16 , 0338 16 , 0328 16 , 02f8 16 = 1 ) : input from clki pin _ set the corresponding function select register a to i/o port transmission/reception control _______ _______ _______ _______ ? cts function/rts function/cts, rts function chosen to be invalid transmission start condition ? to start transmission, the following requirements must be met: _ transmit enable bit (bit 0 at addresses 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) = 0 _______ _______ _ when cts function selected, cts input level = l _ txd output is selected by the corresponding peripheral function select register a, b and c. ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ) = 0 : clki input level = h _ clki polarity select bit (bit 6 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ) = 1 : clki input level = l reception start condition ? to start reception, the following requirements must be met: _ receive enable bit (bit 2 at addresses 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) = 1 _ transmit enable bit (bit 0 at addresses 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) = 0 ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ) = 0 : clki input level = h _ clki polarity select bit (bit 6 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ) = 1 : clki input level = l ? when transmitting _ transmit interrupt cause select bit (bit 4 at address 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) = 0 : interrupts requested when data transfer from uarti trans- fer buffer register to uarti transmit register is completed _ transmit interrupt cause select bit (bit 4 at address 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) = 1 : interrupts requested when data transmission from uarti transfer register is completed ? when receiving _ interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed interrupt request generation timing note 1: m denotes the value 00 16 to ff 16 that is set to the uart bit rate generator.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 178 pin name function method of selection txdi (p6 3 , p6 7 , p7 0 , p9 2 , p9 6 ) serial data output (note 1) serial data input (note 2) transfer clock output (note 1) transfer clock input (note 2) programmable i/o port (note 2) (outputs dummy data when performing reception only) rxdi (p6 2 , p6 6 , p7 1 , p9 1 , p9 7 ) clki (p6 1 , p6 5 , p7 2 , p9 0 , p9 5 ) internal/external clock select bit (bit 3 at addresses 0368 16 , 02e8 16 , 0338 16 , 0328 16 , 02f8 16 ) = 0 internal/external clock select bit (bit 3 at addresses 0368 16 , 02e8 16 , 0338 16 , 0328 16 , 02f8 16 ) = 1 port p6 1 , p6 5 , p7 2 , p9 0 and p9 5 direction register (bits 1 and 5 at address 03c2 16 , bit 2 at address 03c3 16 , bit 0 and 5 at address 03c7 16 ) = 0 port p6 2 , p6 6 , p7 1 , p9 1 and p9 7 direction register (bits 2 and 6 at address 03c2 16 , bit 1 at address 03c3 16 , bit 1 and 7 at address 03c7 16 )= 0 (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ) = 0 cts/rts function select bit (bit 2 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ) = 0 port p6 0 , p6 4 , p7 3 , p9 3 and p9 4 direction register (bits 0 and 4 at address 03c2 16 , bit 3 at address 03c3 16 , bits 3 and 4 at address 03c7 16 ) = 0 cts/rts disable bit (bit 4 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16) = 0 cts/rts function select bit (bit 2 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ) = 1 cts/rts disable bit (bit 4 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ) = 1 cts input (note 2) rts output (note 1) ctsi/rtsi (p6 0 , p6 4 , p7 3 , p9 3 , p9 4 ) item specification error detection ? overrun error (note) this error occurs when the next data is started to receive and 6.5 transfer clock is elapsed before uarti receive buffer register are read out. select function ? clk polarity selection whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected ? lsb first/msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected ? continuous receive mode selection reception is enabled simultaneously by a read from the receive buffer register ? reversing serial data logic whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. ? txd, rxd i/o polarity reverse this function is reversing txd port output and rxd port input. all i/o data level is reversed. note : if an overrun error occurs, the uarti receive buffer will have the next data written in. table 1.18.3 lists the functions of the input/output pins during clock synchronous serial i/o mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h . (if the n-channel open drain is selected, this pin is in floating state.) table 1.18.3. input/output pin functions in clock synchronous serial i/o mode ________ note 1: select txd output, clk output and rts output by the corresponding function select registers a, b and c. note 2: select i/o port by the corresponding function select register a. table 1.18.2. specifications of clock synchronous serial i/o mode (2/2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 179 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk stopped pulsing because transfer enable bit = 0 data is set in uarti transmit buffer register tc = tclk = 2(m + 1) / fi fi: frequency of brgi count source (f 1 , f 8 , f 2n ) m: value set to brgi transfer clock transmit enable bit (te) transmit buffer empty flag (tl) clki txdi transmit register empty flag (txept) h l 0 1 0 1 0 1 ctsi the above timing applies to the following settings: ? internal clock is selected. ? cts function is selected. ? clk polarity select bit = 0 . ? transmit interrupt cause select bit = 0 . transmit interrupt request bit (ir) 0 1 stopped pulsing because cts = h transferred from uarti transmit buffer register to uarti transmit register shown in ( ) are bit symbols. cleared to 0 when interrupt request is accepted, or cleared by software dummy data is set in uarti transmit buffer register transmit enable bit (te) transmit buffer empty flag (tl) clki rxdi receive complete flag (rl) rtsi h l 0 1 0 1 0 1 receive enable bit (re) 0 1 receive data is taken in transferred from uarti transmit buffer register to uarti transmit register read out from uarti receive buffer register the above timing applies to the following settings: ? external clock is selected. ? rts function is selected. ? clk polarity select bit = 0 . f ext : frequency of external clock transferred from uarti receive register to uarti receive buffer register receive interrupt request bit (ir) 0 1 shown in ( ) are bit symbols. the following conditions are met when the clki input before data reception = h ? transmit enable bit 1 ? receive enable bit 1 ? dummy data write to uarti transmit buffer register cleared to 0 when interrupt request is accepted, or cleared by software 1 / f ext d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 over run error flag(oer) d 0 1 ? example of transmit timing (when internal clock is selected) ? example of receive timing (when external clock is selected) figure 1.18.1. typical transmit/receive timings in clock synchronous serial i/o mode
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 180 ? when clk polarity select bit = 1 note 2: the clk pin level when not transferring data is l . d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i ? when clk polarity select bit = 0 note 1: the clk pin level when not transferring data is h . d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i lsb first ? when transfer format select bit = 0 d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i ? when transfer format select bit = 1 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d i r x d i clk i msb first note: this applies when the clk polarity select bit = 0 . (a) polarity select function as shown in figure 1.18.2, the clk polarity select bit (bit 6 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ) allows selection of the polarity of the transfer clock. figure 1.18.2. polarity of transfer clock (b) lsb first/msb first select function as shown in figure 1.18.3, when the transfer format select bit (bit 7 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ) = 0 , the transfer format is lsb first ; when the bit = 1 , the transfer format is msb first . figure 1.18.3. transfer format
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 181 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txd i (no reverse) txd i (reverse) h l h l h l ?when lsb first (c) continuous receive mode if the continuous receive mode enable bit (bit 5 at address 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) is set to 1, the unit is placed in continuous receive mode. in this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data back to the transmit buffer register again. (d) serial data logic switch function when the data logic select bit (bit6 at address 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) = 1, and writing to transmit buffer register or reading from receive buffer register, data is reversed. figure 1.18.4 shows the timing example of serial data logic switch. figure 1.18.4. timing for switching serial data logic
clock asynchronous serial i/o (uart) mode under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 182 item specification transfer data format ? character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected ? start bit: 1 bit ? parity bit: odd, even, or nothing as selected ? stop bit: 1 bit or 2 bits as selected transfer clock ? when internal clock is selected (bit 3 at addresses 0368 16 , 02e8 16 , 0338 16 , 0328 16 , 02f8 16 = 0 ) : fi/16(m+1) (note 1) fi = f 1 , f 8 , f 2n ? when external clock is selected (bit 3 at addresses 0368 16 , 02e8 16 , 0338 16 , 0328 16 , 02f8 16 = 1 ) : f ext /16(m+1) (note 1, 2) transmission/reception control _______ _______ _______ _______ ? cts function, rts function, cts/rts function chosen to be invalid transmission start condition ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 at addresses 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) = 1 - transmit buffer empty flag (bit 1 at addresses 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) = 0 _______ _______ - when cts function selected, cts input level = l - txd output is selected by the corresponding peripheral function select register a, b and c. reception start condition ? to start reception, the following requirements must be met: - receive enable bit (bit 2 at addresses 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) = 1 - start bit detection interrupt request ? when transmitting generation timing - transmit interrupt cause select bits (bit 4 at address 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) = 0 : interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed - transmit interrupt cause select bits (bit 4 at address 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) = 1 : interrupts requested when data transmission from uarti transfer register is completed ? when receiving - interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection ? overrun error (note 3) this error occurs when the next data is started to receive and 6.5 transfer clock is elapsed before uarti receive buffer register are read out. (2) clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. tables 1.19.1 and 1.19.2 list the specifications of the uart mode. figure 1.19.1 shows the uarti transmit/receive mode register. table 1.19.1. specifications of uart mode (1/2) note 1: m denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: f ext is input from the clki pin. note 3: if an overrun error occurs, the uarti receive buffer will be over written with the next data.
clock asynchronous serial i/o (uart) mode under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 183 pin name function method of selection serial data output (note 1) serial data input (note 2) programmable i/o port (note 2) transfer clock input (note 2) programmable i/o port internal/external clock select bit (bit 3 at addresses 0368 16 , 02e8 16 , 0338 16 , 0328 16 , 02f8 16 ) = 0 internal/external clock select bit (bit 3 at addresses 0368 16 , 02e8 16 , 0338 16 , 0328 16 , 02f8 16 ) = 1 port p6 1 , p6 5 , p7 2 , p9 0 and p9 5 direction register (bits 1 and 5 at address 03c2 16 , bit 2 at address 03c3 16 , bits 0 and 5 at address 03c7 16 ) = 0 port p6 2 , p6 6 , p7 1 , p9 1 and p9 7 direction register (bits 2 and 6 at address 03c2 16 , bit 1 at address 03c3 16 , bit 1 and 7 at address 03c7 16 )= 0 (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ) = 0 cts/rts function select bit (bit 2 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ) = 0 port p6 0 , p6 4 , p7 3 , p9 3 and p9 4 direction register (bits 0 and 4 at address 03c2 16 , bit 3 at address 03c3 16 , bits 3 and 4 at address 03c7 16 ) = 0 cts input (note 2) rts output txdi (p6 3 , p6 7 , p7 0 , p9 2 , p9 6 ) rxdi (p6 2 , p6 6 , p7 1 , p9 1 , p9 7 ) clki (p6 1 , p6 5 , p7 2 , p9 0 , p9 5 ) ctsi/rtsi (p6 0 , p6 4 , p7 3 , p9 3 , p9 4 ) cts/rts disable bit (bit 4 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16) = 0 cts/rts function select bit (bit 2 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ) = 1 cts/rts disable bit (bit 4 at addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ) = 1 (note 1) (note 2) table 1.19.2. specifications of uart mode (2/2) item specification error detection ? framing error this error occurs when the number of stop bits set is not detected ? parity error if parity is enabled this error occurs when, the number of 1 s in parity and character bits does not match the number of 1 s set ? error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encoun- tered select function ? serial data logic switch this function reveres the logic value of transferring data. start bit, parity bit and stop bit are not reversed. ? txd, rxd i/o polarity switch this function reveres the txd port output and rxd port input. all i/o data level is reversed. table 1.19.3 lists the functions of the input/output pins in uart mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h . (if the n- channel open drain is selected, this pin is in floating state.) table 1.19.3. input/output pin functions in uart mode ________ note 1: select txd output, clk output and rts output by the corresponding function select registers a, b and c. note 2: select i/o port by the corresponding function select register a.
clock asynchronous serial i/o (uart) mode under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 184 transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) start bit parity bit txdi ctsi the above timing applies to the following settings : ? parity is enabled. ? one stop bit. ? cts function is selected. ? transmit interrupt cause select bit = 1 . 1 0 1 l h 0 1 tc = 16 (m + 1) / fi or 16 (m + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 2n ) f ext : frequency of brgi count source (external clock) m : value set to brgi transmit interrupt request bit (ir) 0 1 cleared to 0 when interrupt request is accepted, or cleared by software transmit enable bit(te) transmit buffer empty flag(ti) txdi transmit register empty flag (txept) 0 1 0 1 0 1 the above timing applies to the following settings : ? parity is disabled. ? two stop bits. ? cts function is disabled. ? transmit interrupt cause select bit = 0 . transfer clock tc tc = 16 (m + 1) / fi or 16 (m + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 2n ) f ext : frequency of brgi count source (external clock) m : value set to brgi transmit interrupt request bit (ir) 0 1 shown in ( ) are bit symbols. shown in ( ) are bit symbols. tc transfer clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 sp st p sp d 0 d 1 st stopped pulsing because transmit enable bit = 0 stop bit transferred from uarti transmit buffer register to uarti transmit register start bit the transfer clock stops momentarily as cts is h when the stop bit is checked. the transfer clock starts as the transfer starts immediately cts changes to l . data is set in uarti transmit buffer register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp transferred from uarti transmit buffer register to uarti transmit register stop bit stop bit data is set in uarti transmit buffer register. 0 sp cleared to 0 when interrupt request is accepted, or cleared by software ? example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) ? example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) figure 1.19.1. typical transmit timings in uart mode
clock asynchronous serial i/o (uart) mode under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 185 st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st sp st d3 d4 d5 d6 d7 p d0 d1 d2 transfer clock txd i (no reverse) txd i (reverse) h l h l h l ? when lsb first, parity enabled, one stop bit figure 1.19.3. timing for switching serial data logic ? example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) d 0 start bit sampled l receive data taken in brgi count source receive enable bit rxdi transfer clock receive complete flag rtsi stop bit 1 0 0 1 h l the above timing applies to the following settings : ? parity is disabled. ? one stop bit. ? rts function is selected. receive interrupt request bit 0 1 transferred from uarti receive register to uarti receive buffer register reception triggered when transfer clock is generated by falling edge of start bit d 7 d 1 cleared to 0 when interrupt request is accepted, or cleared by software becomes l by reading the receive buffer figure 1.19.2. typical receive timing in uart mode (a) function for switching serial data logic when the data logic select bit (bit 6 of address 036d 16 , 02ed 16 , 033d 16 , 032d 16 , 02fd 16 ) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. figure 1.19.3 shows the example of timing for switching serial data logic.
clock asynchronous serial i/o (uart) mode under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 186 st : start bit sp : stop bit st st sp sp transfer clock txd i rxd i bus collision detection interrupt request signal h l h l h l 1 0 bus collision detection interrupt request bit 1 0 (b) txd, rxd i/o polarity reverse function this function is to reverse txd pin output and rxd pin input. the level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. set this function to 0 (not to reverse) for normal use. (c) bus collision detection function this function is to sample the output level of the txd pin and the input level of the rxd pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. figure 1.19.4 shows the example of detection timing of a bus collision (in uart mode). uart0 and uart3 are allocated to software interrupt number 40. uart1 and uart4 are allocated to software interrupt number 41. when selecting uart 0, 3, 1 or 4 bus collision detect function, bit 6 or 7 of external interrupt cause select register (address 031f 16 ) must be set. figure 1.19.4. detection timing of a bus collision (in uart mode)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer uarti special mode register 187 uarti special mode register uarti (i=0 to 4) operate the iic bus interface (simple iic bus) using the uarti special mode register (addresses 0367 16 , 02e7 16 , 0337 16 , 0327 16 and 02f7 16 ) and uarti special mode register 2 (addresses 0366 16 , 02e6 16 , 0336 16 , 0326 16 and 02f6 16 ). uarti add special functions using uarti special mode resister 3 (addresses 0365 16 , 02e5 16 , 0355 16 , 0325 16 and 02f5 16 ). (1) iic bus interface mode the i 2 c bus interface mode is provided with uarti. table 1.21.1 shows the construction of the uarti special mode register and uarti special mode regis- ter 2. when the i 2 c mode select bit (bit 0 in addresses 0367 16 , 02e7 16 , 0337 16 , 0327 16 and 02f7 16 ) is set to 1 , the i 2 c bus (simple i 2 c bus) interface circuit is enabled. to use the i 2 c bus, set the scli and the sdai of both master and slave to output with the function select register. also, set the data output select bit (bit 5 in address 036c 16 , 02ec 16 , 033c 16 , 032c 16 and 02fc 16 ) to n-channel open drain output. table 1.21.1 shows the relationship of the iic mode select bit to control. to use the chip in the clock synchronized serial i/o mode or uart mode, always set this bit to 0 . function normal mode (iicm=0) i 2 c mode (iicm=1) factor of interrupt number 17, 19, 33, 35, 37 uarti transmission no acknowledgment detection (nack) factor of interrupt number 18, 20, 34, 36, 38 uarti reception start condition detection or stop condition detection uarti transmission output delay not delayed delayed p6 3 , p6 7 , p7 0 , p9 2 , p9 6 at the time when uarti is in use txd i (output) sdai (input/output) p6 2 , p6 6 , p7 1 , p9 1 , p9 7 at the time when uarti is in use rxd i (input) scli (input/output) p6 1 , p6 5 , p7 2 , p9 0 , p9 5 at the time when uarti is in use clki p6 1 , p6 5 , p7 2 , p9 0 , p9 5 dma factor at the time uarti reception acknowledgment detection (ack) noise filter width 15ns 50ns reading p6 2 , p6 6 , p7 1 , p9 1 , p9 7 reading the terminal when 0 is assigned to the direction register reading the terminal regardless of the value of the direction register 1 2 3 4 5 6 7 8 9 note 1: make the settings given below when i 2 c mode is used. set 0 1 0 in bits 2, 1, 0 of the uarti transmission/reception mode register. disable the rts/cts function. choose the msb first function. note 2: follow the steps given below to switch from one factor to another. 1. disable the interrupt of the corresponding number. 2. switch from a factor to another. 3. reset the interrupt request flag of the corresponding number. 4. set an interrupt level of the corresponding number. note 3: set an initial value of sda transmission output when iic mode (iic mode select bit = "1") is valid and serial i/o is in valid. factor of interrupt number 39 to 41 bus collision detection acknowledgment detection (ack) 10 initial value of uarti output h level (when 0 is assigned to the clk polarity select bit) the value set in latch p6 3 , p6 7 , p7 0 , p9 2 , p9 6 when the port is selected 11 (note 2) (note 2) (note 2) (note 1) (note 3) (note 3) table 1.21.1. features in i 2 c mode
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer uarti special mode register 188 selector i/o timer delay uarti reception register external clock arbitration start condition detection stop condition detection falling edge detection uarti transmission/ nack interrupt request uarti reception/ack interrupt request dmai request 9th pulse port reading * with iicm set to 1, the port terminal is to be readable even if 1 is assigned to p7 1 of the direction register. l-synchronous output enabling bit bus collision/start, stop condition detection interrupt request bus collision detection noize filter i/0 noize filter txdi/sda rxdi/scl clk control internal clock uarti serector uarti i/0 timer clki data register d t q d t q d t q nack ack uarti uarti r iicm=1 iicm=0 iicm=1 iicm=0 iicm=1 and iicm2=0 iicm=0 iicm=1 iicm=1 iicm=0 s r q bus busy iicm=1 iicm=0 als r s swc falling edge of 9th pulse iicm=1 and iicm2=0 iicm=0 or iicm2=1 iicm=0 or iicm2=1 swc2 sdhi to dmai to dmai selector transmission register uarti noize filter figure 1.21.1 is a block diagram of the iic bus interface. the control bits of the iic bus interface is explained as follow: uarti special mode register (uismr:addresses 0367 16 , 02e7 16 , 0337 16 , 0327 16 , 02f7 16 ) bit 0 is the iic mode select bit. when set to 1 , ports operate respectively as the sdai data transmis- sion-reception pin, scli clock i/o pin and port. a delay circuit is added to sdai transmission output, therefore after scli is sufficiently l level, sdai output changes. port (scli) is designed to read pin level regardless of the content of the port direction register. sdai transmission output is initially set to port in this mode. furthermore, interrupt factors for the bus collision detection interrupt, uarti trans- mission interrupt and uarti reception interrupt change respectively to the start/stop condition detec- tion interrupts, acknowledge non-detection interrupt and acknowledge detection interrupt. figure 1.21.1. functional block diagram for i 2 c mode
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer uarti special mode register 189 the start condition detection interrupt is generated when the falling edge at the sdai pin is detected while the scli pin is in the h state. the stop condition detection interrupt is generated when the rising edge at the sdai pin is detected while the scli pin is in the h state. the acknowledge non-detection interrupt is generated when the h level at the sdai pin is detected at the 9th rise of the transmission clock. the acknowledge detection interrupt is generated when the l level at the sdai pin is detected at the 9th rise of the transmission clock. also, dma transfer can be started when the acknowledge is de- tected and uarti transmission is selected as the dmai request factor. bit 1 is the arbitration lost detection flag control bit (abc). arbitration detects a conflict between data transmitted at scli rise and data at the sdai pin. this detection flag is allocated to bit 11 in uarti transmission buffer register (addresses 036f 16 , 02ef 16 , 033f 16 , 032f 16 , 02ff 16 ). it is set to 1 when a conflict is detected. with the arbitration lost detection flag control bit, it can be selected to update the flag in units of bits or bytes. when this bit is set to 1 , update is set to units of byte. if a conflict is then detected, the arbitration lost detection flag control bit will be set to 1 at the 9th rise of the clock. when updating in units of byte, always clear ( 0 interrupt) the arbitration lost detection flag control bit after the 1st byte has been acknowledged but before the next byte starts transmitting. bit 2 is the bus busy flag (bbs). it is set to 1 when the start condition is detected, and reset to 0 when the stop condition is detected. bit 3 is the scli l synchronization output enable bit (lsyn). when this bit is set to 1 , the port data register is set to 0 in sync with the l level at the scli pin. bit 4 is the bus collision detection sampling clock select bit (abscs). the bus collision detection interrupt is generated when rxdi and txdi level do not conflict with one another. when this bit is 0 , a conflict is detected in sync with the rise of the transfer clock. when this bit is 1 , detection is made when timer ai (timer a3 with uart0, timer a4 with uart1, timer a0 with uart2, timer a3 with uart3 and timer a4 with uart4) underflows. operation is shown in figure 1.21.2. bit 5 is the transmission enable bit automatic clear select bit (acse). by setting this bit to 1 , the transmission bit is automatically reset to 0 when the bus collision detection interrupt factor bit is 1 (when a conflict is detected). bit 6 is the transmission start condition select bit (sss). by setting this bit to 1 , txdi transmission starts in sync with the rise at the rxdi pin.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer uarti special mode register 190 1. bus collision detect sampling clock select bit (bit 4 of the uarti special mode register) 0: rising edges of the transfer clock clki timer ai 1: timer ai underflow 2. auto clear function select bit of transmit enable bit (bit 5 of the uarti special mode register) clki txdi/rxdi bus collision detect interrupt request bit transmit enable bit 3. transmit start condition select bit (bit 6 of the uarti special mode register) clki txdi enabling transmission clki txdi rxdi with "1: falling edge of rxd i " selected 0: in normal state txdi/rxdi figure 1.21.2. some other functions added
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer uarti special mode register 191 uarti special mode register 2 (uismr2:addresses 0366 16 , 02e6 16 , 0336 16 , 0326 16 , 02f6 16 ) bit 0 is the iic mode select bit 2 (iicm2). table 1.21.2 gives control changes by bit when the iic mode select bit is 1 . start and stop condition detection timing characteristics are shown in figure 1.21.4. always set bit 7 (start/stop condition control bit) to 1 . bit 1 is the clock synchronizing bit (csc). when this bit is set to 1 , and the rising edge is detected at pin scli while the internal scl is high level, the internal scl is changed to low level, the baud rate generator value is reloaded and the low sector count starts. also, while the scli pin is low level, and the internal scl changes from low level to high, baud rate generator stops counting. if the scli pin is h level, counting restarts. because of this function, the uarti transmission-reception clock takes the and condition for the internal scl and scli pin signals. this function operates from the clock half period before the 1st rise of the uarti clock to the 9th rise. to use this function, select the internal clock as the transfer clock. bit 2 is the scl wait output bit (swc). when this bit is set to 1 , output from the scli pin is fixed to l level at the clock s 9th rise. when set to 0 , the low output lock is released. bit 3 is the sda output stop bit (als). when this bit is set to 1 , an arbitration lost is generated. if the arbitration lost detection flag is 1 , then the sdai pin simultaneously becomes high impedance. bit 4 is the uarti initialize bit (stc). while this bit is set to 1 , the following operations are performed when the start condition is detected. 1. the transmission shift register is initialized and the content of the transmission register is trans- mitted to the transmission shift register. as such, transmission starts with the 1st bit of the next input clock. however, the uarti output value remains the same as when the start condition was detected, without changing from when the clock is input to when the 1st bit of data is output. 2. the reception shift register is initialized and reception starts with the 1st bit of the next input clock. 3. the scl wait output bit is set to 1 . as such, the scli pin becomes low level at the rise of the 9th bit of the clock. when uart transmission-reception has started using this function, the content of the transmission buffer available flag does not change. also, to use this function, select an external clock as the transfer clock. bit 5 is scl wait output bit 2 (swc2). when this bit is set to 1 and serial i/o is selected, an low level can be forcefully output from the scli pin even during uart operation. when this bit is set to 0', the low output from the scli pin is canceled and the uarti clock is input and output. bit 6 is the sda output disable bit (sdhi). when this bit is set to 1 , the sdai pin is forced to high impedance. to overwrite this bit, do so at the rise of the uarti transfer clock. the arbitration lost detection flag may be set.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer uarti special mode register 192 iicm2 = 0 acknowledge not detect (nack) acknowledge detect (ack) acknowledge detect (ack) rising edge of the last bit of re- ceive clock rising edge of the last bit of re- ceive clock function interrupt no. 17, 19, 33, 35, 37 fac- tor interrupt no. 18, 20, 34, 36, 38 fac- tor dma factor data transfer timing from uart re- ceive shift register to receive buffer uart receive / ack interrupt re- quest generation timing iicm2 = 1 uarti transfer (rising edge of the last bit) uarti receive (falling edge of the last bit) uarti receive (falling edge of the last bit) rising edge of the last bit of re- ceive clock rising edge of the last bit of re- ceive clock set up time hold time scl sda (start condition) sda (stop condition) uarti special mode register 3 (uismr3:addresses 0365 16 , 02e5 16 , 0335 16 , 0325 16 , 02f5 16 ) bit 1 is clock phase set bit (ckph). when both the iic mode select bit (bit 0 of uarti special mode select register) and the iic mode select bit 2 (bit 0 of uismr2 register) are "1", functions changed by these bits are shown in table 1.21.3 and figure 1.21.4. bits 5 to 7 are sdai digital delay setting bits (dl0 to dl2). by setting these bits, it is possible to turn the sdai delay off or set the brg count source delay to 2 to 8 cycles. table 1.21.3. functions changed by clock phase set bits ckph = 0, iicm = 1, iicm2 = 1 initial value = h, last value = l rising edge of 9th bit falling edge of 9th bit function scl initial and last value transfer interrupt factor data transfer times from uart re- ceive shift register to receive buffer register ckph = 1, iicm = 1, iicm2 = 1 initial value = l, last value = l falling edge of 10th bit two times :falling edge of 9th bit and rising edge of 9th bit table 1.21.2. functions changed by i 2 c mode select bit 2 figure 1.21.3. start/stop condition detect timing characteristics 3 to 6 cycles < set up time (note) 3 to 6 cycles < hold time (note) note : cycle number shows main clock input oscillation frequency f(x in ) cycle number.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer uarti special mode register 193 figure 1.21.4. functions changed by clock phase set bits uarti special mode register 4 (uismr4:addresses 0364 16 , 02e4 16 , 0334 16 , 0324 16 , 02f4 16 ) bit 0 is the start condition generate bit (stareq). when the scl, sda output select bit (bit 3 of uismr4 register) is "1" and this bit is "1", then the start condition is generated. bit 1 is the restart condition generate bit (rstareq). when the scl, sda output select bit (bit 3 of uismr4 register) is "1" and this bit is "1", then the restart condition is generated. bit 2 is the stop condition generate bit (stpreq). when the scl, sda output select bit (bit 3 of uismr4 register) is "1" and this bit is "1", then the stop condition is generated. bit 3 is scl, sda output select bit (stspsel). functions changed by these bits are shown in table 1.21.4 and figure 1.21.5. table 1.21.4. functions changed by scl, sda output select bit stspsel = 0 output of si/o control circuit start/stop condition detection function scl, sda output star/stop condition interrupt factor stspsel = 1 output of start/stop condition control circuit completion of start/stop condition generation ? ckph= "1" (iicm=1, iicm2=1) ? ckph= "0" (iicm=1, iicm2=1) (internal clock, transfer data 9 bits long and msb first selected.) d 6 d 5 d 4 d 3 d 2 d 1 d 8 d7 sda scl d 0 receive interrupt transmit interrupt transfer to receive buffer (internal clock, transfer data 9 bits long and msb first selected.) d 6 d 5 d 4 d 3 d 2 d 1 d 8 d7 sda scl d 0 receive interrupt transmit interrup t transfer to receive buffer
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer uarti special mode register 194 figure 1.21.5 functions changed by scl, sda output select bit bit 4 is ack data bit (ackd). when the scl, sda output select bit (bit 3 of uismr4 register) is "0" and the ack data output enable bit (bit 5 of uismr4 register) is "1", then the content of ack data bit is output to sdai pin. bit 5 is ack data output enable bit (ackc). when the scl, sda output select bit (bit 3 of uismr4 register) is "0" and this bit is "1", then the content of ack data bit is output to sdai pin. bit 6 is scl output stop bit (sclhi). when this bit is "1", scli output is stopped at stop condition detection. (hi-impedance status). bit 7 is scl wait output bit 3 (swc9). when this bit is "1", scli output is fixed to "l" at falling edge of 10th bit of clock. when this bit is "0", scli output fixed to "l" is released. sda start condition detection interrupt stop condition detection interrupt ? when slave mode (ckdir=0, stspsel=0) scl sda start condition detection interrupt stop condition detection interrupt ? when master mode (ckdir=1, stspsel=1) scl stareq=1 stpreq=1 stspsel=0 stspsel=1 stspsel=0 stspsel=0 stspsel=1
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer uarti special mode register 195 p1 3 p1 2 ic1 p9 3( ss 3 ) p9 2( txd 3 ) p9 0( clk 3 ) p9 1( rxd 3 ) ic2 p9 3( ss 3 ) p9 2( srxd 3 ) p9 0( clk 3 ) p9 1( stxd 3 ) ic3 p9 3( ss 3 ) p9 2( srxd 3 ) p9 0( clk 3 ) p9 1( stxd 3 ) m16c/80 (m) m16c/80 (s) m16c/80 (s) m :master s :slave (2) serial interface special function _____ uarti can control communications on the serial bus using the ssi input pins (figure 1.21.6). the master outputting the transfer clock transfers data to the slave inputting the transfer clock. in this case, in order to _____ prevent a data collision on the bus, the master floats the output pin of other slaves/masters using the ssi input pins. _____ ssi input pins function between the master and slave are as follows. figure 1.21.6. serial bus communication control example using the ss input pins < slave mode (stxdi and srxdi are selected, dinc = 1) > _____ when an h level signal is input to an ssi input pin, the stxdi and srxdi pins both become high _____ impedance, hence the clock input is ignored. when an "l" level signal is input to an ssi input pin, the clock input becomes effective and serial communications are enabled. < master mode (txdi and rxdi are selected, dinc = 0) > _____ _____ the ssi input pins are used with a multiple master system. when an ssi input pin is h level, transmis- _____ sion has priority and serial communications are enabled. when an l signal is input to an ssi input pin, another master exists, and the txdi, rxdi and clki pins all become high impedance. moreover, the trouble error interrupt request bit becomes 1 . communications do not stop even when a trouble error is generated during communications. to stop communications, set bits 0, 1 and 2 of the uarti trans- mission-reception mode register (addresses 0368 16 , 02e8 16 , 0338 16 , 0328 16 and 02f8 16 ) to 0 .
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer uarti special mode register 196 master ss input data output timing data input timing d 0 d 1 d 2 d 3 d 4 d 6 d 7 d 5 "h" "l" clock output (ckpol=0, ckph=0) "h" "l" clock output (ckpol=1, ckph=0) "h" "l" clock output (ckpol=0, ckph=1) "h" "l" clock output (ckpol=1, ckph=1) "h" "l" "h" "l" clock phase setting with bit 1 of uarti special mode register 3 (uismr3:addresses 0365 16 , 02e5 16 , 0335 16 , 0325 16 , 02f5 16 ) and bit 6 of uarti transmission-reception control register 0 (addresses 036c 16 , 02ec 16 , 033c 16 , 032c 16 , 02fc 16 ), four combinations of transfer clock phase and polarity can be selected. bit 6 of uarti transmission-reception control register 0 sets transfer clock polarity, whereas bit 1 of uismr3 register sets transfer clock phase. transfer clock phase and polarity must be the same between the master and slave involved in the transfer. < master (internal clock) (dinc = 0) > figure 1.21.7 shows the transmission and reception timing. < slave (external clock) (dinc = 1) > _____ ? with 0 for ckph bit (bit 1 of uismr3 register), when an ssi input pin is h level, output data is high _____ impedance. when an ssi input pin is l level, the serial transmission start condition is satisfied, though output is indeterminate. after that, serial transmission is synchronized with the clock. figure 1.21.8 shows the timing. _____ _____ ? with 1 for ckph bit, when an ssi input pin is h level, output data is high impedance. when an ssi input pin is l level, the first data is output. after that, serial transmission is synchronized with the clock.figure 1.21.9 shows the thing. figure 1.21.7. the transmission and reception timing in master mode (internal clock)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer uarti special mode register 197 high- inpedance ss input clock input (ckpol=0, ckph=0) clock input (ckpol=1, ckph=0) data output timing data input timing "h" "l" "h" "l" "h" "l" "h" "l" high- inpedance d 0 d 1 d 2 d 3 d 4 d 6 d 7 d 5 indeterminate note :uart2 output is an n-channel open drain and needs to be pulled-up externally. (note) high- inpedance ss input clock input (ckpol=0, ckph=0) clock input (ckpol=1, ckph=0) data output timing data input timing "h" "l" "h" "l" "h" "l" "h" "l" high- inpedance d 0 d 1 d 2 d 3 d 6 d 7 d 4 d 5 note :uart2 output is an n-channel open drain and needs to be pulled-up externally. (note) figure 1.21.8. the transmission and reception timing (ckph=0) in slave mode (external clock) figure 1.21.9. the transmission and reception timing (ckph=1) in slave mode (external clock)
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 198 can module the microcomputer incorporates full-can modules compliant with can (controller area network) 2.0b specification. these full-can modules are outlined below. table 1.22.1 outline of the can module item description protocol compliant with can 2.0b specification number of message slots 16 slots polarity 0: dominant 1: recessive acceptance filter global mask: 1 mask (for message slots 0 C 13) local mask: 2 masks (for message slots 14 and 15 each) baud rate 1 time quantum (tq) = (brp + 1) / cpu clock (note) (brp = baud rate prescaler set value) baud rate = 1 / (tq period x number of tq s in one bit) ---max. 1 mbps brp: 1-255 (0: inhibited) number of tq s in one bit = synchronization segment + propagation time segment + phase buffer segment 1 + phase buffer segment 2 synchronization segment : 1 tq (fixed) propagation time segment : 1 to 8 tq phase buffer segment 1 : 2 to 8 tq phase buffer segment 2 : 2 to 8 tq remote frame automatic the message slot that received a remote frame automatically transmits it. answering function timestamp function this timestamp function is based on a 16-bit counter. a count period can be derived from the can bus bit period (as the fundamental period) by dividing it by 1, 2, 3, or 4. basiccan mode the basiccan function is realized by using message slots 14 and 15. transmit abort function this function is used to cancel a transmit request. loopback function the data the can module itself transmitted is received. return from bus-off function forcibly placed into an error active state from a bus-off state. note: use a specification conforming resonator whose maximum permissible error of oscillation is not greater than 1.58%
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 199 message slot 0 control register control register expansion id register configuration register slot interrupt mask register error interrupt mask register baud rate prescaler sleep control register global mask register local mask register a local mask register b acceptance filter support register message slot buffer 0 time stamp register 16 bits timer status register transmit error count register receive error count register slot interrupt status register error interrupt status register interrupt request message box (slot 0 to 15) message slot 0 bclk acceptance filter can in can out can protocol controller ver 2.0b interrupt control circuit data bus slot buffer select register figure 1.22.1 can module blobk diagram can0 message slot buffer 0 and 1 can be selected by setting of slot buffer select register. figure 1.22.2 shows the message slot buffer and 16 bytes of message slots. figure 1.22.26 to 1.22.30 show related registers. figure 1.22.2. message slot buffer and message slots can0 message slot buffer 0 standard id0 can0 message slot buffer 0 standard id1 can0 message slot buffer 0 extended id0 can0 message slot buffer 0 extended id1 can0 message slot buffer 0 extended id2 can0 message slot buffer 0 data length code can0 message slot buffer 0 data 0 can0 message slot buffer 0 data 1 can0 message slot buffer 0 data 2 can0 message slot buffer 0 data 3 can0 message slot buffer 0 data 4 can0 message slot buffer 0 data 5 can0 message slot buffer 0 data 6 can0 message slot buffer 0 data 7 can0 message slot 15 time stamp low can0 message slot buffer 0 standard id0 can0 message slot buffer 0 standard id1 can0 message slot buffer 0 extended id0 can0 message slot buffer 0 extended id1 can0 message slot buffer 0 extended id2 can0 message slot buffer 0 data length code can0 message slot buffer 0 data 0 can0 message slot buffer 0 data 1 can0 message slot buffer 0 data 2 can0 message slot buffer 0 data 3 can0 message slot buffer 0 data 4 can0 message slot buffer 0 data 5 can0 message slot buffer 0 data 6 can0 message slot buffer 0 data 7 can0 message slot buffer 0 time stamp high can0 message slot buffer 1 time stamp low can0 message slot 0 to 15 can0 message slot buffer 0 (addresses 01e0 16 to 01ef 16 ) can0 message slot buffer 1 (addresses 01f0 16 to 01ff 16 ) can0 message slot buffer 0 standard id0 can0 message slot buffer 0 standard id1 can0 message slot buffer 0 extend id0 can0 message slot buffer 0 extend id1 can0 message slot buffer 0 extend id2 can0 message slot buffer 0 data length code can0 message slot buffer 0 data 0 can0 message slot buffer 0 data 1 can0 message slot buffer 0 data 2 can0 message slot buffer 0 data 3 can0 message slot buffer 0 data 4 can0 message slot buffer 0 data 5 can0 message slot buffer 0 data 6 can0 message slot buffer 0 data 7 can0 message slot buffer 0 time stamp high can0 message slot buffer 0 time stamp low can0 message slot 0 standard id0 can0 message slot 0 standard id1 can0 message slot 0 extend id0 can0 message slot 0 extend id1 can0 message slot 0 extend id2 can0 message slot 0 data length code can0 message slot 0 data 0 can0 message slot 0 data 1 can0 message slot 0 data 2 can0 message slot 0 data 3 can0 message slot 0 data 4 can0 message slot 0 data 5 can0 message slot 0 data 6 can0 message slot 0 data 7 can0 message slot 0 time stamp high can0 message slot 0 time stamp low
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 200 can0 control register 0 symbol address when reset (note 1) c0ctlr0 0201 16, 0200 16 xxxx 0000 xx01 0x01 2 rw note 1: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. note 2: only writing 1 is accepted. the bit is automatically cleared to 0 in hardware. reset 1 tspre0 tsreset ecreset can reset bit 1 time stamp counter reset bit error counter reset bit 0 : reset released 1 : reset requested reset 0 loopback basiccan can reset bit 0 loop back mode select bit basic can mode select bit 0 0: can bus bit clock is selected 0 1: division by 2 of can bus bit clock is selected 1 0: division by 3 of can bus bit clock is selected 1 1: division by 4 of can bus bit clock is selected b9 b8 0 : basic can mode function disabled 1 : basic can mode function enabled 0: loop back function disabled 1: loop back function enabled 0: reset released 1: reset requested tspre1 0 : count enabled 1 : count reset (set 0000 16 ) (note 2) 0 : normal operation mode 1 : error counter reset (note 2) time stamp prescaler select bit reserved bit must set to "0". bit name function bit symbol nothing is assigned. when write, set to "0". when read, their contents are indeterminate. nothing is assigned. when write, set to "0". when read, their contents are indeterminate. nothing is assigned. when write, set to "0". when read, its contents is indeterminate. b7 b0 b15 (b7) b8 (b0) 0 figure 1.22.3 can0 control register 0
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 201 1. can0 control register 0 bit 0: can reset bits 0 and 1 (reset0 and reset1) if the reset0 and reset1 bits both are set from 1 to 0, can communication is enabled after detecting 11 consecutive recessive bits. the can timestamp register starts counting at the same time com- munication is enabled. in no case will the can be reset unless transmission of all messages are completed. note 1: reset0 and reset1 bits must both be cleared to "0" or set to "1" simutnously. note 2: setting a new transmit request is inhibited before the can status register state_reset bit is set to 1 and the can module is reset after setting the reset0 and reset1 bits to 1. note 3: when the can module is reset by setting the reset0 and reset1 bits to 1, the can timestamp register (c0tsr), can transmit error counter (c0tec), and can receive error counter (c0rec) are initialized to 0. note 4: if reset0 and reset1 bits sre set to "1" during communication, the can out pin output goes "h" immediately after that. therefore, setting these bits to 1 while the can module is sending a frame may cause a can bus error. note 5: to can communication, function select register a1 (ps1), function select register a2 (ps2), function select register b1 (psl1), function select register b2 (psl2), function select register c (psc) and input function select register (ips) must be set. these registers must be set when can module is reset. bit 1: loopback mode select bit (loopback) setting the loopback bit to 1 enables loopback mode, so that if any receive slot whose id matches that of a frame the can module itself transmitted exists, the frame is received. note 1: ack is not returned for the transmit frame. note 2: do not set or reset the loopback bit while the can module is operating (can status register state_reset bit = 0). bit 3: basiccan mode select bit (basiccan) if this bit is set to 1, message slots 14 and 15 operate in basiccan mode. operation during basiccan mode in basiccan mode, message slots 14 and 15 are used with a dual-structured buffer. the received frames whose ids are found matching by acceptance filtering are stored in slots 14 and 15 alter- nately. when slot 14 is active (i.e., the next received frame is to be stored in slot 14), this acceptance filtering is accomplished using the id that is set in slot 14 and local mask a; when slot 15 is active, it is accomplished using the id that is set in slot 15 and local mask b. frame types of both data frame and remote frame can be received. when using basiccan mode, setting the ids of two slots and the mask registers the same way helps to reduce the possibility of causing an overrun error. procedure for entering basiccan mode make the following settings during initialization. (1) set the basiccan bit to 1. (2) set the ids of slots 14 and 15 and local mask registers a and b. (we recommend setting the same value) (3) set the frame format to be handled with slots 14 and 15 (standard or extended) in the can extended id register. (we recommend setting the same format)
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 202 (4) set the message slot control registers for slots 14 and 15 to receive data frames. note 1: do not set or reset the basiccan bit while the can module is operating (can status regis- ter state_reset bit = 0). note 2: slot 14 is the first slot to become active after clearing the reset0 bit. note 3: even during basiccan mode, slot 0 through slot 13 can be used in the same way as when operating normally. bit 8, 9: timestamp prescaler select bits (tspre0, 1) these bits select the count clock source for the timestamp counter. note 1: do not set or reset these tspre0, 1 bits while the can module is operating (can status register state_reset bit = 0). bit 10: timestamp counter reset bit (tsreset) setting this bit to 1 clears the value of the can timestamp register (c0tsr) to 0000 16 . this bit is automatically cleared after the can timestamp register (c0tsr) has its value cleared to 0000 16 . bit 11: error counter reset bit (ecreset) setting this bit to 1 clears the receive error counter register (c0rec) and transmit error counter register (c0tec), with the can module forcibly placed in an error active state. this bit is automati- cally cleared upon entering an error active state. note 1: when in an error active state, the can module becomes ready to communicate when it detects 11 consecutive recessive bits on the can bus.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 203 banksel can0 control register 1 symbol address when reset (note) c0ctlr1 0241 16 xx0000xx 2 rw can0 bank select bit 0 : message slot control register selected 1 : mask register selected note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. bit name function bit symbol reserved bit must set to "0". reserved bit must set to "0". nothing is assigned. when write, set to "0". when read, their contents are indeterminate. nothing is assigned. when write, set to "0". when read, their contents are indeterminate. b7 b0 0 0 0 figure 1.22.4. can0 control register 1 2. can0 control register 1 bit 3: can0 bank select bit (banksel) this bit selects between registers allocated to the addresses 0220 16 through 023f 16 . setting the banksel bit to 0 selects the can0 message slot control register. setting the banksel bit to 1 selects the can0 mask register.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 204 sleep can0 sleep control register symbol address when reset c0slpr 0242 16 xxxxxxx0 2 rw sleep mode control bit 0 : sleep mode on 1 : sleep mode off (note) note: after can sleep mode is canceled, set up the can configuration. while the can module is in sleep mode, no sfr registers for the can, except the sleep mode control register, can be accessed for read or write. bit name function bit symbol nothing is assigned. when write, set to "0". when read, their contents are indeterminate. b7 b0 figure 1.22.5. can0 sleep control register 3. can0 sleep control register bit 0: sleep mode control bit (sleep) the can module isn't supplied with a clock by setting the sleep bit to 0, and is shifted to sleep mode. the can module is supplied with a clock by setting the sleep bit to 1, and is released from sleep mode. note: sleep mode can be shifted to only after can is reset (state_reset bit = 1).
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 205 can0 status register symbol address when reset (note) c0str 0203 16, 0202 16 x000 0x01 0000 0000 2 rw 0 0 0 0 : slot 0 0 0 1 0 : slot 1 0 0 1 1 : slot 2 0 1 0 0 : slot 3 ? ? ? ? 1 1 0 1 : slot 13 1 1 1 0 : slot 14 1 1 1 1 : slot 15 b2 b3 b0 b1 note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. mbox0 trmsucc recsucc active slot determination bit trmstate recstate state_reset state_loopback state_basiccan state_buserror state_errpas state_busoff transmission-finished status reception-finished status transmission status reception status can reset status loop back status basic can status can bus error error passive status bus-off status 0: transmission not finished 1: transmission finished 0: reception not finished 1: reception finished 0: not transmitting 1: transmitting 0: not receiving 1: receiving 0: operating 1: reset 0: normal mode 1: loop back mode 0: normal mode 1: basic can mode 0: no error occurred 1: error occurred 0: not error passive state 1: error passive state 0: not bus-off state 1: bus-off state mbox1 mbox2 mbox3 bit name function bit symbol nothing is assigned. when write, set to "0". when read, its content is indeterminate. nothing is assigned. when write, set to "0". when read, its content is indeterminate. b7 b0 b15 (b7) b8 (b0) figure 1.22.6. can0 status register 4. can0 status register bits 0 3: active slot determination bits (mbox) when the can module finished transmitting data or finished storing received data, the relevant slot number is stored in these bits. the mbox bits cannot be cleared to 0 in software.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 206 bit 4: transmission-finished status (trmsucc) [set condition] this bit is set to 1 when the can module finished transmitting data normally. [clear condition] this bit is cleared when the can module finished receiving data normally. bit 5: reception-finished status (recsucc) [set condition] this bit is set to 1 when the can module finished receiving data normally (regardless of whether the received message has been stored in a message slot). however, this bit is not set if the received message is one that was transmitted in loopback mode. [clear condition] this bit is cleared when the can module finished transmitting data normally. bit 6: transmission status (trmstate) [set condition] this bit is set to 1 when the can module is operating as a transmit node. [clear condition] this bit is cleared when the can module goes to a bus-idle state or starts operating as a receive node. bit 7: reception status (recstate) [set condition] this bit is set to 1 when the can module is operating as a receive node. [clear condition] this bit is cleared when the can module goes to a bus-idle state or starts operating as a transmit node. bit 8: can reset status (state_reset) when the state_reset bit = 1, it means that the can module is in a reset state. [set condition] this bit is set to 1 when can module is in a reset state. [clear condition] this bit is cleared by clearing the reset0 or reset1 bits to 0. bit 9: loopback status (state_loopback) when the state_loopback bit = 1, it means that the can module is operating in loopback mode. [set condition] this bit is set to 1 by setting the can control register loopback bit to 1. [clear condition] this bit is cleared by clearing the loopback bit to 0.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 207 bit 11: basiccan status (state_basiccan) when the state_basiccan bit = 1, it means that the can module is operating in basiccan mode. [set condition] this bit is set to 1 when the can module is operating in basiccan mode. conditions for the can module to operate in basiccan mode are as follows: ? the can control register basiccan bit is set to 1. ? slots 14 and 15 both are set for data frame reception. [clear condition] this bit is cleared by clearing the basiccan bit to 0. bit 12: can bus error (state_buserror) [set condition] this bit is set to 1 when an error on the can bus is detected. [clear condition] this bit is cleared when the can module finished transmitting or receiving normally. clearing of this bit does not depend on whether the received message has been stored in a message slot. note :when this bit is 1, although can module is reset, this bit does not become to 0. bit 13: error passive status (state_errpas) when the state_errpas bit = 1, it means that the can module is in an error-passive state. [set condition] this bit is set to 1 when the value of c0tec register or c0rec register exceeds 127, with the can module in an error-passive state. [clear condition] this bit is cleared when the can module goes from the error-passive state to any other error state. note :when this bit is 1, then can module is reset, this bit becomes 0 automatically. bit 14: bus-off status (state_busoff) when the state_busoff bit = 1, it means that the can module is in a bus-off state. [set condition] this bit is set to 1 when the value of the c0tec register exceeds 255, with the can module in a bus- off state. [clear condition] this bit is cleared when the can module returns from the bus-off state.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 208 can0 extended id register symbol address when reset (note) c0idr 0205 16, 0204 16 0000 16 rw note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. ide15 ide14 ide13 ide12 ide11 ide10 expansion id15 (slot 15) ide9 ide8 ide7 ide6 ide5 0: standard id format 1: extended id format ide4 ide3 ide2 ide1 ide0 expansion id14 (slot 14) expansion id13 (slot 13) expansion id12 (slot 12) expansion id11 (slot 11) expansion id10 (slot 10) expansion id9 (slot 9) expansion id8 (slot 8) expansion id7 (slot 7) expansion id6 (slot 6) expansion id5 (slot 5) expansion id4 (slot 4) expansion id3 (slot 3) expansion id2 (slot 2) expansion id1 (slot 1) expansion id0 (slot 0) 0: standard id format 1: extended id format 0: standard id format 1: extended id format 0: standard id format 1: extended id format 0: standard id format 1: extended id format 0: standard id format 1: extended id format 0: standard id format 1: extended id format 0: standard id format 1: extended id format 0: standard id format 1: extended id format 0: standard id format 1: extended id format 0: standard id format 1: extended id format 0: standard id format 1: extended id format 0: standard id format 1: extended id format 0: standard id format 1: extended id format 0: standard id format 1: extended id format 0: standard id format 1: extended id format bit name function bit symbol b7 b0 b15 (b7) b8 (b0) figure 1.22.7. can0 extended id register 5. can0 extended id register this register selects the format of a frame handled by the message slot that corresponds to each bit in this register. setting any bit to 0 selects the standard (standard id) format. setting any bit to 1 selects the extended (extended id) format. note 1: when setting or resetting any bit in this register, make sure the corresponding slot has no transmit or receive request.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 209 can0 configuration register symbol address when reset (note) c0conr 0207 16, 0206 16 000x 16 rw 0 0 0: propagation time segment = 1tq 0 0 1: propagation time segment = 2tq 0 1 0: propagation time segment = 3tq 0 1 1: propagation time segment = 4tq 1 0 0: propagation time segment = 5tq 1 0 1: propagation time segment = 6tq 1 1 0: propagation time segment = 7tq 1 1 1: propagation time segment = 8tq b6 b7 b5 0 0 0: must not be set 0 0 1: phase buffer segment 1 = 2tq 0 1 0: phase buffer segment 1 = 3tq 0 1 1: phase buffer segment 1 = 4tq 1 0 0: phase buffer segment 1 = 5tq 1 0 1: phase buffer segment 1 = 6tq 1 1 0: phase buffer segment 1 = 7tq 1 1 1: phase buffer segment 1 = 8tq b9 b10 b8 0 0 0: must not be set 0 0 1: phase buffer segment 2 = 2tq 0 1 0: phase buffer segment 2 = 3tq 0 1 1: phase buffer segment 2 = 4tq 1 0 0: phase buffer segment 2 = 5tq 1 0 1: phase buffer segment 2 = 6tq 1 1 0: phase buffer segment 2 = 7tq 1 1 1: phase buffer segment 2 = 8tq b12 b13 b11 0 0: sjw = 1tq 0 1: sjw = 2tq 1 0: sjw = 3tq 1 1: sjw = 4tq b14 b15 note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. pts1 pbs11 pbs21 propagation time segment phase buffer segment 1 phase buffer segment 2 resynchronization jump width sjw0 sjw1 pbs20 pbs22 pbs10 pbs12 pts0 pts2 bit name function bit symbol sampling number 0: sampled once 1: sampled three times nothing is assigned. when write, set to "0". when read, their contents are indeterminate. sam b7 b0 b15 (b7) b8 (b0) 0 figure 1.22.8. can0 configuration register
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 210 6. can0 configuration register bit 4: sam bit (sam) this bit sets the sampling number per one bit. 0: the value sampled at the last of the phase buffer segment 1 becomes the bit value. 1: the bit value is determined by the majority operation circuit using values sampled at the following three points: the last of the phase buffer segment 1, before 1tq, and before 2tq. bits 5 7: pts bits (rts00-rts02) these bits set the width of propagation time segment. bits 8 10: pbs1 bits (pbs10-pbs12) these bits set the width of phase buffer segment 1. the pbs1 bits must be set to 1 or greater. bits 11 13: pbs2 bits (pbs20-pbs22) these bits set the width of phase buffer segment 2. the pbs2 bits must be set to 1 or greater. bits 14, 15: sjw bits (sjw0, sjw1) these bits set the width of resynchronization jump width. the sjw bits must be set to a value equal to or less than pbs2. table 1.22.2 bit timing setup example when the cpu clock = 30 mhz baud rate brp tq period (ns) 1 bit's tq number pts+pbs1 pbs2 sample point 1mbps 1 66.7 15 12 2 87% 1 66.7 15 11 3 80% 1 66.7 15 10 4 73% 2 100 10 7 2 80% 2 100 10 6 3 70% 2 100 10 5 4 60% 500kbps 2 100 20 16 3 85% 2 100 20 15 4 80% 2 100 20 14 5 75% 3 133.3 15 12 2 87% 3 133.3 15 11 3 80% 3 133.3 15 10 4 73% 4 166.7 12 9 2 83% 4 166.7 12 8 3 75% 4 166.7 12 7 4 67% 5 200 10 7 2 80% 5 200 10 6 3 70% 5 200 10 5 4 60%
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 211 can0 transmit error count register symbol address when reset (note) c0tec 020a 16 00 16 rw function transmit error count value note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. b7 b0 8-bit figure 1.22.9. can0 time stamp register 7. can0 timestamp register the can module incorporates a 16-bit counter. the count period for this counter can be derived from the can bus bit period by dividing it by 1, 2, 3, or 4 using the can0 control register0 (c0ctlr0) s tspre0, 1 bits. when the can module finishes transmitting or receiving, the can0 timestamp register (c0tsr) value is captured and the value is automatically stored in a message slot. the c0tsr register starts counting upon clearing the c0ctlr register s reset and reset1 bits to 0. note 1: setting the c0ctlr0 register s reset0 and reset1 bits to 1 resets can, and the c0tsr register thereby initialized to 0000 16 . also, setting the tsreset (timestamp counter reset) bit to 1 initializes the c0tsr register to 0000 16 on-the-fly (while the can remains operating; can0 status register's state_reset bit is "0"). note 2: during loopback mode, if any receive slot exists in which a message can be stored, the c0tsr register value is stored in the corresponding slot when the can module finished receiving. (this storing of the c0tsr register value does not occur at completion of trans- mission.) figure 1.22.10. can0 transmit error count register 8. can0 transmit error count register when in an error active or an error passive state, the transmit error count value is stored in this register. the count is decremented when the can module finished transmitting normally or incremented when an error occurred while transmitting. when in a bus-off state, an indeterminate value is stored in this register. the register is reset to 00 16 upon returning to an error active state. can0 time stamp register symbol address when reset (note) c0tsr 0209 16, 0208 16 0000 16 rw function setting range 16 bits count value 0000 16 to ffff 16 b15 (b7) (upper 8-bit) (lower 8-bit) b8 (b0)b7 b0 note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 212 can0 baud rate prescaler symbol address when reset (note 1) c0brp 0217 16 01 16 rw function setting range note 1: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. note 2: do not set to "00 16 " (division by 1). 01 16 to ff 16 baud rate prescaler value selected (note 2) 8-bit b7 b0 figure 1.22.11. can0 reception error count register 9. can0 reception error count register when in an error active or an error passive state, the receive error count value is stored in this register. the count is decremented when the can module finished receiving normally or incremented when an error occurred while receiving. when c0rec > 128 (error passive state) at the time the can module finished receiving normally, the c0rec register is set to 127. when in a bus-off state, an indeterminate value is stored in this register. the register is reset to 00 16 upon returning to an error active state. figure 1.22.12. can0 baud rate register 10. can0 baud rate prescaler this register is used to set the tq period, the can bit time. the can baud rate is determined by (tq period x number of tq s in one bit). tq period = (c0brp+1)/cpu clock can baud rate = 1 / (tq period x number of tq s in one bit) number of tq s in one bit = synchronization segment + propagation time segment + phase buffer segment 1 + phase buffer segment 2 can0 reception error count register symbol address when reset (note) c0rec 020b 16 00 16 rw function reception error count value note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. b7 b0 8-bit
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 213 can0 slot interrupt status register symbol address when reset (note 1) c0sistr 020d 16, 020c 16 0000 16 rw note 1: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. note 2: "0" can be set. when set to "1", the previous value is remained. sis15 sis14 sis13 sis12 sis11 sis10 slot 15 interrupt request status bit sis9 sis8 sis7 sis6 sis5 slot 14 interrupt request status bit slot 13 interrupt request status bit slot 12 interrupt request status bit slot 11 interrupt request status bit slot 10 interrupt request status bit slot 9 interrupt request status bit slot 8 interrupt request status bit slot 7 interrupt request status bit slot 6 interrupt request status bit slot 5 interrupt request status bit slot 4 interrupt request status bit slot 3 interrupt request status bit slot 2 interrupt request status bit slot 1 interrupt request status bit slot 0 interrupt request status bit sis4 sis3 sis2 sis1 sis0 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) bit name function bit symbol b7 b0 b15 (b7) b8 (b0) figure 1.22.13. can slot interrupt status register
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 214 9. can0 slot interrupt status register when using can interrupts, the can0 slot interrupt status register helps to know which slot requested an interrupt. for transmit slots the status is set to 1 when the can module finished storing the can timestamp register value in the message slot after completing transmission. to clear this bit, write 0 in software (note 1) . for receive slots the status is set to 1 when the can module finished storing the received message in the message slot after completing reception. to clear this bit, write 0 in software (note 1) . note 1: to clear any bit of the can interrupt status register, write 0 to the bit to be cleared and 1 to all other bits, without using bit clear instructions. example : assembler language mov.w #07fffh, c0sistr c language c0sister = 0x7fff; note 2: for remote frame receive slots whose automatic answering function is enabled, the slot interrupt status bit is set when the can module finished receiving a remote frame and when it finished transmitting a data frame. note 3: for remote frame transmit slots, the slot interrupt status bit is set when the can module finished transmitting a remote frame and when it finished receiving a data frame. note 4: if the slot interrupt status bit is set by an interrupt request at the same time it is cleared by writing in software, the former has priority, i.e., the slot interrupt status bit is set.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 215 can0 slot interrupt mask register symbol address when reset (note) c0simkr 0211 16, 0210 16 0000 16 rw note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. sim15 sim14 sim13 sim12 sim11 sim10 slot 15 interrupt request mask bit sim9 sim8 sim7 sim6 sim5 slot 14 interrupt request mask bit slot 13 interrupt request mask bit slot 12 interrupt request mask bit slot 11 interrupt request mask bit slot 10 interrupt request mask bit slot 9 interrupt request mask bit slot 8 interrupt request mask bit slot 7 interrupt request mask bit slot 6 interrupt request mask bit slot 5 interrupt request mask bit slot 4 interrupt request mask bit slot 3 interrupt request mask bit slot 2 interrupt request mask bit slot 1 interrupt request mask bit slot 0 interrupt request mask bit 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled sim4 sim3 sim2 sim1 sim0 bit name function bit symbol b7 b0 b15 (b7) b8 (b0) figure 1.22.14. can0 slot interrupt mask register 12. can0 slot interrupt mask register this register controls can interrupts by enabling or disabling interrupt requests generated by each corresponding slot at completion of transmission or reception. setting any bit of this register (simn where n = 0 C 15) to 1 enables the interrupt request to be generated by the corresponding slot at completion of transmission or reception.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 216 boim epim beim can0 error interrupt mask register symbol address when reset (note) c0eimkr 0214 16 xxxx x000 2 rw 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled 0: interrupt request masked (disabled) 1: interrupt request enabled note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. bit name function bit symbol bus off interrupt mask bit error passive interrupt mask bit can bus error interrupt mask bit nothing is assigned. when write, set to "0". when read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 figure 1.22.15. can0 error interrupt mask register 13. can0 error interrupt mask register bit 0: bus-off interrupt mask bit (boim) this bit controls can interrupts by enabling or disabling interrupt requests generated when the can module goes to a bus-off state. setting this bit to 1 enables a bus-off interrupt request. bit 1: error passive interrupt mask bit (epim) this bit controls can interrupts by enabling or disabling interrupt requests generated when the can module goes to an error passive state. setting this bit to 1 enables an error passive interrupt request. bit 2: can bus error interrupt mask bit (beim) this bit controls can interrupts by enabling or disabling interrupt requests generated by occurrence of a can bus error. setting this bit to 1 enables a can bus error interrupt request.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 217 note 1: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. note 2: "0" can be set. when set to "1", the previous value is remained. can0 error interrupt status register symbol address when reset (note 1) c0eistr 0215 16 xxxx x000 2 rw bois epis beis bus off interrupt status bit error passive interrupt status bit can bus error interrupt status bit 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) 0: interrupt not requested 1: interrupt requested (note 2) bit name function bit symbol nothing is assigned. when write, set to "0". when read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 figure 1.22.16. can0 error interrupt status register 14. can0 error interrupt status register when using can interrupts, the can error interrupt status register helps to verify the causes of error-derived interrupts. bit 0: bus-off interrupt status bit (bois) this bit is set to 1 when the can module goes to a bus-off state. to clear this bit, write 0 in software (note 1) . bit 1: error passive interrupt status bit (epis) this bit is set to 1 when the can module goes to an error passive state. to clear this bit, write 0 in software (note 1) . bit 2: can bus error interrupt status bit (beis) this bit is set to 1 when a can communication error is detected. to clear this bit, write 0 in software (note 1) . note 1: to clear any bit of the can error interrupt status register, write 0 to the bit to be cleared and 1 to all other bits, without using bit clear instructions. example: assembler language mov.b #006h, c0eistr c language c0eistr = 0x06;
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 218 slot 8 transmit/receive finished sis8 slot 14 transmit/receive finished slot 13 transmit/receive finished can0 transmit/ receive error interrupt b0 sim15 f/f sis15 f/f b0 b1 sim14 f/f sis14 f/f b1 b2 sim13 f/f sis13 f/f b2 b3 sim12 f/f sis12 f/f b3 b4 sim11 f/f sis11 f/f b4 c0sistr c0simkr slot 15 transmit/receive finished b5 sim10 f/f sis10 f/f b5 b6 sim9 f/f sis9 f/f b6 b7 sim8 f/f slot 12 transmit/receive finished slot 11 transmit/receive finished slot 10 transmit/receive finished slot 9 transmit/receive finished f/f b7 to 11 other input sources on the next page data bus (level) 19-source inputs figure 1.22.17. can0 transmit, receive and error interrupt block diagram (1/3)
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 219 to previous page b8 sim7 f/f sis7 f/f b8 b9 sim6 f/f sis6 f/f b9 b10 sim5 f/f sis5 f/f b10 b11 sim4 f/f sis4 f/f b11 b12 sim3 f/f sis3 f/f b12 slot 7 transmit/receive finished b13 sim2 f/f sis2 f/f b13 b14 sim1 f/f sis1 f/f b14 b15 sim0 f/f to 3 other input sources on the next page f/f b15 sis0 slot 6 transmit/receive finished slot 5 transmit/receive finished slot 4 transmit/receive finished slot 3 transmit/receive finished slot 2 transmit/receive finished slot 1 transmit/receive finished slot 0 transmit/receive finished c0sistr c0simkr data bus (level) 19-source inputs figure 1.22.18. can0 transmit, receive and error interrupt block diagram (2/3)
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 220 b2 beim f/f beis f/f b2 b1 epim f/f epis f/f b1 b0 boim f/f bois f/f b0 can bus error occur shift to error passive state shift to bus off state c0eistr c0eimkr data bus (level) 19-source inputs to the previous page figure 1.22.19. can0 transmit, receive and error interrupt block diagram (3/3)
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 221 can0 global mask register standard id0 can0 local mask register a, b standard id0 symbol address when reset (note) c0gmr0 0228 16 xxx0 0000 2 c0lmar0 0230 16 xxx0 0000 2 c0lmbr0 0238 16 xxx0 0000 2 rw sid6m sid7m sid8m sid9m standard id6 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked standard id7 standard id8 standard id9 sid10m standard id10 0: id not checked 1: id checked note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. bit name function bit symbol nothing is assigned. when write, set to "0". when read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 figure 1.22.20. can0 global mask register standard id0 and can0 local mask register a, b standard id0 15. can0 global mask register standard id0 can0 local mask register a, b standard id0 the mask registers used for acceptance filtering consist of the global mask register, local mask register a, and local mask register b. the global mask register takes care of message slots 0 C 13 whereas local mask registers a and b are used for message slots 14 and 15, respectively. ? if any bit of this register is set to 0, its corresponding id bit is masked during acceptance filtering. (the masked bit is not checked for id; the id is assumed to be matching.) ? if any bit of this register is set to 1, its corresponding id bit is compared with the received id during acceptance filtering. if it matches the id that is set in any message slot, the received data is stored in that slot. note 1: the global mask register can only be modified when none of the slots 0 C 13 has receive requests set. note 2: the local mask register a can only be modified when slot 14 has no receive requests set. note 3: the local mask register b can only be modified when slot 15 has no receive requests set.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 222 can0 global mask register standard id1 can0 local mask register a, b standard id1 symbol address when reset (note) c0gmr1 0229 16 xx00 0000 2 c0lmar1 0231 16 xx00 0000 2 c0lmbr1 0239 16 xx00 0000 2 rw standard id0 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked standard id1 standard id2 standard id3 standard id4 standard id5 0: id not checked 1: id checked 0: id not checked 1: id checked sid0m sid1m sid2m sid3m sid4m sid5m note: this applies when the can module is supplied with a clock by setting the sleep mode control bit ( bit 0 at address 0242 16 ) to 1 after reset. bit name function bit symbol nothing is assigned. when write, set to "0". when read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 figure 1.22.21. can0 global mask register standard id1 and can0 local mask register a, b standard id1 16. can0 global mask register standard id1 can0 local mask register a, b standard id1 the mask registers used for acceptance filtering consist of the global mask register, local mask register a, and local mask register b. the global mask register takes care of message slots 0 C 13 whereas local mask registers a and b are used for message slots 14 and 15, respectively. ? if any bit of this register is set to 0, its corresponding id bit is masked during acceptance filtering. (the masked bit is not checked for id; the id is assumed to be matching.) ? if any bit of this register is set to 1, its corresponding id bit is compared with the received id during acceptance filtering. if it matches the id that is set in any message slot, the received data is stored in that slot. note 1: the global mask register can only be modified when none of the slots 0 C 13 has receive requests set. note 2: the local mask register a can only be modified when slot 14 has no receive requests set. note 3: the local mask register b can only be modified when slot 15 has no receive requests set.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 223 can0 global mask register extend id0 can0 local mask register a, b extend id0 symbol address when reset (note) c0gmr2 022a 16 xxxx 0000 2 c0lmar2 0232 16 xxxx 0000 2 c0lmbr2 023a 16 xxxx 0000 2 rw eid14m eid15m eid16m eid17m extend id14 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked extend id15 extend id16 extend id17 note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. bit name function bit symbol nothing is assigned. when write, set to "0". when read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 figure 1.22.22. can0 global mask register extend id0 and can0 local mask register a, b extend id0 17. can0 global mask register extend id0 can0 local mask register a, b extend id0 the mask registers used for acceptance filtering consist of the global mask register, local mask register a, and local mask register b. the global mask register takes care of message slots 0 C 13 whereas local mask registers a and b are used for message slots 14 and 15, respectively. ? if any bit of this register is set to 0, its corresponding id bit is masked during acceptance filtering. (the masked bit is not checked for id; the id is assumed to be matching.) ? if any bit of this register is set to 1, its corresponding id bit is compared with the received id during acceptance filtering. if it matches the id that is set in any message slot, the received data is stored in that slot. note 1: the global mask register can only be modified when none of the slots 0 C 13 has receive requests set. note 2: the local mask register a can only be modified when slot 14 has no receive requests set. note 3: the local mask register b can only be modified when slot 15 has no receive requests set.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 224 can0 global mask register extend id1 can0 local mask register a, b extend id1 symbol address when reset (note) c0gmr3 022b 16 00 16 c0lmar3 0233 16 00 16 c0lmbr3 023b 16 00 16 rw eid6m eid7m eid8m eid9m eid10m eid11m eid13m eid12m extend id6 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked extend id7 extend id8 extend id9 extend id10 extend id11 extend id12 extend id13 note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 figure 1.22.23. can0 global mask register extend id1 and can0 local mask register a, b extend id1 18. can0 global mask register extend id1 can0 local mask register a, b extend id1 the mask registers used for acceptance filtering consist of the global mask register, local mask register a, and local mask register b. the global mask register takes care of message slots 0 C 13, whereas local mask registers a and b are used for message slots 14 and 15, respectively. ? if any bit of this register is set to 0, its corresponding id bit is masked during acceptance filtering. (the masked bit is not checked for id; the id is assumed to be matching.) ? if any bit of this register is set to 1, its corresponding id bit is compared with the received id during acceptance filtering. if it matches the id that is set in any message slot, the received data is stored in that slot. note 1: the global mask register can only be modified when none of the slots 0 C 13 has receive requests set. note 2: the local mask register a can only be modified when slot 14 has no receive requests set. note 3: the local mask register b can only be modified when slot 15 has no receive requests set.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 225 note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. can0 global mask register extend id2 can0 local mask register a, b extend id2 symbol address when reset (note) c0gmr4 022c 16 xx00 0000 2 c0lmar4 0234 16 xx00 0000 2 c0lmbr4 023c 16 xx00 0000 2 rw eid0m eid1m eid2m eid3m eid4m eid5m extend id0 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked 0: id not checked 1: id checked extend id1 extend id2 extend id3 extend id4 extend id5 bit name function bit symbol nothing is assigned. when write, set to "0". when read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 figure 1.22.24. can0 global mask register extend id2 and can0 local mask register a, b extend id2 19. can0 global mask register extend id2 can0 local mask register a, b extend id2 the mask registers used for acceptance filtering consist of the global mask register, local mask register a, and local mask register b. the global mask register takes care of message slots 0 C 13, whereas local mask registers a and b are used for message slots 14 and 15, respectively. ? if any bit of this register is set to 0, its corresponding id bit is masked during acceptance filtering. (the masked bit is not checked for id; the id is assumed to be matching.) ? if any bit of this register is set to 1, its corresponding id bit is compared with the received id during acceptance filtering. if it matches the id that is set in any message slot, the received data is stored in that slot. note 1: the global mask register can only be modified when none of the slots 0 C 13 has receive requests set. note 2: the local mask register a can only be modified when slot 14 has no receive requests set. note 3: the local mask register b can only be modified when slot 15 has no receive requests set.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 226 can0 message slot i control register (i=0 to 15) symbol address when reset (note 1) c0mctli(i=0 to 5) 0230 16, 0231 16, 0232 16, 0233 16, 0234 16, 0235 16 00 16 c0mctli(i=6 to 11) 0236 16, 0237 16, 0238 16, 0239 16, 023a 16, 023b 16 00 16 c0mctli(i=12 to 15) 023c 16, 023d 16, 023e 16, 023f 16 00 16 rw when receive, newdata when transmit, sentdata when receive, invaldata when transmit, trmactive msglost remactive rsplock remote trmreq recreq transmit/receive finished flag using basiccan mode 0: data flame received (status) 1: remote flame received (status) not using basiccan mode 0: data flame 1: remote flame 0: automatic answering of remote flame enable 1: automatic answering of remote flame disable 0: transmit/receive data flame 1: transmit/receive remote flame 0: reception not requested 1: reception requested 0: transmission not requested 1: transmission requested transmitting/ receiving flag overwrite flag remote flame transmit/receive status flag automatic answering disable bit remote frame set bit receive request bit transmit request bit 0: over run error not occurred 1: over run error occurred (note 2) 0: not transmitted yet 0: not received yet 1: finished transmitting 1: finished receiving when transmitting when receiving 0: stopped transmitting 0: stopped receiving 1: accepted transmit request 1: storing received data when transmitting when receiving bit name function bit symbol note 1: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. note 2: "0" can be set. when set to "1", the previous value is remained. (note 2) (note 2) b7 b6 b5 b4 b3 b2 b1 b0 figure 1.22.25. can0 message slot i control register
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 227 20. can0 message slot i control register bit 0: transmission finished flag /reception finished flag (sentdata, newdata) this bit indicates that the can module finished transmitting or receiving a message. ? for transmit slots the bit is set to 1 when the can module finished transmitting from the message slot. this bit is cleared by writing 0 in software. however, it cannot be cleared when the trmactive (transmit/receive status) bit = 1. ? for receive slots the bit is set to 1 when the can module finished receiving a message normally that is to be stored in the message slot. this bit is cleared by writing 0 in software. however, it cannot be cleared when the invaldata (trans- mit/receive status) bit = 1. note 1: before reading received data from the message slot, be sure to clear the newdata (transmis- sion/reception finished status) bit. also, if the newdata bit is set to 1 after readout, it means that new received data has been stored in the message slot while reading out from the slot, and that the read data contains an indeterminate value. in this case, discard the read data and clear the newdata bit before reading out from the slot again. note 2: the newdata bit is not set by a completion of remote frame transmission or reception. bit 1: transmitting flag /receiving flag (trmactive, invaldata) this bit indicates that the can module is transmitting or receiving a message, with the message slot being accessed. the bit is set to 1 when the can module is accessing the message slot and set to 0 when not accessing the message slot. ? for transmit slots this bit is set to 1 when the message slot has its transmit request accepted. if the message slot failed in arbitration, this bit is cleared to 0 by occurrence of a can bus error or completion of trans- mission. ? for receive slots this bit is set to 1 when the can module is receiving a message, with the received message being stored in the message slot. note that the value read out from the message slot while this bit remains set is indeterminate. bit 2: overwrite flag (msglost) this bit is useful for the receive slots, those that are set for reception. this bit is set to 1 when while the message slot contains an unread received message, it is overwritten by a new received mes- sage. this bit is cleared by writing 0 in software. bit 3: remote frame transmit/receive status flag (remactive) this bit functions differently for slots 0 C 13 and slots 14, 15. ? for slots 0 C 13 if the slot is set for remote frame transmission (or reception), this bit is set to 1. then, when the slot finished transmitting (or receiving) a remote frame, this bit is cleared to 0.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 228 ? for slots 14 and 15 the remactive bit functions differently depending on how the can control register s basiccan (basiccan mode) bit is set. when basiccan = 0 (operating normally), if the slot is set for remote frame transmission (or recep- tion), the remactive bit is set to 1. when basiccan = 1 (operating in basiccan mode), the remactive bit indicates which frame type of message was received. during basiccan mode, slots 14 and 15 store the received data whether it be a data frame or a remote frame. if remactive = 0, it means that the message stored in the slot is a data frame. if remactive = 1, it means that the message stored in the slot is a remote frame. bit 4: automatic answering disable bit (rsplock) this bit is useful for the slots set for remote frame reception, indicating the processing to be per- formed after receiving a remote frame. if this bit is set to 0, the slot automatically changes to a transmit slot after receiving a remote frame and the message stored in the slot is transmitted as a data frame. if this bit is set to 1, the slot stops operating after receiving a remote frame. note 1: this bit must always be set to 0 for any slots other than those set for remote frame reception. bit 5: remote frame set bit (remote) set this bit to 1 for the message slots that handle a remote frame. message slots can be set to handle a remote frame in the following two ways. ? set to transmit a remote frame and receive a data frame the message stored in the message slot is transmitted as a remote frame. the slot automatically changes to a data frame receive slot after it finished transmitting. however, if it receives a data frame before it finishes transmitting a remote frame, the data frame is stored in the message slot and the remote frame is not transmitted. ? set to receive a remote frame and transmit a data frame the slot receives a remote frame. the processing to be performed after receiving a remote frame depends on how the rsplock (automatic answering disable) bit is set. bit 6: receive request bit (recreq) set this bit to 1 when using any message slot as a receive slot. set this bit to 0 when using any message slot as a data frame transmit or remote frame transmit slot. if the trmreq (transmit request) bit and recreq (receive request) bit both are set to 1, the operation of the can module is indeterminate. bit 7: transmit request bit (trmreq) set this bit to 1 when using any message slot as a transmit slot. set this bit to 0 when using any message slot as a data frame receive or remote frame receive slot.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 229 note 1: there is a total of 16 can0 message slots for transmission and reception uses, respectively. each message slot can be selected for use as a transmit or a receive slot. note 2: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. can0 slot buffer select register symbol address when reset (note 2) c0sbs 0240 16 00 16 rw sbs00 sbs01 can0 message slot buffer 0 number select bit can0 message slot buffer 1 number select bit sbs02 sbs03 sbs10 sbs11 sbs12 sbs13 0 0 0 0 : slot 0 0 0 1 0 : slot 1 0 0 1 1 : slot 2 0 1 0 0 : slot 3 (note 1) (note 1) bit name function bit symbol b3 b2 b1 b0 1 1 0 0 : slot 12 1 1 0 1 : slot 13 1 1 1 0 : slot 14 1 1 1 1 : slot 15 ? ? ? ? ? ? 0 0 0 0 : slot 0 0 0 1 0 : slot 1 0 0 1 1 : slot 2 0 1 0 0 : slot 3 b3 b2 b1 b0 1 1 0 0 : slot 12 1 1 0 1 : slot 13 1 1 1 0 : slot 14 1 1 1 1 : slot 15 ? ? ? ? ? ? b7 b6 b5 b4 b3 b2 b1 b0 figure 1.22.26. can0 slot buffer select register 21. can0 slot buffer select register bits 0-3: can0 message slot buffer 0 slot number select bits (sbs0) the message slot whose number is selected with these bits appears in can0 message slot buffer 0. bits 4-7: can0 message slot buffer 1 slot number select bits (sbs1) the message slot whose number is selected with these bits appears in can0 message slot buffer 1. the selected message slot can be identified by reading the message slot buffer. a message written to the message slot buffer is stored in the selected message slot.
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 230 can0 message slot buffer i standard id1 (i=0,1) (note) symbol address when reset c0sloti_1(i=0,1) 01e1 16, 01f1 16 indeterminate rw sid0 sid1 sid2 sid3 sid4 sid5 standard id0 message slot j (j=0 to 15) standard id1 standard id2 standard id3 standard id4 standard id5 message slot j (j=0 to 15) message slot j (j=0 to 15) message slot j (j=0 to 15) message slot j (j=0 to 15) message slot j (j=0 to 15) bit name function bit symbol nothing is assigned. when write, set to "0". when read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 note: can0 message slot j standard id1 (j=0 to 15) is stored in this register. j is selected with the slot buffer select register. can0 message slot buffer i standard id0 (i=0,1) (note) symbol address when reset c0sloti_0(i=0,1) 01e0 16, 01f0 16 indeterminate rw sid6 sid7 sid8 sid9 sid10 standard id6 standard id7 standard id8 standard id9 standard id10 message slot j (j=0 to 15) message slot j (j=0 to 15) message slot j (j=0 to 15) message slot j (j=0 to 15) message slot j (j=0 to 15) bit name function bit symbol nothing is assigned. when write, set to "0". when read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 note: can0 message slot j standard id0 (j=0 to 15) is stored in this register. j is selected with the slot buffer select register. figure 1.22.27. can0 message slot buffer i standard id0 and id1
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 231 can0 message slot buffer i extend id1 (i=0,1) (note 1,2) symbol address when reset c0sloti_3(i=0,1) 01e3 16, 01f3 16 indeterminate rw eid6 eid7 eid8 eid9 extended id6 message slot j (j=0 to 15) extended id7 extended id8 extended id9 message slot j (j=0 to 15) message slot j (j=0 to 15) message slot j (j=0 to 15) eid10 eid11 extended id10 extended id11 message slot j (j=0 to 15) message slot j (j=0 to 15) eid12 eid13 extended id12 extended id13 message slot j (j=0 to 15) message slot j (j=0 to 15) bit name function bit symbol note 1: when receive slot is standard id format, eid bits are indeterminate when saving received data. note 2: can0 message slot j extend id1 (j=0 to 15) is stored in this register. j is selected with the slot buffer select register. b7 b6 b5 b4 b3 b2 b1 b0 can0 message slot buffer i extend id0 (i=0,1) (note 1, 2) symbol address when reset c0sloti_2(i=0,1) 01e2 16, 01f2 16 indeterminate rw eid14 eid15 extended id14 extended id15 message slot j (j=0 to 15) message slot j (j=0 to 15) eid16 eid17 extended id16 extended id17 message slot j (j=0 to 15) message slot j (j=0 to 15) bit name function bit symbol nothing is assigned. when write, set to "0". when read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 note 1: when receive slot is standard id format, eid bits are indeterminate when saving received data. note 2: can0 message slot j extend id0 (j=0 to 15) is stored in this register. j is selected with the slot buffer select register. figure 1.22.28. can0 message slot buffer i extended id0 and id1
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 232 can0 message slot buffer i data length code (i=0,1)(note) symbol address when reset c0sloti_5(i=0,1) 01e5 16, 01f5 16 indeterminate rw message slot j (j=0 to 15) dlc0 dlc1 dlc2 dlc3 data length set bit nothing is assigned. when write, set to "0". when read, their contents are indeterminate. bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 note : can0 message slot j data length code (j=0 to 15) is stored in this register. j is selected with the slot buffer select register. can0 message slot buffer i extend id2 (i=0,1) (note 1,2) symbol address when reset c0sloti_4(i=0,1) 01e4 16, 01f4 16 indeterminate rw eid0 eid1 eid2 eid3 extended id0 message slot j (j=0 to 15) extended id1 extended id2 extended id3 message slot j (j=0 to 15) message slot j (j=0 to 15) message slot j (j=0 to 15) eid4 eid5 extended id4 extended id5 message slot j (j=0 to 15) message slot j (j=0 to 15) bit name function bit symbol note 1: when receive slot is standard id format, eid bits are indeterminate when saving received data. note 2: can0 message slot j extend id2 (j=0 to 15) is stored in this register. j is selected with the slot buffer select register. nothing is assigned. when write, set to "0". when read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 figure 1.22.29. can0 message slot buffer i extended id2 and can0 message slot buffer i data lengthcode
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 233 can0 message slot buffer i time stamp high (i=0,1) (note) symbol address when reset c0sloti_14(i=0,1) 01ee 16, 01fe 16 indeterminate r w function setting range message slot j time stamp high (j=0 to 15) 00 16 to ff 16 note : can0 message slot j time stamp high (j=0 to 15) is stored in this register. j is selected with the slot buffer select register. b7 b0 can0 message slot buffer i time stamp low (i=0,1) (note) symbol address when reset c0sloti_15(i=0,1) 01ef 16, 01ff 16 indeterminate r w function setting range message slot j time stamp low (j=0 to 15) 00 16 to ff 16 note : can0 message slot j time stamp low (j=0 to 15) is stored in this register. j is selected with the slot buffer select register. b7 b0 figure 1.22.30. can0 message slot buffer i data m and can0 message slot buffer i time stamp can0 message slot buffer i data m (i=0,1 m=0 to 7) symbol address when reset c0slot0_n(n=m+6,m=0 to 3) 01e616, 01e716, 01e816, 01e916 indeterminate c0slot0_n(n=m+6,m=4 to 7) 01ea16, 01eb16, 01ec16, 01ed16 indeterminate c0slot1_n(n=m+6,m=0 to 3) 01f616, 01f716, 01f816, 01f916 indeterminate c0slot1_n(n=m+6,m=4 to 7) 01fa16, 01fb16, 01fc16, 01fd16 indeterminate r w function setting range message slot j data m (j=0 to 15, m=0 to 7) 00 16 to ff 16 note: j is selected with the slot buffer select register (note) b7 b0
can module under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 234 when receive id is "6f3 16 " write to c0afs 0011001100011011 sid4 sid3 sid2 sid1 sid0 sid10sid9 sid8 sid7 sid6 11011110011 "6" "f" "3" "d" "e" "3" sid10 sid0 read from c0afs 0000100011011110 divide to 8 bits and 3 bits receive id "d" "e" "08 16 " bit search information address search information sid5 b7 b8 b0 b15 b7 b8 b0 b7 b0 b15 01 16 02 16 04 16 08 16 10 16 20 16 40 16 80 16 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 bit search information low-order 3 bits of receive id 8 bits 3 bits because the value of these three bits is 3, bit 3 in the table below is 1. (if the value of these three bits is 4, bit 4 in the table below is 1.) b3 can0 acceptance filter support register symbol address when reset (note) c0afs 0245 16, 0244 16 0100 16 rw function setting range produces receive id determination data 0000 16 to ffff 16 note: this applies when the can module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242 16 ) to 1 after reset. b15 b0 b8 b7 b15 b0 sid5 sid4 sid3 sid2 sid1 sid0 sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 csid2 csid1 csid0 sid10 sid9 sid8 sid7 sid6 csid5 csid4 csid3 csid7 csid6 write read 3-8 decode b7 b8 b15 b0 from the receive id of the standard for- mat, this register produces data with which to search the data table. after searching the table using this data, the can module determines whether the receive id is valid or not. 007 16 "0" 006 16 "0" 005 16 "0" 004 16 "0" 003 16 "0" 002 16 "0" 001 16 "1" 000 16 "0" 00f 16 "1" 00e 16 "0" 00d 16 "0" 00c 16 "0" 00b 16 "0" 00a 16 "0" 009 16 "0" 008 16 "0" 6f7 16 "0" 6f6 16 "0" 6f5 16 "0" 6f4 16 "0" 6f3 16 "1" 6f2 16 "0" 6f1 16 "0" 6f0 16 "0" 7f7 16 "0" 7f6 16 "0" 7f5 16 "0" 7f4 16 "0" 7f3 16 "0" 7f2 16 "0" 7f1 16 "0" 7f0 16 "1" 7ff 16 "0" 7fe 16 "0" 7fd 16 "1" 7fc 16 "0" 7fb 16 "0" 7fa 16 "0" 7f9 16 "0" 7f8 16 "0" top+00 16 top+01 16 top+fe 16 top+ff 16 top+de 16 b7 b6 b5 b4 b3 b2 b1 b0 address search information bit search information figure 1.22.31. can0 acceptance filter support register
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 235 intelligent i/o intelligent i/o uses multifunctional i/o ports for time measurement, waveform generation, clock-synchro- nous/asynchronous (uart) serial i/o, ie bus (note) communications, hdlc data processing and more. a single intelligent i/o group comes with one 16-bit base timer for free running, eight 16-bit registers for time measurement and waveform generation, and two shift registers for 8-bit and 16-bit communications. the m32c/83 has four internal intelligent i/o groups. table 1.23.1 lists functions by group. table 1.23.1. list of functions of intelligent i/o function group 0 group 1 group 2 group 3 group 0,1 cascaded configuration ? base timer 1 1 1 1 1 ? tm 4ch(2ch) CC C C ? tm/wg register (shared) 4chs(1ch) 4chs(2chs) CC 8chs(3chs) ? wg register C 4chs(1ch) 8chs 8chs(3chs) 8chs(2chs) ? communication shift register 8bits x 2chs 8bits x 2chs 8bits x 2chs CC time measurement functions max. 8chs max. 4chs CC max. 8chs (3chs) (2chs) (3chs) ? digital filter function ? CC ? trigger input prescale function 2chs 2chs CC 2chs ? gate function for trigger input 2chs 2chs CC 2chs wg function max. 4chs max. 8chs max. 8chs max. 8chs max. 8chs (1ch) (3chs) (3chs) (2chs) (1ch) ? single phase waveform output ?? ? phase delayed waveform output ?? ? set/reset waveform output ?? ? bit modulation pwm output CC ? C ? real-time port output CC ? C ? parallel real-time port output CC ? C communication functions ? bit length 8 bits fixed 8 bits fixed variable length CC ? communication mode 1. clock synchronous serial i/o ?? CC 2. uart ? CC C 3. hdlc data processing ? CC C 4. ie bus sub set CC CC note 1: ie bus is a trademark of nec. note 2: 100-pin specification are in parentheses. : present C : not present tm:time measurement wg:waveform genaration
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 236 ch0 tm/wg register 16-bit base timer pwm output reset reset request from communication block gr1 base timer reset 2 x (n+1) divider f 1 edge select digital filter gate function edge select digital filter gate function edge select digital filter edge select digital filter edge select digital filter edge select digital filter edge select digital filter edge select digital filter pwm output pwm output inpc0 0 inpc0 1 /isclk0 inpc0 2 /isrxd0 inpc0 3 inpc0 4 inpc0 5 inpc0 6 inpc0 7 bts bt0s df df df df df df df df gt gt pr pr 8 / ch0 to ch7 interrupt request signal outc0 0 / ist x d0 outc0 1 / isclk0 outc0 4 outc0 5 arbitration comparator (8-bit) comparator (8-bit) comparator (8-bit) comparator (8-bit) special interrupt check 4 / comparison register (8-bit) comparison register (8-bit) comparison register (8-bit) comparison register (8-bit) 4 / buffer register data register (8-bit) shift register 4 / prescale function prescale function start bit generation circuit bit insert circuit sof generation circuit parity bit generation circuit stop bit generation circuit transmit latch transmit data generation circuit transmit crc clock wait control circuit si/o transmit buffer register (8-bit) transmit register transmit buffer transmit output register (8-bit) si/o receive buffer register (8bit) receive data generation circuit start bit check parity bit check bit insert check stop bit check receive crc receive input register (8bit) polarity reversing clock selector clock selector tm input to gr1 (when cascaded) start bit hdlc data process interrupt transmit interrupt hdlc data transmit interrupt receive interrupt special communication interrupt wg input to gr1 (when cascaded) polarity reversing transmit buffer receive buffer receive shift register receive shit register tm: time measurement wg: waveform generation receive buffer ch1 tm/wg register ch2 tm register ch3 tm register ch4 tm/wg register ch5 tm/wg register ch6 tm register ch7 tm register transmission reception base timer carry output (note 1) (note 1) transmit shift register note 1: these pins aren't connected with external pins in 100-pin version. note 2: each register becomes reset status after supplying a clock by setting of the base timer control register 0. block diagrams for groups 0 to 3 are given in figures 1.23.1 to 1.23.4. figure 1. 23. 1. block diagram of intelligent i/o group 0
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 237 transmission reception ch1 tm/wg register ch2 tm/wg register ch3 tm/wg register ch4 tm/wg register ch5 tm/wg register ch6 tm/wg register ch7 tm/wg register pwm output 2 x (n+1) divider edge select digital filter gate function edge select digital filter gate function edge select digital filter edge select digital filter pwm output pwm output inpc1 1 inpc1 2 inpc1 6 inpc1 7 bts bt1s df df df df gt gt pr pr 8 / outc1 0 /ist x d1 /be1out outc1 1 /isclk1 outc1 4 outc1 5 arbitration comparator (8-bit) comparator (8-bit) comparator (8-bit) comparator (8-bit) special interrupt check 4 / comparison register (8-bit) comparison register (8-bit) comparison register (8-bit) comparison register (8-bit) 4 / buffer register data register (8-bit) shift register 4 / prescale function prescale function start bit generation circuit bit insert circuit sof generation circuit parity bit generation circuit stop bit generation circuit transmit latch transmit data generation circuit clock wait control circuit si/o transmit buffer register (8-bit) transmit register transmit buffer transmit output register (8-bit) receive shift register receive data generation circuit start bit check parity bit check bit insert check stop bit check receive crc clock selector clock selector pwm output outc1 6 outc1 7 outc1 2 outc1 3 f 1 tm input from gr0 (when cascaded) wg input from gr0 (when cascaded) ch0 tm/wg register 16bits base timer reset reset request from communication block gr0 base timer reset ch0 to ch7 interrupt request signal transmit interrupt transmit crc polarity reversing transmit buffer hdlc data transmit interrupt receive interrupt si/o receive buffer register (8bit) receive buffer special communication interrupt tm: time measurement wg: waveform generation polarity reversing receive input register (8bit) receive shit register receive buffer hdlc data process interrupt start bit base timer carry input (note) note 1: ch0 tm register can be used in 32-bit cascade connections. note 2: these pins aren't connected with external pins in 100-pin version. note 3: each register becomes reset status after supplying a clock by setting of the base timer control register 0. (note 2) (note 2) transmit shift register figure 1. 23. 2. block diagram of intelligent i/o group 1
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 238 pwm output control ch0 wg register ch1 wg register ch2 wg register ch3 wg register ch4 wg register ch5 wg register ch6 wg register ch7 wg register 16-bit base timer reset reset request from communication block gr1 base timer reset 2 x (n+1) divider ch0 interrupt request signal f 1 bt2s bts bit modulation pwm bit modulation pwm bit modulation pwm bit modulation pwm bit modulation pwm bit modulation pwm bit modulation pwm bit modulation pwm pwm output control pwm output control outc2 0 /istxd2 pwm output control outc2 1 /isclk2 outc2 2 outc2 3 outc2 4 outc2 5 outc2 6 outc2 7 waveform generation interrupt clock selector serial i/o receive interrupt serial i/o transmit interrupt input inverted receive shift register (8-bit) output control function ie start bit interrupt 8 isclk2 1 isrxd2 1 isrxd2 0 digital filter df 0 1 00 01 ips4,5 real time port output value digital filter df 0 1 0 1 ips6 isclk2 0 10 isrxd2 2 bit counter transmit register (8-bit) transmit buffer register(8-bit) transmit parity operation output inverted arbitration lost detect byte counter ie, serial i/o interrupt control ie receive interrupt ie transmit interrupt 8 ack operation receive parity operation start bit detect receive buffer register (8-bit) id detect all "f" detect address detect statement length detect transmit latch wg: waveform generation note 1: these pins aren't connected with external pins in 100-pin version. note 2: each register becomes reset status after supplying a clock by setting of the base timer control register 0. (note 1) figure 1. 23. 3. block diagram of intelligent i/o group 2
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 239 ch4 mask register ch5 mask register ch6 mask register ch7 mask register pwm output control ch0 wg register ch1 wg register ch2 wg register ch3 wg register ch4 wg register ch5 wg register ch6 wg register ch7 wg register 16-bit base timer reset 2 x (n+1) divider f 1 bt3s bts bit modulation pwm bit modulation pwm bit modulation pwm bit modulation pwm bit modulation pwm bit modulation pwm bit modulation pwm bit modulation pwm pwm output control pwm output control outc3 0 pwm output control outc3 1 outc3 2 outc3 3 outc3 4 outc3 5 outc3 6 outc3 7 waveform generation interrupt 8 real time port output value gr2 base timer reset ch0 interrupt request signal wg: waveform generation note 1: these pins aren t connected with external pins in 100-pin version. note 2: each register becomes reset status after supplying a clock by setting of the base timer control register 0. (note 1) figure 1. 23 . 4. block diagram of intelligent i/o group 3
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 240 group i base timer control register 0 (i=0 to 3) (note) symbol address when reset gibcr0 (i=0 to 3) 00e2 16 , 0122 16 , 0162 16 , 01a2 16 00 16 rw bit name function bit symbol : clock stop : must not be set : must not be set : f 1 b1 0 0 1 1 b0 0 1 0 1 bck0 bck1 div0 count source select bit div1 count source division ratio select bit div2 div3 it base timer interrupt select bit 0 : bit 15 overflow 1 : bit 14 overflow div4 divides the count source by 2x(n + 1) for a setting value n (n = 0 to 31). (n=0) 0 0 0 0 0 : division by 2 (n=1) 0 0 0 0 1 : division by 4 (n=2) 0 0 0 1 0 : division by 6 : (n=30) 1 1 1 1 0 : division by 62 (n=31) 1 1 1 1 1 : no division b6 b5 b4 b3 b2 note: in cascade connections, set the same value to the base timer control register 0 of groups 0 and 1. b7 b0 base timer (group 0 to 3) the internally generated count source is a free run source. base timer specifications are given in table 1.23.2, base timer registers in figures 1.23.5 to 1.23.9 and a block diagram in figure 1.23.10. figure 1. 23. 5. base timer-related register (1) group i base timer register (i=0 to 3) symbol address when reset gibt (i=0,1) 00e1 16 , 00e0 16, 0121 16 , 0120 16 indeterminate gibt (i=2,3) 0161 16 , 0160 16, 01a1 16 , 01a0 16 indeterminate rw function (b7) b0 setting range count value of the 16-bit base timer 0000 16 to ffff 16 (note) note : when this register is read while the base timer is being reset, the value is indeterminate. the counter value is read if the register is output while the timer is running. written value while the base timer is being reset is ignored. the count starts from "0000 16 " after starting the base timer. when writing value while the base timer is operating, the count starts from the written value immediately after written. b8 b15 b7 (b0)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 241 figure 1. 23. 6. base timer-related register (2) group i base timer control register 1 (i=0,1) symbol address when reset gibcr1 (i=0,1) 00e3 16 , 0123 16 00 16 r w bit name function bit symbol b6 0 0 1 1 b5 0 1 0 1 rst0 rst1 rst2 base timer reset cause select bit 0 base timer start bit bts ud0 cas ud1 base timer reset cause select bit 1 base timer reset cause select bit 2 up / down control bit 0: synchronizes the base timer reset without resetting the timer 1: synchronizes the base timer reset with resetting the timer 0: does not reset the base timer when it matches wg register ch0 1: reset the base timer when it matches wg register ch0 0: base timer reset 1: base timer count start : up mode : up / down mode (triangle wave) : two-phase pulse signal processing mode (note 4) : must not be set (note1) groups 0 and 1 cascaded function select bit 0: 16-bit tm / wg function 1: 32-bit tm / wg function (note 5) (note 2) (note 3) 0: does not reset the base timer when input to the int pin is "l" level 1: reset the base timer when input to the int pin is "l" level note 1: with group 0, reset synchronizing with group 1 base timer. with group 1, reset synchronizing with group 0 base timer. note 2: the base timer is reset 2 clock cycles after it matches waveform generation register ch0. note 3: with group 0, the base timer is reset when "l" level is input to int0. with group 1, it resets when "l" level is input to int1. note 4:operation of this mode is equal to timer a two-phase pulse signal processing except count value. note 5: in cascade connections, set to "81 16 " for group 0 base timer control register 1. set to "1000 0xx0 2 " for group 1 base timer control register 1. reserved bit must always set to "0". b7 b0 0
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 242 group 2 base timer control register 1 symbol address when reset g2bcr1 0163 16 00 16 rw bit name function bit symbol note : the base timer is reset 2 clock cycles after it matches waveform generation register ch0. b7 b0 rst0 rst1 rst2 base timer reset cause select bit 0 base timer start bit bts base timer reset cause select bit 1 base timer reset cause select bit 2 0 : synchronizes the group 1 base timer reset without resetting the timer 1 : synchronizes the group 1 base timer reset with resetting the timer 0 : does not reset the base timer when it matches wg register ch0 1 : reset the base timer when it matches wg register ch0 0 : does not reset the base timer when a reset is requested from the communication additional circuit 1 : reset the base timer when a reset is requested from the communication additional circuit must always set to "0". 0 : base timer reset 1 : base timer count start parallel real-time port function select bit prp 0 : not use 1 : use (note) rst3 ud0 ud1 reserve bit reserve bit must always set to "0". 0 0 0 figure 1. 23. 7. base timer-related register (3)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 243 figure 1. 23. 8. base timer-related register (4) group 3 base timer control register 1 symbol address when reset g3bcr1 01a3 16 0xx0 x000 2 rw bit name function bit symbol note : the base timer is reset 2 clock cycles after it matches waveform generation register ch0. b7 b0 rst0 rst1 base timer reset cause select bit 0 base timer start bit bts base timer reset cause select bit 1 0 : synchronizes the base timer 2 reset without resetting the timer 1 : synchronizes the base timer 2 reset with resetting the timer 0 : does not reset the base timer when it matches wg register ch0 1 : reset the base timer when it matches wg register ch0 nothing is assigned. when write, set to "0". when read, the content is indeterminate. 0 : base timer reset 1 : base timer count start parallel real-time port function select bit prp 0 : not use 1 : use (note) wg: waveform generation nothing is assigned. when write, set to "0". when read, their contents are indeterminate. must always set to "0". reserved bit 0
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 244 figure 1. 23. 9. base timer-related register (5) base timer start register (note 1, 2) symbol address when reset bstr 0164 16 xxxx 0000 2 rw bit name function bit symbol nothing is assigned. when write, set "0". when read, their contents are indeterminate. bt0s bt1s bt2s group 0 base timer start bit bt3s 0 : base timer reset 1 : base timer count start 0 : base timer reset 1 : base timer count start 0 : base timer reset 1 : base timer count start 0 : base timer reset 1 : base timer count start group 1 base timer start bit group 2 base timer start bit group 3 base timer start bit (note 2) b7 b0 note 1: when starting multiple base timer with this register at the same time (including group 0 and 1 cascaded connection), do the followings. do not need when starting base timer individually. * set the same values to each group s base timer clock division ratio ( bits 6 to 0 of base timer control register). * when changing base timer clock division ratio, start base timer twice with the following procedure. (1) start each group base timer using the base timer start register. (2) after one clock, stop base timer by setting "00 16 " to base timer start register. (3) further after one clock, restart each group base timer using the base timer start register. note 2: this register is enabled after when group 2 base timer control register 0 is set.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 245 table 1. 23.2. base timer specifications item specifications count source f1/2(n+1) n: set by count source division ratio select bit (n=0 to 31, however, please note when n=31, the counter source is not divided.) count operation up count / down count count start condition writes "1" for the start bit in the base timer start register or base timer control register 1. (after writing the bit, the base timer resets to "0000 16 " and counting starts.) count stop condition writes "0" for both the start bit in the base timer start register and base timer control register 1. count reset condition group 0, 1 (1) synchronizes and resets the base timer with that of another group. group 0: synchronizes base timer reset with the group 1 base timer. group 1: synchronizes base timer reset with the group 0 base timer. (2) matches the value of the base timer to the value of wg register 0. (3) input "l" to int pin group 0 : int 0 pin group 1 : int 1 pin the above 3 factors can be used in conjunction with one another. group 2, 3 (1) synchronizes and resets the base timer with that of another group. group 2: synchronizes base timer reset with the group 1 base timer. group 3: synchronizes base timer reset with the group 2 base timer. (2) matches the value of the base timer to the value of wg register 0. (3) reset request from communication additional circuit (group 2 only) the above 3 factors can be used in conjunction with one another. interrupt request generation timing when bit 14 or bit 15 overflows read from timer ? when the base timer is running the count is output when the base timer is read. ? when the base timer not running an undefined value is output when the base timer is read. write to timer possible. values that are written while the base timer is resetting are ignored. if values are written while the base timer is running, counting continues after the values are written. f 1 2(n+1) divider rst0 rst1 rst2 other base timer reset base timer i b14 b15 overflow signal base timer i interrupt request count source switching select bit interrupt timing select bit reset signal bt0s bts input "l" to int pin matched to waveform generation register 0 (group 0,1) figure 1. 23.10. base timer block diagram
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 246 figure 1. 23.11. operation timing of base timer ffff 16 8000 16 contents of counter 0000 16 b14 (overflow signal) b15 "1" "0" "0" "1"
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 247 figure 1. 23. 12. time measurement-related register (1) time measurement (group 0 and 1) synchronizes external trigger input and stores the base timer value in the time measurement register j. specifications for the time measurement function are given in table 1.23.3, the time measurement control registers in figures 1.23.12 to 1.23.13, and the operating timing of the time measurement function in figure 1.23.14 and 15. group i time measurement control register j (i=0,1/j=0 to 7) (note 1) symbol address when reset gitmcrj(i=0/j=0 to 3) 00d8 16 , 00d9 16 , 00da 16 , 00db 16 00 16 gitmcrj(i=0/j=4 to 7) 00dc 16 , 00dd 16 , 00de 16 , 00df 16 00 16 gitmcrj(i=1/j=1, 2) 0119 16 , 011a 16 00 16 gitmcrj(i=1/j=6, 7) 011e 16 , 011f 16 00 16 rw bit name function bit symbol cst0 cst1 df0 time measurement trigger select bit df1 gate function select bit gt goc pr gsc digital filter function select bit gate function release select bit 0 : gate function not used 1 : gate function used gate function release bit prescaler function select bit b1 0 0 1 1 b0 0 1 0 1 : no time measurement : rising edge : falling edge : both edges b3 0 0 1 1 b2 0 1 0 1 : no digital filter : must not be set : base timer clock : f 1 (note 2, 4) (note 2, 3) (note 2) 0 : no effect 1 : release the gate when it matches wg register 0 : no effect 1 : gate released 0 : not used 1 : used note 1: the 16-bit time measurement function is available for 8 channels (ch0 to 7) with group 0 and 4 channels (ch1, 2, 6 and 7) with group 1. when using the 16-bit time measurement function, use the time measurement register values for ch0, 3, 4 and 5 of group 1 as they are, or, if writing values, write "00 16 ". the 32-bit time measurement function can be used with 8 channels (ch0 to 7) by linking groups 0 and 1. when using the 32-bit time measurement function, write the same value for time measurement registers of similar channels in groups 0 and 1. note 2: these functions are available only for time measurement ch6 and 7 (time measurement registers 6 and 7). for ch0 to 5, set "0" for bits 4 to 7 of the time measurement register. note 3: these bits are valid only when "1" is set for the gate function select bit. note 4: the gate function cannot be used at the same time as the 32-bit time measurement function. (note 2, 3) wg: waveform generation b7 b0
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 248 group i time measurement register j (i=0,1/j=0 to 7) symbol address when reset gitmj(i=0/j=0 to 2) 00c1 16, 00c0 16, 00c3 16, 00c2 16, 00c5 16, 00c4 16 0000 16 gitmj(i=0/j=3 to 5) 00c7 16, 00c6 16, 00c9 16, 00c8 16, 00cb 16, 00ca 16 0000 16 gitmj(i=0/j=6,7) 00cd 16, 00cc 16, 00cf 16, 00ce 16 0000 16 gitmj(i=1/j=0 to 2) 0101 16, 0100 16, 0103 16, 0102 16, 0105 16, 0104 16 0000 16 gitmj(i=1/j=3 to 5) 0107 16, 0106 16, 0109 16, 0108 16, 010b 16, 010a 16 0000 16 gitmj(i=1/j=6,7) 010d 16, 010c 16, 010f 16, 010e 16 0000 16 rw function setting range b15 (b7) b8 (b0) when an event occures, the value of the base timer is stored. b7 b0 group i time measurement prescale register j (i=0,1/j=6,7) symbol address when reset gitprj(i=0/j=6, 7) 00e4 16 , 00e5 16 00 16 gitprj(i=1/j=6, 7) 0124 16 , 0125 16 00 16 rw function setting range prescales time measurement events. (generates the time measurement request after an n + 1 count.) 00 16 to ff 16 (note) note : this function is only built into time measurement ch6 and 7 of intelligent i/o groups 0 and 1. b7 b0 figure 1. 23. 13. time measurement-related register (2) group i function select register (i=0, 1) symbol address when reset gifs (i=0,1) 00e7 16 , 0127 16 00 16 rw bit name bit symbol b7 b0 fsc0 fsc1 fsc2 ch0 tm/wg function select bit fsc3 fsc4 fsc5 fsc7 function fsc6 whether the corresponding port functions as tm or wg is selected 0 : wg function is selected 1 : tm function is selected note : in group 0, channles 2, 3, 6 and 7 cannot be selected in 16-bit mode. all channel can be selected in 32-bit mode. in group 1, channles 0 and 3 to 5 cannot be selected in 16-bit mode. all channel can be selected in 32-bit mode. ch1 tm/wg function select bit ch2 tm/wg function select bit ch3 tm/wg function select bit ch4 tm/wg function select bit ch5 tm/wg function select bit ch6 tm/wg function select bit ch7 tm/wg function select bit
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 249 table 1. 23.3. specifications of time measurement function item specifications time resolution t=1/(base timer count source) trigger input polarity select ? rising edge ? falling edge ? both edges measurement start condition (note) write "1" to the function enable bit measurement stop condition write "0" to the function enable bit time measurement timing ? prescaler (only ch6 and ch7) : every the (m+1) trigger input ? no prescaler : every trigger input interrupt request generation timing same timing as time measurement inpc pin function trigger input pin (set the corresponding pin to input with the function select register) select function ? digital filter function pulses will pass when they match either f 1 or the base timerclock 3 times . ? prescaler function (only for ch6 and ch7) counts trigger inputs and measures time by inputting a trigger of +1 the value of the time measurement prescale register. ? gate function (only for ch6 and ch7) prohibits the reception of trigger inputs after the time measurement starts for the first trigger input. trigger input is newly enabled when the below conditions are satisfied. (1) when the base timer i matches the value in wg register j (2) when 1 is written for the gate function release bit this bit automatically becomes 0 after the gate function is released. note: on channels where both the time measurement function and waveform output function can be used, select the time measurement function for the function select register (addresses 00e7 16 and 0127 16 ). table 1. 23.4. list of time measurement channels with prescaler function and gate function group channel tm register wg register matehes signal to release gate function ch6 tm register 6 base timer 0 matches to wg register 4 group 0 ch7 tm register 7 base timer 0 matches to wg register 5 ch6 tm register 6 base timer 1 matches to wg register 4 group 1 ch7 tm register 7 base timer 1 matches to wg register 5
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 250 figure 1. 23. 14 operation timing of time measurement function delay by 1 clock base timer count source base timer value trigger input time measurement interrupts request signal time measurement register (a) when the rising edge has been selected as the trigger input polarity (b) when both edges have been selected as the trigger input polarity digital filter count source trigger input triggers signal after passing through digital filter trigger signal delayed by digital filter max. 3.5 clock cycles (c) when digital filter is used (count of digital filter) n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n n+5 n+8 n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n n+2 n+5 n+8 n+12 base timer count source base timer value trigger input time measurement interrupts request signal time measurement register signals which do not match 3 times are stripped off
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 251 figure 1. 23. 15. operation timing when gate function and prescaler function is used base timer counter source base timer trigger input time measurement interrupts request signal time measurement register internal time measurement trigger prescaler (a) when prescaler function is used (the value of time measurement prescaler register is "2".) (b) when gate function is used ( gate function released by matching wg register) base timer counter source base timer trigger input internal time measurement trigger function enabled flag waveform generation register match signal gate signal time measurement register time measurement interrupts request signal wg register value (xxxx 16 ) this trigger input is invalid because of gate function. 210 ffff 16 0000 16 n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n+1 n+13 2
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 252 group i waveform generation register j (i=0 to 3/j=0 to 7) symbol address when reset gipoj(i=0/j=0 to 2) 00c1 16, 00c0 16, 00c3 16, 00c2 16, 00c5 16, 00c4 16 xxxx 16 gipoj(i=0/j=3 to 5) 00c7 16, 00c6 16, 00c9 16, 00c8 16, 00cb 16, 00ca 16 xxxx 16 gipoj(i=0/j=6,7) 00cd 16, 00cc 16, 00cf 16, 00ce 16 xxxx 16 gipoj(i=1/j=0 to 2) 0101 16, 0100 16, 0103 16, 0102 16, 0105 16, 0104 16 xxxx 16 gipoj(i=1/j=3 to 5) 0107 16, 0106 16, 0109 16, 0108 16, 010b 16, 010a 16 xxxx 16 gipoj(i=1/j=6,7) 010d 16, 010c 16, 010f 16, 010e 16 xxxx 16 gipoj(i=2/j=0 to 2) 0141 16, 0140 16, 0143 16, 0142 16, 0145 16, 0144 16 xxxx 16 gipoj(i=2/j=3 to 5) 0147 16, 0146 16, 0149 16, 0148 16, 014b 16, 014a 16 xxxx 16 gipoj(i=2/j=6,7) 014d 16, 014c 16, 014f 16, 014e 16 xxxx 16 gipoj(i=3/j=0 to 2) 0181 16, 0180 16, 0183 16, 0182 16, 0185 16, 0184 16 xxxx 16 gipoj(i=3/j=3 to 5) 0187 16, 0186 16, 0189 16, 0188 16, 018b 16, 018a 16 xxxx 16 gipoj(i=3/j=6,7) 018d 16, 018c 16, 018f 16, 018e 16 xxxx 16 rw function setting range b15 (b7) b8 (b0) a compared value for waveform generation is stored. b7 b0 0000 16 to ffff 16 (note) note: when resetting the base timer on ch0, the timer is reset 2 clock cycles after it matches the waveform generation register of ch0. wg: waveform generation group 3 waveform generation mask register j (j=4 to 7) symbol address when reset g3mkj (j=4,5) 0199 16 ,0198 16 , 019b 16 ,019a 16 xxxx 16 g3mkj (j=6,7) 019d 16 ,019c 16 , 019f 16 ,019e 16 xxxx 16 rw function note 1: this function is provided only for the waveform generation functions on ch 4 to 7 of intelligent i/o group 3. note 2: comparison results are masked in bit positions where a "1" has been set for the register bits. b7 b0 setting range masks base timer value 0000 16 to ffff 16 (note 1) (note 2) (b7) (b0) b15 b8 waveform generation (wg) function (group 0 to 3) waveforms are generated when the base timer value matches the value of wg register j. there are five mode in wg function: single phase waveform output mode (group 0 to 3), phase delayed waveform output mode (group 0 to 3), sr (set/reset) waveform output mode (group 0 to 3), bit modulation pwm output mode (group 2 and 3) and parallel real-time port output mode (group 2 and 3). the wg function related registers are shown in figures 1.23.16 to 1.23.19. figure 1. 23. 16. wg-related register (1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 253 group i waveform generation control register j (i=0 to 1/ j=0 to 7) (note 1) symbol address when reset gipocrj (i=0/j=0,1) 00d0 16 , 00d1 16 0x00x000 2 gipocrj (i=0/j=4,5) 00d4 16 , 00d5 16 0x00x000 2 gipocrj (i=1/j=0 to 3) 0110 16 , 0111 16 , 0112 16 , 0113 16 0x00x000 2 gipocrj (i=1/j=4 to 7) 0114 16 , 0115 16 , 0116 16 , 0117 16 0x00x000 2 rw bit name function bit symbol mod0 mod1 mod2 operation mode select bit output initial value select bit ivl rld inv 0: outputs "0" as the initial value 1: outputs "1" as the initial value inverted output function select bit b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 : single pwm mode : s-r pwm mode : phase delayed pwm mode : must not be set : must not be set : must not be set : must not be set : assigns communication output to a port 0: reloads a new count when cpu writes the count 1: reloads a new count when the base timer i is reset 0: output is not inverted 1: output is inverted b2 0 0 0 0 1 1 1 1 must always set to "0" when read, the value of this bit is indeterminate. reload timing select bit (note 3) (note 4) (note 5) must always set "0" when read, the value of this bit is indeterminate. (note 2) note 1: group 0 and 1 have 16-bit wg function and 32-bit wg function. the 16-bit wg function is available for 4 channels (ch=0,1,4,5) with group 0 and 8 channels (ch=0 to 7) with group 1. when using the 16-bit wg function, use the wg register values for ch2, 3, 6 and 7 of group 0 as they are, or, if writing values, write "00 16 ". the 32-bit wg function can be used with 8 channels (ch0 to 7) by linking groups 0 and 1. when using the 32-bit wg function, write the same value for wg registers of similar channels in groups 0 and 1. note 2: this setting is valid only on even-numbered channels. when this mode is selected, settings for corresponding odd-numbered (even number + 1) channels are ignored. waveforms are output for even-numbered channels, not output for odd-numbered channels. note 3: when receiving in uart mode of group 0 and 1, group i wg control register 2 is set to be "00000110 2 ". note 4: this setting is valid only for wg function ch0 and 1. do not set this value for other channels. note 5: inverted output function is allocated at the final stage of wg circuit. therefore, when selecting b7 b0 figure 1. 23. 17. wg-related register (2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 254 group i function enable register (i=0 to 3) symbol address when reset gife (i=0 to 3) 00e6 16 , 0126 16 , 0166 16 , 01a6 16 00 16 b7 b0 rw bit name bit symbol ife0 ife1 ife2 ch0 function enable bit ife3 ife4 ife5 ife7 function ife6 whether the corresponding port functions is selected 0 : disables function on ch i 1 : enables function on ch i ch1 function enable bit ch2 function enable bit ch3 function enable bit ch4 function enable bit ch5 function enable bit ch6 function enable bit ch7 function enable bit figure 1. 23. 18. wg-related register (3) group i waveform generation control register j (i=2 to 3/ j=0 to 7) symbol address when reset gipocrj (i=2/j=0 to 3) 0150 16 , 0151 16 , 0152 16 , 0153 16 0x00 x000 2 gipocrj (i=2/j=4 to 7) 0154 16 , 0155 16 , 0156 16 , 0157 16 0x00 x000 2 gipocrj (i=3/j=0 to 3) 0190 16 , 0191 16 , 0192 16 , 0193 16 0x00 x000 2 gipocrj (i=3/j=4 to 7) 0194 16 , 0195 16 , 0196 16 , 0197 16 0x00 x000 2 rw bit name function bit symbol mod0 mod1 mod2 operation mode select bit output initial value select bit ivl rld inv 0: outputs "0" as the initial value 1: outputs "1" as the initial value parallel rtp output trigger select bit prt 0: match of wg register j isn t trigger 1: match of wg register j is trigger inverted output function select bit b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 : single pwm mode : s-r pwm mode : phase delayed pwm mode : must not be set : bit modulation pwm mode : must not be set : must not be set : assigns communication output to a port 0: reloads a new count when cpu writes the count 1: reloads a new count when the base timer i is reset 0: output is not inverted 1: output is inverted rtp rtp port function select bit 0: not use 1: use b2 0 0 0 0 1 1 1 1 reload timing select bit (note 2) (note 3) (note 1) note 1: this setting is valid only on even-numbered channels. when this mode is selected, settings for corresponding odd-numbered (even number + 1) channels are ignored. waveforms are output for even-numbered channels, not output for odd-numbered channels. note 2: this setting is valid only for group 2 wg function ch0 and 1. do not set this value for other channels. note 3: inverted output function is allocated at the final stage of wg circuit. therefore, when selecting "0" output by ivl bit and inverted output by inv bit, "1" is output. b7 b0
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 255 figure 1. 23. 19. wg-related register (4) group i rtp output buffer register (i=2,3) symbol address when reset girtp (i=2,3) 0167 16 , 01a7 16 00 16 b7 b0 rw bit name bit symbol rtp0 rtp1 rtp2 ch0 rtp output buffer rtp3 rtp4 rtp5 rtp7 function rtp6 the corresponding port's output value is set 0 : output "0" 1 : output "1" ch1 rtp output buffer ch2 rtp output buffer ch3 rtp output buffer ch4 rtp output buffer ch5 rtp output buffer ch6 rtp output buffer ch7 rtp output buffer group i function select register (i=0, 1) symbol address when reset gifs (i=0,1) 00e7 16 , 0127 16 00 16 rw bit name bit symbol b7 b0 fsc0 fsc1 fsc2 ch0 tm/wg function select bit fsc3 fsc4 fsc5 fsc7 function fsc6 whether the corresponding port functions as tm or wg is selected 0 : wg function is selected 1 : tm function is selected note : in group 0, channles 2, 3, 6 and 7 cannot be selected in 16-bit mode. all channel can be selected in 32-bit mode. in group 1, channles 0 and 3 to 5 cannot be selected in 16-bit mode. all channel can be selected in 32-bit mode. ch1 tm/wg function select bit ch2 tm/wg function select bit ch3 tm/wg function select bit ch4 tm/wg function select bit ch5 tm/wg function select bit ch6 tm/wg function select bit ch7 tm/wg function select bit
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 256 (1) single phase waveform output mode (group 0 to 3) this mode is set when the base timer value matches the value of wg register j, and reset when the base timer overflows or the count is reset. specifications for the single phase waveform output mode are given in table 1.23.5 and an operating chart for the single phase waveform output mode in figure 1.23.20. table 1. 23.5. specifications of single phase waveform output mode item specifications output waveform ? when free run operation period : base timer count source x 1/65536 "h" level width : 1/base timer count source x (65536 - m) ? resetting when the base timer matches wg register 0 (ch0) period : base timer count source x 1/(k+2) "h" level width : 1/base timer count source x (k+2-m) m : values set to wg register j k: values set to wg register 0 waveform output start condition write "1" to the function enable bit (note) waveform output stop condition write "0" to the function enable bit interrupt generation timing when the base timer value matches the wg register j outc pin pulse output (corresponding pins are set with the function select register.) read from the wg register 0 the set value is output write to the wg register 0 can always write select function ? initial value setting function sets output level used at waveform output start ? inverted output function inverts waveform output level and outputs the waveform from the outc pin note: on channels where both the time measurement function and waveform output function can be used, select the waveform output function for the function select register (addresses 00e7 16 and 0127 16 ). figure 1. 23. 20. operation timing in single phase waveform output mode base timer xxxa xxxb xxxc xxxd xxxe ffff 0000 0001 count source xxxa xxxb 0000 0001 0002 0003 reset when channel 0 (xxxa 16 ) is matched cleared by software. output waveform when wg register is "xxxa 16 " interrupt request flag "h" "l" "0" "1"
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 257 (2) phase delayed waveform output mode (group 0 to 3) this mode is repeatedly set and reset when the base timer value matches the value of wg register j. specifications for the phase delayed waveform output mode are given in table 1.23.6 and an operation timing in phase delayed waveform output mode in figure 1.23.21. table 1. 23.6. specifications of phase delayed waveform output mode item specifications output waveform ? when free run operation period : base timer count source x 1/65536 x 1/2 "h" and "l" level width : 1/base timer count source x 65536 ? resetting when group i base timer matches wg register 0 (ch0) period : base timer count source x 1/(k+2) x 1/2 "h" and "l" level width : 1/base timer count source x (k+2) k : values set to wg register 0 waveform output start condition write "1" to the function enable bit (note) waveform output stop condition write "0" to the function enable bit interrupt generation timing when the base timer value matches the wg register j outcij pin pulse output (corresponding pins are set with the function select register.) read from the wg register the set value is output write to the wg register can always write select function ? initial value setting function sets output level used at waveform output start ? inverted output function inverts waveform output level and outputs the waveform from the outc pin note : on channels where both the time measurement function and waveform output function can be used, select the waveform output function for the function select register (addresses 00e7 16 and 0127 16 ). figure 1. 23. 21. operation timing in phase delayed waveform output mode xxxa xxxb xxxc ffff 0000 0001 xxxa xxxb xxxc xxxd "h" "l" "0" "1" base timer count source cleared by software. output waveform when wg register is "xxxb 16 " interrupt request flag cleared by software.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 258 (3) sr (set/reset) waveform output mode (group 0 to 3) this mode is set when the base timer value matches the value of wg register j (j is an even-numbered channel), and reset when the base timer matches the wg register (j + 1) or the base timer value is 0 . specifications for the sr waveform output mode are given in table 1.23.7 and an operating chart for the sr waveform output mode in figure 1.23.22. table 1. 23.7. specifications of sr waveform output mode item specifications output waveform ? when free run operation period : base timer count source x 1/65536 "h" level width : 1/base timer count source x (m-p) ? resetting when base timer matches wg register 0 (ch0) period : base timer count source x 1/(k+2) (note 1) "h" level width : 1/base timer count source x (m-p) m : values set to wg register j p : values set to wg register i(j+1) k : values set to wg register 0 (j is an even-numbered channel) (note 2) waveform output start condition write "1" to the function enable bit (note 3) waveform output stop condition write "0" to the function enable bit interrupt generation timing when the base timer value matches the wg register j outc pin (note 4) pulse output (corresponding pins are set with the function select register.) read from the wg register the set value is output write to the wg register can always write select function (note 5) ? initial value setting function sets output level used at waveform output start ? inverted output function inverts waveform output level and outputs the waveform from the outc pin note 1: the sr waveform output function that sets and resets the mode on ch0 and 1 cannot be used when the base timer is reset by wg register 0 (ch0). note 2: set wg register values for odd-numbered channels that are lower than even-numbered channels. note 3: on channels where both the time measurement function and waveform output function can be used, select the waveform output function for the function select register (addresses 00e7 16 and 0127 16 ). note 4: sr waveforms are output for even-numbered channels only. note 5: settings for the wg control register on the odd-numbered channels are ignored.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 259 figure 1. 23. 22. operation timing in sr waveform output mode xxxa xxxb xxxc yyy9 yyya yyyb yyyc "h" "l" "0" "1" "0" "1" base timer count source cleared by software. cleared by software. output waveform when wg register j is "xxxb 16 " and wg register j + 1 is "yyya 16 " channel j interrupt request flag channel j+1 interrupt request flag
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 260 (4) bit modulation pwm output mode (group 2 and 3) this mode performs pwm to improve output resolution. specifications for the bit modulation pwm mode are given in table 1.23.8 and an operating chart for the bit modulation pwm mode in figure 1.23.23. table 1. 23.8. specifications of bit modulation pwm mode item specifications output waveform period : base timer count source x 1/64 "h" level width (avelage) : 1/base timer count source x [k+(m/1024)] k : values set to wg register j (six high-order bits) m : values set to wg register j (ten lower-order bits) waveform output start condition write "1" to the function enable bit waveform output stop condition write "0" to the function enable bit interrupt generation timing when the base timer value matches the wg register j outc pin pulse output (corresponding pins are set with the function select register.) read from the wg register j the set value is output write to the wg register j can always write select function ? initial value setting function sets output level used at waveform output start ? inverted output function inverts waveform output level and outputs the waveform from the outc pin figure 1. 23. 23. operation timing in bit modulation pwm mode a a 00 16 3f 16 aa aa k b15 b10 b9 b0 00 16 3f 16 k+1 k set value k 1024 pulses increases the "l" level width for 1 clock cycle for an m number of pulses out of 1,024 base timer 6 low-order bits sets pwm width k=0 to 63 (3f 16 ) sets bit modulation frequency m=0 to 1023 (3ff 16 ) wg register j set value k internal signal base timer 6 low-order bits base timer count source output waveform output waveform
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 261 (5) real-time port output mode (group 2 and 3) this mode outputs the value set in the real-time port register from the outc pin when the base timer value matches the value of wg register j. specifications for the real-time port output mode are given in table 1.23.9 and a block diagram and timing chart of the real-time port output function in figure 1.23.24. table 1. 23.9. specifications of real-time port output mode item specifications waveform output start condition write "1" to the function enable bit waveform output stop condition write "0" to the function enable bit interrupt generation timing when the base timer value matches the wg register j outc pin rtp output (corresponding pins are set with the function select register.) read from the wg register j the set value is output write to the wg register j can always write read from the rtp output buffer register the set value is output write to the rtp output buffer register can always write select function ? initial value setting function sets output level used at waveform output start ? inverted output function inverts waveform output level and outputs the waveform from the outc pin base timer output waveform xxx5 xxx6 xxx7 xxx8 xxx9 xxxa xxxb xxxc xxxd xxxe xxxf count source when wg register j = "xxx8 16 " and bit j of rtp output buffer register = "1" (previous value is 0) channel i interrupt request flag cleared by software. "h" "l" "0" "1" aaa aaa aaa aaa aaa aaa wg register 0 base timer dq t bit0 bit6 bit7 dq t dq t wg register 6 wg register 7 rtp output outci 0 outci 6 outci 7 rtp output buffer register (i=2, 3 ) figure 1. 23. 24. block diagram and operation timing of real-time port output function
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 262 (6) parallel real-time port output mode (group 2 and 3) this mode outputs the value set in the real-time port register from the outc pin when the base timer value matches the value of wg register j. specifications for the parallel real-time port output mode are given in table 1.23.10 and a block diagram and timing chart of the real-time port output function in figure 1.23.25. table 1. 23.10. specifications of parallel real-time port output mode item specifications waveform output start condition write "1" to the function enable bit waveform output stop condition write "0" to the function enable bit interrupt generation timing when the base timer value matches the wg register outc pin rtp output (corresponding pins are set with the function select register.) read from the wg register the set value is output write to the wg register can always write read from the rtp output buffer register the set value is output write to the rtp output buffer register can always write select function ? initial value setting function sets output level used at waveform output start ? inverted output function inverts waveform output level and outputs the waveform from the outc pin
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o 263 aa aa aa aa aa aa aa aa aa aa aa dq t bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 dq t dq t dq t dq t dq t dq t dq t real-time port output real-time port output buffer register wg register 0 base timer wg register 1 wg register 2 wg register 3 wg register 4 wg register 5 wg register 6 wg register 7 outci 0 outci 1 outci 2 outci 3 outci 4 outci 5 outci 6 outci 7 (i=2, 3) xxx1 xxx2 xxx3 xxx4 xxx5 xxx6 xxx7 xxxc xxxd xxxe xxxf "h" "l" "h" "l" "h" "l" "0" "1" "0" "1" "0" "1" base timer output waveform outci0 output waveform outci1 output waveform outci7 count source when wg register j = "xxx1 16 " rtp output buffer register = "0xxx xx01 2 " wg register j + 1 = "xxx5 16 " rtp output buffer register = "1xxx xx10 2 " (this value is saved to rtp output buffer register as channel j interrupt request trigger) wg register j + 2 = "xxxc 16 " rtp output buffer register = "1xxx xx11 2 " (this value is saved to rtp output buffer register as channel j+1 interrupt request trigger) channel j interrupt request flag channel j+1 interrupt request flag channel j+2 interrupt request flag cleared by software. cleared by software. cleared by software. figure 1. 23. 25. block diagram and operation timing of parallel real-time port output function
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 264 serial i/o (group 0 to 2) intelligent i/o groups 0 to 2 each have two internal 8-bit shift registers. when used in conjunction with the time measurement (tm) function or wg function, these shift registers enable clock synchronous/asyn- chronous serial communications. (1) clock synchronous serial i/o mode (group 0, 1) intelligent i/o groups 0 and 1 each have communication block that have two internal 8-bit shift registers. when used in conjunction with the communication block and wg function, these shift registers enable 8-bit clock synchronous and hdlc data process function. when used in conjunction with the communi- cation block, tm function and wg function, these shift registers enable 8-bit clock asynchronous com- munication. table 1.23.11 lists using registers in group 0 and 1, figure 1.23.26 to 1.23.29 shows the related regis- ters. table 1.23.11. using registers in group 0 and 1 clock synchronous serial i/o uart hdlc base timer control register 0 ?? base timer control register 1 ?? time measument control register 2 C C waveform generate control register 0 ?? waveform generate control register 1 CC waveform generate control register 2 ? C waveform generate control register 3 ? C waveform generate register 0 ?? waveform generate register 1 C time measument /waveform generate register 2 ? C waveform generate register 3 ? C function select register ?? function enable register ?? si/o communication mode register ?? si/o extended mode register CC si/o communication control register ?? si/o extended transmit control register CC si/o extended receive control register CC si/o special communication interrupt detect register CC si/o receive buffer register ?? transmit buffer ?? (receive data register ) CC data compare register j (j=0 to 3) CC data mask register j (j=0, 1) CC transmit crc code register CC receive crc code register CC transmit output register CC receive input register CC : use C : not use
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 265 figure 1. 23. 26. group 0 and 1 related register (1) group i receive input register (i=0,1) symbol address when reset giri (i=0, 1) 00ec 16 , 012c 16 indeterminate rw function setting range b7 b0 data that is input to the receive data process unit 00 16 to ff 16 group i transmit output register (i=0,1) symbol address when reset gito (i=0, 1) 00ee 16 , 012e 16 indeterminate rw function setting range b7 b0 data that is output from the transmit data process unit group i si/o communication control register (i=0,1) symbol address when reset gicr (i=0,1) 00ef 16 , 012f 16 0000 x000 2 rw bit name function bit symbol nothing is assigned. when write, set to "0". when read, the contents is indeterminate. b7 b0 ti txept ri transmit buffer empty flag te re ipol opol receive complete flag transmit enable bit receive enable bit rxd input polarity reverse select bit txd output polarity reverse select bit 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : transmission disabled 1 : transmission enabled 0 : reception disabled 1 : reception enabled 0 : no reverse (usually set to "0") 1 : reverse transmit register empty flag 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : no reverse (usually set to "0") 1 : reverse (note) (note) note :this bit is set to "1" in uart mode.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 266 figure 1. 23. 27. group 0 and 1 related register (2) group i si/o communication mode register (i=0,1) symbol address when reset gimr (i=0,1) 00ed 16 , 012d 16 00 16 rw bit name function bit symbol note 1: can be used only in the uart mode. note 2: select a pin for clock output by setting the waveform generation control register, input function select register, and function select registers a, b and c. data transmission pins are the same as clock output pins. note 3: select which pins will input the clock with the input function select register and set those pins to the input port using function select register a. data input pins are the same as with clock input pins. b7 b0 gmd0 gmd1 ckdir communication mode select bit stps pry prye uform irs internal/external clock select bit stop bit length select bit odd/even parity select bit parity enable select bit transfer direction select bit transmit interrupt cause select bit 0 : internal clock 1 : external clock 0 : 1 stop bit 1 : 2 stop bits 0 : odd parity 1 : even parity 0 : parity disabled 1 : parity enabled 0 : lsb first 1 : msb first 0 : transmit buffer is empty 1 : transmit is completed : uart mode : serial i/o mode : special communication mode : hdlc data process mode b1 0 0 1 1 b0 0 1 0 1 (note 1) (note 1) (note 1) (note 2) (note 3) function group i si/o receive buffer register (i=0,1) bit name bit symbol symbol address when reset gibf(i=0,1) 00e9 16, 00e8 16, 0129 16, 0128 16 indeterminate rw note: only effective for receive data. fer receive data per 0 : no parity error 1 : parity error found oer 0 : no overrun error 1 : overrun error found nothing is assigned. when read, their value are indeterminate. nothing is assigned. when read, its value is indeterminate. (note) framing error flag 0 : no framing error 1 : framing error found parity error flag (note) overrun error flag (note) receive buffer b7 b0 b15 (b7) b14 (b6) b13 (b5) b12 (b4) b11 (b3) b10 (b2) b9 (b1) b8 (b0)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 267 figure 1. 23. 28. group 0 and 1 related register (3) group i si/o expansion mode register (i=0,1) (note 1) symbol address when reset giemr (i=0,1) 00fc 16 , 013c 16 00 16 rw bit name function bit symbol note 1: other than when in the special communication mode or hdlc data process mode, either use the reset state as is or write "00 16 ". note 2: initialized when the data compare register matches. b7 b0 smode crcv acrc bsint rxsl txsl crc0 crc1 synchronous mode select bit reception source select bit transmission source select bit 0 : not initialize 1 : initialize 0 : not use 1 : use 0 : rxd pin 1 : receive input register 0 : txd pin 1 : transmit output register 0 : normal mode 1 : resynchronous mode crc initial value select bit 0 : "0000 16 " is set 1 : "ffff 16 " is set crc initialization select bit bit stuffing error interrupt select bit crc polynomial select bit : x 8 +x 4 +x+1 : must not be set : x 16 +x 15 +x 2 +1 : x 16 +x 12 +x 5 +1 b7 0 0 1 1 b6 0 1 0 1 (note 2) group i si/o expansion transmit control register (i=0,1) (note) symbol address when reset gietc (i=0,1) 00ff 16 , 013f 16 00000xxx 2 rw bit name function bit symbol note : other than when in the special communication mode or hdlc data processing mode, either use the reset state as is or write "00 16 ". nothing is assigned. when write, set "0". when read, their contents are indeterminate. b7 b0 sof tcrce abte tbsf0 tbsf1 transmit crc enable bit arbitration enable bit transmit bit stuffing "1" insert select bit 0 : not use 1 : use 0 : not use 1 : use sof transmit request bit 0 : no sof transmit request 1 : sof transmit request transmit bit stuffing "0" insert select bit 0 : "1" is not inserted 1 : "1" is inserted 0 : "0" is not inserted 1 : "0" is inserted
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 268 figure 1. 23. 29. group 0 and 1 related register (4) group i special communication interrupt detect register (i=0,1) (note) symbol address when reset giirf (i=0,1) 00fe 16 , 013e 16 0000 00xx 2 rw bit name function bit symbol note : other than when in the special communication mode or hdlc data processing mode, either use the reset state as is or write "00 16 ". nothing is assigned. when write, set "0". when read, their contents are indeterminate. b7 b0 abt bserr arbitration lost detecting flag bit stuffing error detecting flag 0 : not detected 1 : detected 0 : not detected 1 : detected irf0 irf1 irf2 interrupt cause determination flag 0 irf3 0 : received data does not match data compare register 0 1 : received data matches data compare register 0 interrupt cause determination flag 1 interrupt cause determination flag 2 interrupt cause determination flag 3 0 : received data does not match data compare register 1 1 : received data matches data compare register 1 0 : received data does not match data compare register 2 1 : received data matches data compare register 2 0 : received data does not match data compare register 3 1 : received data matches data compare register 3 group i si/o expansion receive control register (i=0,1) (note 1) symbol address when reset gierc (i=0,1) 00fd 16 , 013d 16 00 16 rw bit name function bit symbol note 1: other than when in the special communication mode or hdlc data processing mode, either use the reset state as is or write "00 16 ". note 2: to use the crc initialization function (when bit 2 of si/o expansion mode register is set to "1"), set bit 3 to "1". b7 b0 cmp0e cmp1e cmp2e data compare function 0 select bit cmp3e rcrce rshte rbsf0 rbsf1 receive crc enable bit receive shift operation enable bit 0 : not enable 1 : enable 0 : receive shift operation disabled 1 : receive shift operation enabled 0 : does not compare the received data with data compare register 0 1 : compare the received data with data compare register 0 data compare function 1 select bit data compare function 2 select bit data compare function 3 select bit receive bit stuffing "1" delete select bit receive bit stuffing "1" delete select bit 0 : "1" is not deleted 1 : "1" is deleted 0 : "0" is not deleted 1 : "0" is deleted 0 : does not compare the received data with data compare register 1 1 : compare the received data with data compare register 1 0 : does not compare the received data with data compare register 2 1 : compare the received data with data compare register 2 0 : does not compare the received data with data compare register 3 1 : compare the received data with data compare register 3 (note 2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 269 figure 1. 23. 30. group 0 and 1 related register (5) group i transmit buffer/receive data register (i=0,1) symbol address when reset gidr (i=0,1) 00ea 16 , 012a 16 indeterminate rw function setting range b7 b0 transmit data for data compare is stored receive data for data compare is stored group i data compare register j (i=0,1/j=0 to 3) symbol address when reset gicmpj (i=0/j=o to 3) 00f0 16 , 00f1 16 , 00f2 16 , 00f3 16 indeterminate gicmpj (i=1/j=o to 3) 0130 16 , 0131 16 , 0132 16 , 0133 16 indeterminate rw function setting range b7 b0 compare data 00 16 to ff 16 note : when using the data compare registers 0 and 1, the data mask registers 0 and 1 must be set. group i data mask register j (i=0,1/j=0,1) symbol address when reset gimskj (i=0/j=0, 1) 00f4 16 , 00f5 16 indeterminate gimskj (i=1/j=0, 1) 0134 16 , 0135 16 indeterminate rw function setting range b7 b0 mask data for receive data (masked by "1") 00 16 to ff 16 group i transmit crc code register (i=0,1) symbol address when reset gitcrc (i=0, 1) 00fb 16 ,00fa 16 , 013b 16 , 013a 16 0000 16 rw function setting range (b7) b0 transmit crc calculation results (note) note : computed results are initialized when the transmit crc enable bit (bit 4 of group i expanded transmit control register) is set to "0". b7 (b0) b15 b8 group i receive crc code register (i=0,1) symbol address when reset gircrc (i=0, 1) 00f9 16 ,00f8 16 , 0139 16 , 0138 16 0000 16 rw function setting range (b7) b0 receive crc calculation results b7 (b0) b15 b8 note 1: computed results are initialized when the receive crc enable bit (bit 4 of group i expanded reseive control register) is set to "0", or when the crc initialization bit (bit 2 of group i si/o expansion mode register) is set to "1" and values match the data comparison register. note 2: initialize to selected value when starting to receive.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 270 interrupt request generation timing clock synchronous serial i/o mode (group 0 and 1) table 1.23.12 gives specifications for the clock synchronous serial i/o mode. table 1.23.12. specifications of clock synchronous serial i/o mode (group 0 and 1) item specification transfer data format ? transfer data length: 8 bits fixed transfer clock ? when internal clock is selected _ transfer speed is determined when the base timer is reset by the ch0 wg function transfer rate (bps) = base timer count source (frequency) / (k+2) / 2 k : values set to wg register 0 _ transfer clock is generated when the transfer clock in the phase delayed waveform output mode transmit clock : ch3 wg function receive clock : ch2 wg function sets the same value in the wg registers on ch2 and ch3 ? when external clock is selected _ transfer rate (bps) = clock input to isclk pin transmission start condition to start transmission, the following requirements must be met: ? transmit enable bit = 1 ? write data to transmit buffer reception start condition to start reception, the following requirements must be met: ? receive enable bit = 1 ? when transmitting _ when transmit buffer is empty, transmit interrupt cause select bit = 0 _ when transmission is completed, transmit interrupt cause select bit = 1 ? when receiving when data is transferred to si/o receive buffer register error detection ? overrun error this error occurs when the next data is ready before the contents of si/o receive buffer register are read out select function ? lsb first/msb first selection when transmission/reception begins with bit 0 or bit 7, it can be selected ? transmit/receive data polarity switching this function is reversing istxd pin output and isrxd pin input. (all i/o data level is reversed.) note: set the transmission clock to at least 6 divisions of the base timer clock. table 1.23.13 lists i/o pin functions for the clock synchronous serial i/o mode of groups 0 and 1. from when the operating mode is selected until transmission starts, the istxdi pin is "h" level. figure 1.23.31 shows typical transmit/receive timings in clock synchronous serial i/o mode in group 0 and 1.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 271 figure 1.23.31. typical transmit/receive timings in clock synchronous serial i/o mode in group 0 and 1 table 1.23.13. i/o pin functions in clock synchronous serial i/o mode of group 0, group 1 pin name function selected method istxd serial data output ? use the ch0 wg function (p7 6 , p15 0 , p7 3 , p11 0 ) ? sets "111" for the operating mode select bit (bits 2, 1 and 0) in wg control register 0 ? selects istxd output for the port using function select registers a, b and c isrxd serial data input ? selects a using port with input function select register (p8 0 , p15 2 , p7 5 , p11 2 ) ? selects i/o with function select register a ? sets a selected port to input using the port direction register isclk transfer clock output ? use the ch1 wg function (p7 7 , p15 1 , p7 4 , p11 1 ) ? sets "111" for the operating mode select bit (bits 2, 1 and 0) in wg control register 1 ? sets "0" for the internal/external clock select bit (bit 2) of the si/o communication mode register ? selects isclk output for the port using function select registers a, b and c transfer clock input ? selects a using port with input function select register ? sets "1" for the internal/external clock select bit (bit 2) of the si/o communication mode register ? sets a selected port to input using the port direction register ? selects i/o port with function select register a t t base timer receive data base timer resets using ch0 wg function (input to inpci 2 /isrxd i pin (i=0,1)) receive clock using ch2 wg function transmit data transmit clock using ch3 wg function bit 1 bit 2 bit 6 bit 7 bit 0 write to transmit buffer t: transfer rate/2 bit 1 bit 6 bit 7 t : values set to ch2 wg register values set to ch3 wg register bit 0
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 272 interrupt request generation timing (2) clock asynchronous serial i/o mode (uart) (group 0 and 1) table 1.23.14 lists the specifications for the uart mode. table 1.23.14. specifications of uart mode item specification transfer data format ? character bit (transfer data) : 8 bits ? start bit : 1 bit ? parity bit : odd, even, or nothing selected ? stop bit : 1 bit or 2 bits selected transfer clock ? when internal clock is selected (generates the transmit/receive clock in the phase delayed waveform output mode) _ transfer speed is determined when the base timer is reset by the ch0 wg function transfer rate (bps) = base timer count source (frequency) / (k+2) / 2 k : values set to wg register 0 _ transfer clock is generated when the transfer clock in the phase delayed waveform output mode transmit clock : ch3 wg function receive clock : change ch2 tm function to wg function detects falling edge of start bit changes to the wg mode when the time measurement interrupt arrives ? when external clock is selected _ transfer rate (bps) = clock input to isclk pin transmission start condition to start transmission, the following requirements must be met: ? transmit enable bit = 1 ? write data to transmit buffer reception start condition to start reception, the following requirements must be met: ? receive enable bit = 1 ? when transmitting _ when transmit buffer is empty, transmit interrupt cause select bit = 0 _ when transmission is completed, transmit interrupt cause select bit = 1 ? when receiving _ when data is transferred to si/o receive buffer register error detection ? overrun error : this error occurs when the next data is ready before contents of si/o receive buffer register are read out ? framing error : this error occurs when the number of stop bits set is not detected ? parity error : this error occurs when if parity is enabled, the number of 1 s in parity and character bits does not match the number of 1 s set select function ? stop bit length : stop bit length can be selected as 1 bit or 2 bits ? parity : parity can be turned on/off : when parity is on, odd/even parity can be selected ? lsb first/msb first selection : whether transmit/receive begins with bit 0 or bit 7 can be selected ? transmit/receive data polarity switching : this function is reversing istxd port output and isrxd port input. (all i/o data level are reversed.) ? data transfer bit length : transmission data length can be set between 1 to 8 bits
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 273 figure 1.23.32. typical transmit timings in uart mode figure 1.23.33. typical receive timing in uart mode txd, rxd i/o polarity reverse function this function is to reverse txd pin output and rxd pin input. the level of any data to be input or output (including the start bit, stop bit(s), and parity bit) are reversed. txd output polarity reverse select bit is set to 0 (not to reverse) for usual use. k + 2 t base timer transmit data base timer resets using ch0 wg function transmit clock using ch3 wg function t : values set to ch3 wg register write to transmit buffer start bit bit 0 bit 7 parity stop bit (1 bit) k+2 t base timer receive data base timer resets using ch0 wg function (input to inpci 2 /isrxd i pin (i=0,1)) receive clock using ch2 wg function interrupt request signal start bit bit 0 bit 7 parity stop bit (1 bit) t : values set to ch2 wg register reception completed interrupt request
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 274 (2) clock synchronous serial i/o mode (group 2) intelligent i/o groups 2 has communication block that have two internal 8-bit shift registers. when used in conjunction with the communication block and wg function, these shift registers enable variable clock synchronous and ie bus (note) communications. table 1.23.16 lists using registers in group 2, figure 1.23.34 to 1.23.37 shows the related registers. note : ie bus is a trademark of nec corporation. table 1.23.16. using registers in group 2 clock synchronous serial i/o ie bus base timer control register 0 ? base timer control register 1 ? waveform generate control register 0 ? waveform generate control register 1 C waveform generate control register 2 ? waveform generate control register 3 C waveform generate control register 4 C (note 1) waveform generate control register 5 C waveform generate control register 6 C waveform generate control register 7 C waveform generate register 0 ? waveform generate register 1 C waveform generate register 2 ? waveform generate register 3 C waveform generate register 4 C waveform generate register 5 C waveform generate register 6 C waveform generate register 7 C function enable register ? si/o communication mode register ? si/o communication control register ? ie bus control register C ie bus address register C ie bus transmit interrupt cause detect register C ie bus receive interrupt cause detect register C si/o receive buffer register ? si/o transmit buffer register ? : use C : not use note 1: when receiving slave, set corresponding value with 32.5 s. don't set 170 s.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 275 function group 2 si/o transmit buffer register bit name bit symbol symbol address when reset g2tb 016d 16 , 016c 16 indeterminate rw sz0 sz2 sz1 b7 b0 b15 (b7) b14 (b6) b13 (b5) b12 (b4) b11 (b3) b10 (b2) b9 (b1) b8 (b0) transfer bit length select bit transmit buffer transmit data b9 0 0 1 1 0 0 1 1 b8 0 1 0 1 0 1 0 1 : 8-bit long : 1-bit long : 2-bit long : 3-bit long : 4-bit long : 5-bit long : 6-bit long : 7-bit long b10 0 0 0 0 1 1 1 1 a pc p ack function select bit nothing is assigned. when write, set "0". when read, their contents are indeterminate. parity operation continuing bit parity function select bit 0 : no function 1 : adds an ack bit after the final transmission bit 0 : adds the parity bit after the transmitted data 1 : repeats the parity check with the next transmission 0 : no parity 1 : parity (only even parity) note: when this bit is set to "1", set the parity function select bit to "0". (note) function group 2 si/o receive buffer register bit name bit symbol symbol address when reset g2rb 016f 16 , 016e 16 indeterminate rw note : this bit is automatically set to "0" when communication unit reset is selected for the communication mode select bit and the reception enable bit is set to "0". receive data oer 0 : no overrun error 1 : overrun error found nothing is assigned. when write, set "0". when read, their contents are indeterminate. nothing is assigned. when write, set "0". when read, their contents are indeterminate. receive buffer overrun error flag (note) b7 b0 b15 (b7) b14 (b6) b13 (b5) b12 (b4) b11 (b3) b10 (b2) b9 (b1) b8 (b0) figure 1. 23. 34. group 2 intelligent i/o-related register (1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 276 group 2 ie bus control register symbol address when reset iecr 0172 16 00xxx000 2 rw bit name function bit symbol nothing is assigned. when write, set "0". when read, their contents are indeterminate. b7 b0 0 : idle state 1 : busy state (start condition detected) ieb iets iebbs ie bus enable bit df ie bus transmit start request bit digital filter select bit 0 : transmit completed 1 : transmit start 0 : ie bus disabled 1 : ie bus enabled 0 : no digital filter 1 : digital filter iem ie bus busy flag ie bus mode select bit 0 : mode 1 1 : mode 2 (note) note :when this bit is set to "0", hold "0" for at least 1 cycle of base timer . group 2 ie bus address register symbol address when reset iear 0171 16 , 0170 16 indeterminate rw function b7 b0 address data nothing is assigned. when write, set "0". when read, their contents are indeterminate. address data (b7)(b6)(b5)(b4)(b3)(b2)(b1)(b0) b15 b14 b13 b12 b11 b10 b9 b8 figure 1. 23. 35. group 2 intelligent i/o-related register (2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 277 figure 1. 23. 36. group 2 intelligent i/o-related register (3) group 2 ie bus transmit interrupt cause determination register symbol address when reset ietif 0173 16 xxx00000 2 rw bit name function bit symbol note : only "0" can be written for this bit. also, it is cleared to "0" when "0" is written for bit 0 of the ie bus control register. at this time, hold "0" for at least 1 cycle of base timer clock. nothing is assigned. when write, set "0". when read, their contents are indeterminate. b7 b0 (note) ietnf ieack ietmb normal termination flag iett ieabl ack error flag arbitration lost flag 0 : no error 1 : error found 0 : terminated in error 1 : terminated normally max. transfer byte error flag timing error flag 0 : no error 1 : error found 0 : no error 1 : error found 0 : no error 1 : error found (note) (note) (note) (note) group 2 ie bus receive interrupt cause determination register symbol address when reset ierif 0174 16 xxx00000 2 rw bit name function bit symbol note : only "0" can be written for this bit. also, it is cleared to "0" when "0" is written for bit 0 of the ie bus control register. at this time, hold "0" for at least 1 cycle of base timer clock. nothing is assigned. when write, set "0". when read, their contents are indeterminate. b7 b0 (note) iernf iepar iermb iert ieretc parity error flag other cause receive completed flag 0 : no error 1 : error found max. transfer byte error flag timing error flag 0 : no error 1 : error found 0 : no error 1 : error found 0 : no error 1 : error found (note) (note) (note) (note) normal termination flag 0 : terminated in error 1 : terminated normally
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 278 figure 1. 23. 37. group 2 intelligent i/o-related register (4) b7 b0 gmd0 gmd1 ckdir communication mode select bit uform irs internal/external clock select bit transfer direction select bit transmit interrupt cause select bit 0 : internal clock 1 : external clock 0 : lsb first 1 : msb first 0 : transmit buffer is empty 1 : transmit is completed : communication part is reset (overrun error flag is cleared) : serial i/o mode : special communication mode : hdlc data process mode b1 0 0 1 1 b0 0 1 0 1 (note 2) (note 3) group 2 si/o communication mode register symbol address when reset g2mr 016a 16 00xxx000 2 rw bit name function bit symbol note 1: intelligent i/o group 2 has ie bus communication function as special communication function. note 2: select a pin for clock output by setting the waveform generation control register, input function select register, and function select registers a, b and c. data transmission pins are the same as clock output pins. note 3: select which pins will input the clock with the input function select register and set those pins to the input port using function select register a. data input pins are the same as with clock input pins. nothing is assigned. when write, set "0". when read, their contents are indeterminate. group 2 si/o communication control register symbol address when reset g2cr 016b 16 0000 x000 2 rw bit name function bit symbol nothing is assigned. when write, set to "0". when read, the contents is indeterminate. b7 b0 te txept ri transmit enable bit ti re ipol opol receive complete flag transmit buffer empty flag receive enable bit rxd input polarity reverse select bit txd output polarity reverse select bit 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no reverse (usually set to "0") 1 : reverse transmit register empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : no reverse (usually set to "0") 1 : reverse
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 279 clock synchronous serial i/o mode (group 2) table 1.23.17 gives specifications for the group 2 clock synchronous serial i/o mode. table 1.23.17. specifications of clock synchronous serial i/o mode item specification transfer data format ? transfer data length: variable length (group2) transfer clock ? when internal clock is selected, the transfer clock in the single waveform output mode is generated. _ transfer speed is determined when the base timer is reset by the ch0 wg function transfer rate (bps) = base timer count source (frequency) / (k+2) k : values set to wg register 0 _ transfer clock is generated by ch2 single phase wg function ch3 wg register = (k+2)/2 (note 1) ? when external clock is selected _ transfer rate (bps) = clock input to isclk pin (note 2) transmission start condition ? to start transmission, the following requirements must be met: _ transmit enable bit = 1 _ write data to si/o transmit buffer register reception start condition ? to start reception, the following requirements must be met: _ receive enable bit = 1 _ transmit enable bit = 1 _ write data to si/o transmit buffer register ? when transmitting _ when si/o communication buffer register is empty, transmit interrupt cause select bit = 0 _ when transmission is completed, transmit interrupt cause select bit = 1 ? when receiving _ when data is transferred to si/o receive buffer register error detection ? overrun error this error occurs when the next data is ready before the contents of si/o receive buffer register are read out select function ? lsb first/msb first selection when transmission/reception begins with bit 0 or bit 7, it can be selected. ? transmit/receive data polarity switching _ this function is reversing istxd pin output and isrxd pin input. (all i/o data level is reversed.) ? data transfer bit length _ transmission data length can be set between 1 to 8 bits note 1: when the transfer clock and transfer data are transmission, transfer clock is set to at least 6 divi- sions of the base timer clock. except this, transfer clock is set to at least 20 divisions of the base timer clock. note 2: transfer clock is set to at least 20 divisions of the base timer clock. interrupt request generation timing
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer intelligent i/o (serial i/o) 280 k + 2 t base timer second writing to the transmit buffer receive data writes data to the transmit register (8 bits) bit 0 bit 1 bit 2 bit 7 bit 6 bit 8 bit 9 bit 10 bit 11 bit 0 bit 1 bit 2 bit 7 bit 6 bit 8 bit 9 bit 10 bit 11 bit 5 writes data to the transmit register (4 bits) transfer to the receive register transfer to the receive register first writing to the transmit buffer base timer resets using ch0 wg function transmit/receive clock using ch2 wg function t : values set to ch2 wg register values set to ch3 wg register figure 1. 23. 38. typical transmit/receive timings in clock synchronous serial i/o mode in group 2
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 281 a-d converter the a-d converter consists of two 10-bit successive approximation a-d converter circuit with a capacitive coupling amplifier. pins p10 0 to p10 7 , p15 0 to p15 7 , p0 0 to p0 7 , p2 0 to p2 7 , p9 5 , and p9 6 are shared as the analog signal input pins. pins p15 0 to p15 7 , p0 0 to p0 7 and p2 0 to p2 7 can be used as the analog signal input pins and switched by analog input port select bit. however, p0 0 to p0 7 and p2 0 to p2 7 can be used in single chip mode. set input to direction register corresponding to a pin doing a-d conversion. the result of a-d conversion is stored in the a-d registers of the selected pins. table 1.24.1 shows the performance of the a-d converter. figure 1.24.1 shows the block diagram of the a-d converter, and figures 1.24.2 to 1.24.7 show the a-d converter-related registers. this section is described to 144-pin version as example. in 100-pin version, an1 0 to an1 7 cannot be selected because there is no p15.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 282 a-d1 register 0 a-d1 register 1 a-d1 register 2 a-d1 register 3 a-d1 register 4 a-d1 register 5 a-d1 register 6 a-d1 register 7 decoder (01c1 16 , 01c0 16 ) (01c3 16 , 01c2 16 ) (01c5 16 , 01c4 16 ) (01c7 16 , 01c6 16 ) (01c9 16 , 01c8 16 ) (01cb 16 , 01ca 16 ) (01cd 16 , 01cc 16 ) (01cf 16 , 01ce 16 ) ad1 control register 0 (address 01d6 16 ) 000 an 0 001 an 1 010 an 2 011 an 3 100 an 4 an 5 101 110 an 6 111 an 7 000 an2 0 001 an2 1 010 an2 2 011 an2 3 100 an2 4 an2 5 101 110 an2 6 111 an2 7 000 an15 0 001 an15 1 010 an15 2 011 an15 3 100 an15 4 an15 5 101 110 an15 6 111 an15 7 a-d0 register 0 a-d0 register 1 a-d0 register 2 a-d0 register 3 a-d0 register 4 a-d0 register 5 a-d0 register 6 a-d0 register 7 decoder (0381 16 , 0380 16 ) (0383 16 , 0382 16 ) (0385 16 , 0384 16 ) (0387 16 , 0386 16 ) (0389 16 , 0388 16 ) (038b 16 , 038a 16 ) (038d 16 , 038c 16 ) (038f 16 , 038e 16 ) 000 an0 0 001 an0 1 010 an0 2 011 an0 3 100 an0 4 an0 5 101 110 an0 6 111 an0 7 successive conversion register resister ladder ad0 control register 0 (address 0396 16 ) ad1 control register 1 (address 01d7 16 ) ad0 control register 1 (address 0397 16 ) 1/3 1/2 1/2 0 1 0 1 0 1 ad1con0 : csk0 ad1con1 : csk1 f ad ? ad1 1/3 1/2 1/2 0 1 0 1 0 1 ad0con0 : csk0 ad0con1 : csk1 f ad ? ad0 anex0 anex1 ad0con1 : opa0, opa1 adicon2 : trg1, trg0 adicon0 : trg ex trgi x1 1x 11 01 00 ad0con0 : ch2, ch1, ch0 ad1con0 : ch2, ch1, ch0 10 00 01 11 ad1con2 : aps1, aps0 ad0con2 : ads p2 p0 p15 p10 ad trg tb2int iiog2 ch1 int (i=0) or iiog3 ch1 int (i=1) p9 6 p9 5 0101 comparator 0 comparator 1 address address successive conversion register resister ladder figure 1.24.1. block diagram of a-d converter
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 283 table 1.24.1. performance of a-d converter item performance method of a-d conversion successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to av cc (v cc ) operating clock ? ad (note 2) f ad , f ad /2, f ad /3 , f ad /4 f ad =f(x in ) resolution 8-bit or 10-bit (selectable) operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 analog input pins 34 pins an, an0, an2, an15 (note 3) each 8 pins extended input 2 pins (anex0 (note 4) and anex1 (note 5) ) a-d conversion start condition ? software trigger a-d conversion starts when the a-d conversion start flag changes to 1 ? external trigger (can be retriggered) a-d conversion starts by outbreak of the following factors chosen among in three (note 6) ad trg /p9 7 input changes from h to l timer b2 interrupt occurrences frequency counter overflow interrupt of intelligent i/o group 2 or 3 channel 1 conversion speed per pin ? without sample and hold function 8-bit resolution: 49 ? ad cycles 10-bit resolution: 59 ? ad cycles ? with sample and hold function 8-bit resolution: 28 ? ad cycles 10-bit resolution: 33 ? ad cycles note 1: does not depend on use of sample and hold function. note 2: when f(x in ) is over 10 mhz, the f ad frequency must be under 10 mhz by dividing. without sample and hold function, set the f ad frequency to 250khz or more. with the sample and hold function, set the f ad frequency to 1mhz or more. note 3: when port p15 is used as analog input port, port p15 input peripheral function select bit (bit 2 of address 0178 16 ) must set to be "1". note 4: when port p9 5 is used as analog input port, port p9 5 output peripheral function select bit (bit 5 of address 03b7 16 ) must set to be "1". note 5: when port p9 6 is used as analog input port, port p9 6 output peripheral function select bit (bit 6 of address 03b7 16 ) must set to be "1". note 6: set the port direction register to input.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 284 function a-d0 control register 0 (note 1) bit name bit symbol symbol address when reset ad0con0 0396 16 00 16 rw ch0 ch1 ch2 analog input pin select bit md0 md1 trg cks0 adst a-d operation mode select bit 0 a-d conversion start flag trigger select bit frequency select bit 0 : software trigger 1 : external trigger 0 : a-d conversion disabled 1 : a-d conversion started 0 : f ad /3 or f ad /4 is selected 1 : f ad /1 or f ad /2 is selected 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 repeat sweep mode 1 b1 b0 0 0 0 : an0 0 0 1 : an1 0 1 0 : an2 0 1 1 : an3 1 0 0 : an4 1 0 1 : an5 1 1 0 : an6 1 1 1 : an7 b2 b3 b4 (note 2, 3) (note 2) (note 5) (note 6) note 1: if the a-d0 control register 0 is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. note 3: this bit is disabled in single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. note 4: external trigger request cause can be selected in external trigger request cause select bit (bit5 and bit 6 of address 0394 16 ). note 5: when external trigger is selected, set to "1" after selecting the external trigger request cause using the external trigger request cause select bit. note 6: when f(x in ) is over 10 mhz, the ad frequency must be under 10 mhz by dividing. (note 4) b7 b6 b5 b4 b3 b2 b1 b0 figure 1.24.2. a-d converter-related registers (1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 285 function a-d0 control register 1 (note 1) bit name bit symbol symbol address when reset ad0con1 0397 16 00 16 rw scan0 scan1 md2 a-d sweep pin select bit bits cks1 vcut opa1 opa0 8/10-bit mode select bit external op-amp connection mode bit 0 : v ref not connectec 1 : v ref connectec 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode v ref connect bit 0 : f ad /2 or f ad /4 is selected 1 : f ad /1 or f ad /3 is selected 0 : 8-bit mode 1 : 10-bit mode a-d operation mode select bit 1 0 0 : anj 0 , anj 1 (anj 0 ) 0 1 : anj 0 to anj 3 (anj 0 , anj 1 ) 1 0 : anj 0 to anj 5 (anj 0 to anj 2 ) 1 1 : anj 0 to anj 7 (anj 0 to anj 3 ) 0 : any mode other than repeat sweep mode 1 1 : repeat sweep mode 1 (note 2, 3) frequency select bit (note 3) (note 4) (note 5) (note 6) (note 7) (note 8) b1 b0 b7 b6 note 1: if the a-d0 control register 1 is rewritten during a-d conversion, the conversion result is indeterminate. note 2: this bit is invalid in one-shot mode and repeat mode. channel shown in the parentheses, becomes valid when repeat sweep mode 1(bit2="1") is selected. note 3: when f(x in ) is over 10 mhz, the ad frequency must be under 10 mhz by dividing. note 4: in single sweep mode and repeat sweep mode 0, 1, bit 7 and bit 6 cannot be set "01" and "10". note 5: when this bit is set, set "00" to bit6 and bit5 of function select register b3. note 6: when this bit is set, set "1" to bit5 of function select register b3. note 7: when this bit is set, set "1" to bit6 of function select register b3. note 8: when this bit is set, set "11" to bit6 and bit5 of function select register b3. b7 b6 b5 b4 b3 b2 b1 b0 figure 1.24.3. a-d converter-related registers (2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 286 function a-d0 control register 2 (note 1) bit name bit symbol symbol address when reset ad0con2 0394 16 x000 0000 2 rw smp ads trg0 trg1 note 1: if the a-d0 control register 2 is rewritten during a-d conversion, the conversion result is indeterminat e note 2: when the a-d circuit of either of a-d0 and a-d1 are operated, do not write "1" to this bit. note 3: this bit is valid when software trigger is selected. note 4: when this bit read, the value is indeterminate. note 5: this is valid in three-phase pwm mode. note 6: turn every setting of a-d0 and a-d1 into same, and start at the same time in sweep mode. a-d conversion method select bit 0 : without sample and hold 1 : with sample and hold reserved bit must always set to "0" 0 : channel replace is invalid 1 : channel replace is valid pst external trigger request cause select bit a-d channel replace select bit simultaneous start bit 0 : invalid 1 : 2 circuit a-d simultaneous start 0 0 : ad trg is selected 0 1 : timer b2 interrupt occurrence frequency counter overflow is selected (note 3) 1 0 : group 2 channel 1 interrupt is selected 1 1 : must not be set (note 2) (note 6) b6 b5 (note 5) (note 4) b7 b6 b5 b4 b3 b2 b1 b0 000 function a-d0 register j (j=0 to 7) symbol address when reset ad0j(j=0 to 2) 0381 16 ,0380 16 , 0383 16 ,0382 16 , 0385 16 ,0384 16 indeterminate ad0j(j=3 to 5) 0387 16 ,0386 16 , 0389 16 ,0388 16 , 038b 16 ,038a 16 indeterminate ad0j(j=6,7) 038d 16 ,038c 16 , 038f 16 ,038e 16 indeterminate rw eight low-order bits of a-d conversion result nothing is assigned. when write, set "0". when read, their contents are indeterminate. during 10-bit mode during 8-bit mode : two high-order bits of a-d conversion result : when read, their contents are indeterminate b7 b0 b15 (b7) b8 (b0) figure 1.24.4. a-d converter-related registers (3)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 287 function a-d1 control register 0 (note 1) bit name bit symbol symbol address when reset ad1con0 01d6 16 00 16 rw ch0 ch1 ch2 analog input pin select bit md0 md1 trg cks0 adst a-d operation mode select bit 0 a-d conversion start flag trigger select bit frequency select bit 0 : software trigger 1 : external trigger 0 : a-d conversion disabled 1 : a-d conversion started 0 : f ad /3 or f ad /4 is selected 1 : f ad /1 or f ad /2 is selected 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 repeat sweep mode 1 0 0 0 : anj 0 0 0 1 : anj 1 0 1 0 : anj 2 0 1 1 : anj 3 1 0 0 : anj 4 1 0 1 : anj 5 1 1 0 : anj 6 1 1 1 : anj 7 (note 2, 3, 4) (note 2) (note 7) (note 5, 6) (note 8) b2 b1 b4 b3 b0 note 1: if the a-d1 control register 0 is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. note 3: this bit is disabled in single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. note 4: j=0, 2, 15 is selected by analog input port select bits (bit1 and bit 2 of address 01d4 16 ). note 5: external trigger request cause can be selected in external trigger request cause select bit (bit5 and bit 6 of address 01d4 16 ). note 6: after selecting external trigger request cause, set to "1". note 7: when external trigger is selected, set to "1" after selecting the external trigger. note 8: when f(x in ) is over 10 mhz, the ad frequency must be under 10 mhz by dividing. (j=0, 2, 15) b7 b6 b5 b4 b3 b2 b1 b0 figure 1.24.5. a-d converter-related registers (4)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 288 function a-d1 control register 1 (note 1) bit name bit symbol symbol address when reset ad1con1 01d7 16 xx000000 2 rw scan0 scan1 md2 a-d sweep pin select bit bits cks1 vcut 8/10-bit mode select bit v ref connect bit 0 : v ref not connectec 1 : v ref connectec frequency select bit 0 : f ad /2 or f ad /4 is selected 1 : f ad /1 or f ad /3 is selected 0 : 8-bit mode 1 : 10-bit mode a-d operation mode select bit 1 0 0 : anj 0 ,anj 1 (anj 0 ) 0 1 : anj 0 to anj 3 (anj 0 ,anj 1 ) 1 0 : anj 0 to anj 5 (anj 0 to anj 2 ) 1 1 : anj 0 to anj 7 (anj 0 to anj 3 ) (j=0, 2, 15) 0 : any mode except repeat sweep mode 1 1 : repeat sweep mode 1 (note 4) (note 2, 3) b1 b0 nothing is assigned. when write, set to "0". when read, their contents are indeterminate . note 1: if the a-d1 control register 1 is rewritten during a-d conversion, the conversion result is indeterminate. note 2: this bit is invalid in one-shot mode and repeat mode. channel shown in the parentheses, becomes valid when repeat sweep mode 1(bit 2 = "1") is selected. note 3: j=0, 2, 15 is selected by analog input port select bits (bit1 and bit 2 of address 01d4 16 ). note 4: when f(x in ) is over 10 mhz, the ad frequency must be under 10 mhz by dividing. b7 b6 b5 b4 b3 b2 b1 b0 figure 1.24.6. a-d converter-related registers (5)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 289 bit name a-d1 control register 2 (note 1) bit name bit symbol symbol address when reset ad1con2 01d4 16 x00xx000 2 rw smp aps0 aps1 a-d conversion method select bit note 1: if the a-d1 control register 2 is rewritten during a-d conversion, the conversion. note 2: this is valid in three-phase pwm mode. 0 : without sample and hold 1 : with sample and hold nothing is assigned. when write, set to "0". when read, its content is indeterminate. nothing is assigned. when write, set to "0". when read, their contents are indeterminate. trg0 trg1 external trigger request cause select bit 0 0 : ad trg is selected 0 1 : timer b2 interrupt occurrence frequency counter overflow is selected (note 2) 1 0 : group 3 channel 1 interrupt is selected 1 1 : must not be set b6 analog input port select bit 0 0 : p15 0 1 : must not be set 1 0 : p0 1 1 : p2 b2 b1 b5 b7 b6 b5 b4 b3 b2 b1 b0 function a-d1 register j (j=0 to 7) symbol address when reset ad1j(j=0 to 2) 01c1 16 ,01c0 16 , 01c3 16 ,01c2 16 , 01c5 16 ,01c4 16 indeterminate ad1j(j=3 to 5) 01c7 16 ,01c6 16 , 01c9 16 ,01c8 16 , 01cb 16 ,01ca 16 indeterminate ad1j(j=6,7) 01cd 16 ,01cc 16 , 01cf 16 ,01ce 16 indeterminate rw eight low-order bits of a-d conversion result nothing is assigned. when write, set to "0". when read, their contents are indeterminate. during 10-bit mode during 8-bit mode : two high-order bits of a-d conversion result : when read, their contents are indeterminate b7 b0 b15 (b7) b8 (b0) figure 1.24.7. a-d converter-related registers (6)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 290 (1) one-shot mode in one-shot mode, the pin selected using the analog input pin select bit is used for one-shot a-d conver- sion. table 1.24.2 shows the specifications of one-shot mode. table 1.24.2. one-shot mode specifications item specification function the pin selected by the analog input pin select bit is used for one a-d conversion start condition writing 1 to a-di conversion start flag, external trigger stop condition ? end of a-di conversion (a-di conversion start flag changes to 0 , except when external trigger is selected) ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin one of anj 0 to anj 7 (j =non, 0, 2, 15), anex0, anex1 reading of result of a-d converter read a-d register corresponding to selected pin (2) repeat mode in repeat mode, the pin selected using the analog input pin select bit is used for repeated a-d conversion. table 1.24.3 shows the a-d control register in repeat mode. table 1.24.3. repeat mode specifications item specification function the pin selected by the analog input pin select bit is used for repeated a-d con- version start condition writing 1 to a-d conversion start flag, external trigger stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin one of anj 0 to anj 7 (j =non, 0, 2, 15), anex0, anex1 reading of result of a-d converter read a-d register corresponding to selected pin (3) single sweep mode in single sweep mode, the pins selected using the a-d sweep pin select bit are used for one-by-one a-d conversion. table 1.24.4 shows the a-d control register in single sweep mode. table 1.24.4. single sweep mode specifications item specification function the pins selected by the a-di sweep pin select bit are used for one-by-one a-d conversion start condition writing 1 to a-d converter start flag, external trigger stop condition ? end of a-di conversion (a-d conversion start flag changes to 0 , except when external trigger is selected) ? writing 0 to a-di conversion start flag interrupt request generation timing end of sweep input pin anj 0 and anj 1 (2 pins), anj 0 to anj 3 (4 pins), anj 0 to anj 5 (6 pins), or anj 0 to anj 7 (8 pins) (j =non, 0, 2, 15) reading of result of a-d converter read a-d register corresponding to selected pin
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 291 (4) repeat sweep mode 0 in repeat sweep mode 0, the pins selected using the a-d sweep pin select bit are used for repeat sweep a-d conversion. table 1.24.5 shows the specifications of repeat sweep mode 0. table 1.24.5. repeat sweep mode 0 specifications item specification function the pins selected by the a-d sweep pin select bit are used for repeat sweep a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin anj 0 and anj 1 (2 pins), anj 0 to anj 3 (4 pins), anj 0 to anj 5 (6 pins), or anj 0 to an 7 (8 pins) (j =non, 0, 2, 15) reading of result of a-d converter read a-d register corresponding to selected pin (5) repeat sweep mode 1 in repeat sweep mode 1, all pins are used for a-d conversion with emphasis on the pin or pins selected using the a-d sweep pin select bit. table 1.26.6 shows the specifications of repeat sweep mode 1. table 1.26.6. repeat sweep mode 1 specifications item specification function all pins perform repeat sweep a-d conversion, with emphasis on the pin or pins selected by the a-d sweep pin select bit example : an 0 selected anj 0 anj 1 anj 0 anj 2 anj 0 anj 3 etc. (j =non, 0, 2, 15) start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin anj 0 to anj 7 (j =non, 0, 2, 15) with emphasis on the pin anj 0 (1 pin), anj 0 and anj 1 (2 pins), anj 0 to anj 2 (3 pins), anj 0 to anj 3 (4 pins) (j =non, 0, 2, 15) reading of result of a-d converter read a-d register corresponding to selected pin
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 292 (a) resolution select function 8/10-bit mode select bit of a-d control register 1 (bit 3 at address 0397 16 , 01d7 16 ) when set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. when set to 8-bit precision, the low 8 bits are stored in the even addresses. (b) sample and hold sample and hold are selected by setting bit 0 of the a-d control register 2 (address 0394 16 , 01d4 16 ) to 1 . when sample and hold are selected, the rate of conversion of each pin increases. as a result, a 28 ? ad cycle is achieved with 8-bit resolution and 33 ? ad with 10-bit resolution. sample and hold can be selected in all modes. however, in all modes, be sure to specify before starting a-d conversion whether sample and hold are to be used. (c) trigger select function can appoint start of conversion, by a combination of setting of trigger select bit (bit 5 at address 0396 16 , 01d6 16 ) and external trigger request cause select bit (bit 5 and bit 6 at address 0394 16 , 01d4 16 ), as follows. table 1.24.7. trigger select function setting trigger select bit="1" trigger select bit= "0" external trigger cause select bits 00 01 10 a-d0 software trigger ad trg timer b2 ofcoi (note) group 2 channel 1 interrupt a-d1 software trigger ad trg timer b2 ofcoi (note) group 3 channel 1 interrupt timer b2 ofcoi : timer b2 occurrence frequency counter overflow interrupt note :valid in three-phase pwm mode. (d) two circuit same time start (software trigger) two a-d converters can start at the same time by setting simultaneous start bit (bit 7 of address 0394 16 ) to 1 . during the a-d circuit of either of a-d0 and a-d1 are operated, do not set 1 to the simultaneous start bit. do not set to "1" when external trigger is selected. when using this bit, do not set a-d conversion start flag (bit 6 of address 0396 16 , 01d6 16 ) to "1". (e) replace function of input pin setting "1" to a-d channel replace select bit of a-d0 control register 2 (ads:bit 4 at address 0394 16 ) can replace channel of a-d0 and a-d1. a-d conversion reliability is confirmed by replacing channels. when ads bit is "1", a corresponding pin of a-d0 register i is selected by analog input port select bits of a-d1 control register 2 (bits 2 and 1 at address 01d4 16 ). in this case, a-d0 control register 0 and a-d1 control register 0 must be set to same value.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 293 table 1.24.8. setting of analog input port replace of a-d converter setting value a-d channel replace select bit 1 a-d conversion stored register analog output port select bit 00 10 11 a-d0 register 0 an15 0 an0 0 an2 0 a-d0 register 1 an15 1 an0 1 an2 1 a-d0 register 2 an15 2 an0 2 an2 2 a-d0 register 3 an15 3 an0 3 an2 3 a-d0 register 4 an15 4 an0 4 an2 4 a-d0 register 5 an15 5 an0 5 an2 5 a-d0 register 6 an15 6 an0 6 an2 6 a-d0 register 7 an15 7 an0 7 an2 7 a-d1 register 0 an 0 a-d1 register 1 an 1 a-d1 register 2 an 2 a-d1 register 3 an 3 a-d1 register 4 an 4 a-d1 register 5 an 5 a-d1 register 6 an 6 a-d1 register 7 an 7 (f) extended analog input pins in one-shot mode and repeat mode, the input via the extended analog input pins anex0 and anex1 can also be converted from analog to digital as an 0 and an 1 analog input signal respectively. set the related input peripheral function of the function select register b3 to disabled. (g) external operation amp connection mode in this mode, multiple external analog inputs via the extended analog input pins, anex0 and anex1, can be amplified together by just one operation amp and used as the input for a-d conversion. when bit 6 and bit 7 of the a-d control register 1 (address 0397 16 ) is 11 , input via an 0 to an 7 is output from anex0. the input from anex1 is converted from analog to digital and the result stored in the corresponding a-d register. the speed of a-d conversion depends on the response of the external operation amp. do not connect the anex0 and anex1 pins directly. figure 1.24.8 is an example of how to connect the pins in external operation amp mode. set the related input peripheral function of the function select register b3 to disabled.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 294 table 1.24.9. setting of extended analog input pins a-d0 control register 1 anex0 function anex1 function bit 7 bit 6 0 0 not used not used 0 1 p9 5 analog input not used 1 0 not used p9 6 analog input 1 1 output to external ope-amp input from external ope-amp figure 1.24.8. example of external op-amp connection mode (h) power consumption reduction function v ref connect bit (bit 5 at addresses 0397 16 , 01d7 16 ) the v ref connect bit (bit 5 at address 0397 16 , 01d7 16 ) can be used to isolate the resistance ladder of the a-d converter from the reference voltage input pin (v ref ) when the a-d converter is not used. doing so stops any current flowing into the resistance ladder from v ref , reducing the power dissipation. when using the a-d converter, start a-d conversion only after connecting v ref . do not write a-d conversion start flag and v ref connect bit to 1 at the same time. do not clear v ref connect bit to 0 during a-d conversion. this v ref is without reference to d-a converter's v ref . analog input external op-amp an 0 an 7 an 1 an 2 an 3 an 4 an 5 an 6 anex1 anex0 resistance ladder successive conversion register comparator
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer a-d converter 295 precaution after a-d conversion is complete, if the cpu reads the a-d register at the same time as the a-d conver- sion result is being saved to a-d register, wrong a-d conversion value is saved into the a-d register. this happens when the internal cpu clock is selected from divided main clock or sub-clock. when using the one-shot or single sweep mode confirm that a-d conversion is complete before reading the a-d register. (note: when a-d conversion interrupt request bit is set, it shows that a-d conversion is completed.) when using the repeat mode or repeat sweep mode 0 or 1 use the undivided main clock as the internal cpu clock.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer d-a conversion 296 d-a converter this is an 8-bit, r-2r type d-a converter. the microcomputer contains two independent d-a converters of this type. d-a conversion is performed when a value is written to the corresponding d-a register. bits 0 and 1 (d-a output enable bits) of the d-a control register decide if the result of conversion is to be output. set the function select register a3 to i/o port, the related input peripheral function of the function select register b3 to disabled and the direction register to input mode. do not set the target port to pulled-up when d-a output is enabled. output analog voltage (v) is determined by a set value (n : decimal) in the d-a register. v = v ref x n/ 256 (n = 0 to 255) v ref : reference voltage (this is unrelated to bit 5 of a-d control register 1 (addresses 0397 16 , 01d7 16 ) table 1.25.1 lists the performance of the d-a converter. figure 1.25.1 shows the block diagram of the d-a converter. figure 1.25.2 shows the d-a control register. figure 1.25.3 shows the d-a converter equivalent circuit. when the d-a converter is not used, set the d-a register to "00" and d-a output enable bit to "0". item performance conversion method r-2r method resolution 8 bits analog output pin 2 channels table 1.25.1. performance of d-a converter d-a register i (8) (i = 0, 1) r-2r resistance ladder (address 0398 16 , 039a 16 ) d-ai output enable bit (i = 0, 1) a aaaaaa aaaaaa p9 3 / da 0 aaaaaa p9 4 / da 1 data bus low-order bits figure 1.25.1. block diagram of d-a converter
d-a conversion under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 297 function d-a control register bit name bit symbol symbol address when reset dacon 039c 16 xxxxxx00 2 rw d-a0 output enable bit d-a1 output enable bit nothing is assigned. when write, set to "0". when read, their contents are "0". 0 : output disabled 1 : output enabled 0 : output disabled 1 : output enabled da1e da0e b7 b6 b5 b4 b3 b2 b1 b0 d-a register i symbol address when reset dai(i=0,1) 0398 16 , 039a 16 indeterminate rw function setting range output value of d-a conversion 00 16 to ff 16 b7 b0 v ref av ss 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r d-a0 output enable bit da0 "1" "0" msb lsb d-a register 0 "0" "1" note 1: in the above figure, the d-a register value is "2a 16 ". note 2: this circuit is the same in d-a1. note 3: to save power dissipation when not using the d-a converter, set the d-a output enable bit to "0" and the d-a register to "00 16 ", and prevent current flowing to the r-2r resistance. r figure 1.25.2. d-a control register figure 1.25.3. d-a converter equivalent circuit
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer crc 298 aaaaa aaaaa eight low-order bits aaaaaa aaaaaa eight high-order bits data bus high-order bits data bus low-order bits aaaaaaaaaa aaaaaaaaaa aaaaa aaaaa crc data register (16) crc input register (8) aaaaaaaaaa a aaaaaaaa a aaaaaaaaaa crc code generating circuit x 16 + x 12 + x 5 + 1 (addresses 037d 16 , 037c 16 ) (address 037e 16 ) setting range crc data register function symbol address when reset crcd 037d 16 , 037c 16 indeterminate rw crc calculation output register 0000 16 to ffff 16 b15 (b7) b8 (b0) b7 b0 setting range crc input register function symbol address when reset crcin 037e 16 indeterminate rw data input register 00 16 to ff 16 b7 b0 crc calculation circuit the cyclic redundancy check (crc) calculation circuit detects an error in data blocks. the microcom- puter uses a generator polynomial of crc_ccitt (x 16 + x 12 + x 5 + 1) to generate crc code. the crc code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. the crc code is set in a crc data register each time one byte of data is transferred to a crc input register after writing an initial value into the crc data register. generation of crc code for one byte of data is com- pleted in two machine cycles. figure 1.26.1 shows the block diagram of the crc circuit. figure 1.26.2 shows the crc-related registers. figure 1.26.3 shows the crc example. figure 1.26.1. block diagram of crc circuit figure 1.26.2. crc-related registers
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer crc 299 b15 b0 (1) setting 0000 16 crc data register crcd [037d 16 , 037c 16 ] b0 b7 b15 b0 (2) setting 01 16 crc input register crcin [037e 16 ] 2 cycles after crc calculation is complete crc data register crcd [037d 16 , 037c 16 ] 1189 16 stores crc code b0 b7 b15 b0 (3) setting 23 16 crc input register crcin [037e 16 ] after crc calculation is complete crc data register crcd [037d 16 , 037c 16 ] 0a41 16 stores crc code the code resulting from sending 01 16 in lsb first mode is (1000 0000). thus the crc code in the generating polynomial, (x 16 + x 12 + x 5 + 1), becomes the remainder resulting from dividing (1000 0000) x 16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. thus the crc code becomes (1001 0001 1000 1000). since the operation is in lsb first mode, the (1001 0001 1000 1000) corresponds to 1189 16 in hexadecimal notation. if the crc operation in msb first mode is necessary in the crc operation circuit built in the m32c, switch between the lsb side and the msb side of the input-holding bits, and carry out the crc operation. also switch between the msb and lsb of the result as stored in crc data. 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 lsb msb lsb msb 98 1 1 modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1 figure 1.26.3. crc example
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer x-y converter 300 x-y converter x-y conversion rotates the 16 x 16 matrix data by 90 degrees. it can also be used to invert the top and bottom of the 16-bit data. figure 1.27.1 shows the xy control register. the xi and the yi registers are 16-bit registers. there are 16 of each (where i= 0 to 15). the xi and yi registers are mapped to the same address. the xi register is a write-only register, while the yi register is a read-only register. be sure to access the xi and yi registers in 16-bit units from an even address. operation cannot be guaranteed if you attempt to access these registers in 8-bit units. function xy control register bit name bit symbol symbol address when reset xyc 02e0 16 xxxxxx00 2 rw read-mode set bit write-mode set bit noting is assigned. when write, set to "0". when read, their contents are indeterminate. 0 : data conversion 1 : no data conversion 0 : no bit mapping conversion 1 : bit mapping conversion xyc1 xyc0 b7 b6 b5 b4 b3 b2 b1 b0 figure 1.27.1. xy control register
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer x-y converter 301 x0 register (0002c0 16 ) x1 register (0002c2 16 ) x2 register (0002c4 16 ) x3 register (0002c6 16 ) x4 register (0002c8 16 ) x5 register (0002ca 16 ) x6 register (0002cc 16 ) x7 register (0002ce 16 ) x8 register (0002d0 16 ) x9 register (0002d2 16 ) x10 register (0002d4 16 ) x11 register (0002d6 16 ) x12 register (0002d8 16 ) x13 register (0002da 16 ) x14 register (0002dc 16 ) x15 register (0002de 16 ) bit of xi register b0 b15 b0 b15 bit of yi register y0 register (0002c0 16 ) y1 register (0002c2 16 ) y2 register (0002c4 16 ) y3 register (0002c6 16 ) y4 register (0002c8 16 ) y5 register (0002ca 16 ) y6 register (0002cc 16 ) y7 register (0002ce 16 ) y8 register (0002d0 16 ) y9 register (0002d2 16 ) y10 register (0002d4 16 ) y11 register (0002d6 16 ) y12 register (0002d8 16 ) y13 register (0002da 16 ) y14 register (0002dc 16 ) y15 register (0002de 16 ) write address read address aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa x0-reg x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 (x register) y0-reg y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 a a aa aa a a aa aa a a a a aa aa aa aa aa aa aa aa aa a a a a a a aa aa a aa aa a aa (y register) the reading of the yi register is controlled by the read-mode set bit (bit 0 at address 02e0 16 ). when the read-mode set bit (bit 0 at address 02e0 16 ) is 0 , specific bits in the xi register can be read at the same time as the yi register is read. for example, when you read the y0 register, bit 0 is read as bit 0 of the x0 register, bit 1 is read as bit 0 of the x1 register, ..., bit 14 is read as bit 0 of the x14 register, bit 15 as bit 0 of the x15 register. similarly, when you read the y15 register, bit 0 is bit 15 of the x0 register, bit 1 is bit 15 of the x1 register, ..., bit 14 is bit 15 of the x14 register, bit 15 is bit 15 of the x15 register. figure 1.27.2 shows the conversion table when the read mode set bit = 0 . figure 1.27.3 shows the x-y conversion example. figure 1.27.2. conversion table when the read mode set bit = 0 figure 1.27.3. x-y conversion example
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer x-y converter 302 x0,y0 register (0002c0 16 ) x1,y1 register (0002c2 16 ) x2,y2 register (0002c4 16 ) x3,y3 register (0002c6 16 ) x4,y4 register (0002c8 16 ) x5,y5 register (0002ca 16 ) x6,y6 register (0002cc 16 ) x7,y7 register (0002ce 16 ) x8,y8 register (0002d0 16 ) x9,y9 register (0002d2 16 ) x10,y10 register (0002d4 16 ) x11,y11 register (0002d6 16 ) x12,y12 register (0002d8 16 ) x13,y13 register (0002da 16 ) x14,y14 register (0002dc 16 ) x15,y15 register (0002de 16 ) b 0 b15 a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa bit of xi register bit of yi register write address read address b15 b0 b15 b0 bit of xi register write address when the read-mode set bit (bit 0 at address 02e0 16 ) is 1 , you can read the value written to the xi register by reading the yi register. figure 1.27.4 shows the conversion table when the read mode set bit = 1 . the value written to the xi register is controlled by the write mode set bit (bit 1 at address 02e0 16 ). when the write mode set bit (bit 1 at address 02e0 16 ) is 0 and data is written to the xi register, the bit stream is written directly. when the write mode set bit (bit 1 at address 02e0 16 ) is 1 and data is written to the xi register, the bit sequence is reversed so that the high becomes low and vice versa. figure 1.27.5 shows the conversion table when the write mode set bit = 1 . figure 1.27.4. conversion table when the read mode set bit = 1 figure 1.27.5. conversion table when the write mode set bit = 1
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dram controller 303 dram controller there is a built in dram controller to which it is possible to connect between 512 kbytes and 8 mbytes of dram. table 1.28.1 shows the functions of the dram controller. dram space 512kb, 1mb, 2mb, 4mb, 8mb bus control 2cas/1w refresh ________ ________ cas before ras refresh, self refresh-compatible function modes edo-compatible, fast page mode-compatible waits 1 wait or 2 waits, programmable to use the dram controller, use the dram space select bit of the dram control register (address 0040 16 ) to specify the dram size. figure 1.28.1 shows the dram control register. the dram controller cannot be used in external memory mode 3 (bits 1 and 2 at address 0005 16 are 11 2 ). always use the dram controller in external memory modes 0, 1, or 2. when the data bus width is 16-bit in dram area, set "1" to r/w mode select bit (bit 2 at address 0004 16 ). set wait time between after dram power on and before memory processing, and processing necessary for dummy cycle to refresh dram by software. (note 1) function dram control register bit name bit symbol symbol address when reset dramcont 0040 16 indeterminate rw ar1 ar2 dram space select bit wt ar0 sref note 1: after reset, the content of this register is indeterminate. dram controller starts operation after writing to this register. note 2: the number of cycles with 2 waits is 3-2-2. with 1 wait, it is 2-1-1. note 3: when you set to "1", both ras and cas change to "l". when you set to "0", ras and cas change to "h" and then normal operation (read/write, refresh) is resumed. in stop mode, there is no control. note 4: set the bus width using the external data bus width control register (address 000b 16 ). when selecting 8-bit bus width, cash is indeterminate. self-refresh mode bit (note 3) 0 : two wait 1 : one wait b3 b2 b1 0 0 0 : dram ignored 0 0 1 : must not be set 0 1 0 : 0.5mb 0 1 1 : 1mb 1 0 0 : 2mb 1 0 1 : 4mb 1 1 0 : 8mb 1 1 1 : must not be set 0 : self-refresh off 1 : self-refresh on nothing is assigned. when write, set to "0". when read, their contents are indeterminate. wait select bit (note 2) b7 b6 b5 b4 b3 b2 b1 b0 table 1.28.1. dram controller functions figure 1.28.1. dram control register
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dram controller 304 a9 (a20) (a19) a18 a17 a16 a15 a14 a13 a12 a11 a10 a0 (a22) (a22) a8 a7 a6 a5 a4 a3 a2 a1 8-bit bus mode (a9) (a20) (a19) (a18) (a17) (a16) (a15) (a14) (a13) (a12) (a11) (a10) 512kb, 1mb 2mb, 4mb 8mb ma1 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 a9 (a20) a18 a17 a16 a15 a14 a13 a12 a11 a10 a0 (a22) a8 a7 a6 a5 a4 a3 a2 a1 a19 a19 a20 a21 a9 a18 a17 a16 a15 a14 a13 a12 a11 a10 a0 (a22) a8 a7 a6 a5 a4 a3 a2 a1 a19 a21 a22 a20 (a9) (a20) (a19) a18 a17 a16 a15 a14 a13 a12 a11 a10 (a0) (a22) (a20) a8 a7 a6 a5 a4 a3 a2 a1 16-bit bus mode (a9) (a20) (a19) (a18) (a17) (a16) (a15) (a14) (a13) (a12) (a11) (a10) pin function 512kb 1mb, 2mb 4mb, 8mb (note 2) ma1 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 (a9) (a20) a18 a17 a16 a15 a14 a13 a12 a11 a10 (a0) (a22) a8 a7 a6 a5 a4 a3 a2 a1 a19 a9 a9 a20 (a9) a18 a17 a16 a15 a14 a13 a12 a11 a10 (a0) a8 a7 a6 a5 a4 a3 a2 a1 row address a19 a9 a21 a20 a22 note 1: ( ) invalid bit: bits that change according to selected mode (8-bit/16-bit bus mode, dram space). note 2: the figure is for 4mx1 or 4mx4 memory configuration. if you are using a 4mx16 configuration, use combinations of the following: for row addresses, ma0 to ma12; for column addresses ma2 to ma8, ma11, and ma12. or for row addresses ma1 to ma12; for column addresses ma2 to ma9, ma11, ma12. note 3: " C " is indetermimate. C C (a8) ma0 C C C C C C (a8) ma0 C C C C row address row address pin function row address row address row address column address column address column address column address column address column address dram controller multiplex address output the dram controller outputs the row addresses and column addresses as a multiplexed signal to the address bus a 8 to a 20 . figure 1.28.2 shows the output format for multiplexed addresses. figure 1.28.2. output format for multiplexed addresses
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dram controller 305 (note) function dram refresh interval set register bit name bit symbol symbol address when reset refcnt 0041 16 indeterminate rw 0 0 0 0 0 0 0 0 : 1.1 s 0 0 0 0 0 0 0 1 : 2.1 s 0 0 0 0 0 0 1 0 : 3.2 s 1 1 1 1 1 1 1 1 : 272.8 s note. refresh interval at 30 mhz operating (no division). refresh interval = bclk frequency x ( refresh interval set bit + 1) x 32 refresh interval set bit refcnt7 refcnt6 refcnt5 refcnt3 refcnt4 refcnt1 refcnt2 refcnt0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 refresh _______ _______ the refresh method is cas before ras. the refresh interval is set by the dram refresh interval set register (address 0041 16 ). the refresh signal is not output in hold state. figure 1.28.3 shows the dram refresh interval set register. use the following formula to determine the value to set in the refresh interval set register. refresh interval set register value (0 to 255) = refresh interval time / (bclk frequency x 32) - 1 figure 1.28.3. dram refresh interval set register the dram self-refresh operates in stop mode, etc. when shifting to self-refresh, select dram ignored by the dram space select bit. in the next instruction, simultaneously set the dram space select bit and self-refresh on by self-refresh mode bit. also, insert two nops after the instruction that sets the self-refresh mode bit to "1". do not access external memory while operating in self-refresh. (all external memory space access is inhibited. ) when disabling self-refresh, simultaneously select dram ignored by the dram space select bit and self- refresh off by self-refresh mode bit. in the next instruction, set the dram space select bit. do not access the dram space immediately after setting the dram space select bit.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dram controller 306 example) one wait is selected by the wait select bit and 4mb is selected by the dram space select bit shifting to self-refresh ??? mov.b #00000001b,dramcont ;dram ignored, one wait is selected mov.b #10001011b,dramcont ;set self-refresh, select 4mb and one wait nop ;two nops are needed nop ; ??? disable self-refresh ??? mov.b #00000001b,dramcont ;disable self-refresh, dram ignored, one wait is ;selected mov.b #00001011b,dramcont ;select 4mb and one wait nop ;inhibit instruction to access dram area nop ??? figures 1.28.4 to 1.28.6 show the bus timing during dram access.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dram controller 307 bclk ma0 to ma12 ras cash casl dw d 0 to d 15 (edo mode) bclk ma0 to ma12 ras cash casl dw d 0 to d 15 'h' < read cycle (wait control bit = 0) > < write cycle (wait control bit = 0) > row address row address note : only casl is operating in 8-bit data bus width. note : only casl is operating in 8-bit data bus width. column address 1 column address 2 column address 3 column address 1 column address 2 column address 3 figure 1.28.4. the bus timing during dram access (1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dram controller 308 bclk ma0 to ma12 ras cash casl dw d 0 to d 15 (edo mode) bclk ma0 to ma12 ras cash casl dw d 0 to d 15 < read cycle (wait control bit = 1) > < write cycle (wait control bit = 1) > row address row address 'h' note : only casl is operating in 8-bit data bus width. note : only casl is operating in 8-bit data bus width. column address 1 column address 2 column address 3 column address 4 column address 1 column address 2 column address 3 column address 4 figure 1.28.5. the bus timing during dram access (2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer dram controller 309 bclk ras cash casl bclk ras < self refresh cycle > note : only casl is operating in 8-bit data bus width. "h" dw < cas before ras refresh cycle > cash casl "h" dw note : only casl is operating in 8-bit data bus width. figure 1.28.6. the bus timing during dram access (3)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 310 programmable i/o ports there are 123 programmable i/o ports in 144-pin version: p0 to p15 (excluding p8 5 ). there are 87 pro- grammable i/o ports in 100-pin version: p0 to p10 (excluding p8 5 ). each port can be set independently for input or output using the direction register. a pull-up resistance for each block of 4 ports can be set. p8 5 is an input-only port and has no built-in pull-up resistance. figures 1.29.1 to 1.29.4 show the programmable i/o ports. each pin functions as a programmable i/o port and as the i/o for the built-in peripheral devices. to use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. when the pins are used as the outputs for the built-in peripheral devices (other than the d-a con- verter), set the corresponding function select registers a, b and c. when pins are to be used as the outputs for the d-a converter, set the function select register a3 of each pin to i/o port, and set the direction registers to input mode. see the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) direction registers figurs 1.29.5 shows the direction registers. these registers are used to choose the direction of the programmable i/o ports. each bit in these regis- ters corresponds one for one to each i/o pin. in memory expansion and microprocessor mode, the contents of corresponding direction register of pins _____ _______ _______ _______ _____ _________ _______ _______ _______ _____ _____ a 0 to a 22 , a 23 , d 0 to d 15 , ma 0 to ma 12 , cs0 to cs3, wrl/wr/casl, wrh/bhe/cash, rd/dw, bclk/ _________ _________ _______ _______ ale/clkout, hlda/ale, hold, ale/ras, and rdy are not changed. note: there is no direction register bit for p8 5 . (2) port registers figure 1.29.6 shows the port registers. these registers are used to write and read data for input and output to and from an external device. a port register consists of a port latch to hold output data and a circuit to read the status of a pin. each bit in a port register corresponds one for one to each i/o pin. in memory expansion and microprocessor mode, the contents of corresponding port register of pins a 0 to _____ _______ _______ _______ _____ _________ _______ _______ _______ _____ _____ a 22 , a 23 , d 0 to d 15 , ma 0 to ma 12 , cs0 to cs3, wrl/wr/casl, wrh/bhe/cash, rd/dw, bclk/ale/ _________ _________ _______ _______ clkout, hlda/ale, hold, ale/ras, and rdy are not changed. (3) function select register a figures 1.29.7 to 1.29.11 show the function select registers a. the register is used to select port output and peripheral function output when the port functions for both port output and peripheral function output. each bit of this register corresponds to each pin that functions for both port output and peripheral function output.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 311 (4) function select register b figures 1.29.12 and 1.29.13 show the function select registers b. this register selects the first peripheral function output and second peripheral function output when mul- tiple peripheral function outputs are assigned to a pin. for pins with a third peripheral function, this regis- ter selects whether to enable the function select register c, or output the second peripheral function. each bit of this register corresponds to each pin that has multiple peripheral function outputs assigned to it. this register is enabled when the bits of the corresponding function select register a are set for peripheral functions. the bit 3 to bit 6 of function select register b3 is ignored bit for input peripheral function. when using da0/da1 and anex0/anex1, set related bit to 1 . when not using da0/da1 or anex0/anex1, set related bit to 0 . (5) function select register c figure 1.29.14 shows the function select register c. this register is used to select the first peripheral function output and the third peripheral function output when three peripheral function outputs are assigned to a pin. this register is effective when the bits of the function select register a of the counterpart pin have selected a peripheral function and when the function select register b has made effective the function select register c. the bit 7 (psc_7) is assigned the key-in interrupt inhibit bit. setting 1 in the key-in interrupt inhibit bit causes no key-in interrupts regardless of the settings in the interrupt control register even if l is entered ______ ______ in pins ki 0 to ki 3 . with 1 set in the key-in interrupt inhibit bit, input from a port pin cannot be effected even if the port direction register is set to input mode. (6) pull-up control registers figures 1.29.15 to 1.29.17 show the pull-up control registers. the pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. when ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. since p0 to p5 operate as the bus in memory expansion mode and microprocessor mode, do not set the pull-up control register. however, it is possible to select pull-up resistance presence to the usable port as i/o port by setting. (7) port control register figure 1.29.18 shows the port control register. this register is used to choose whether to make port p1 a cmos port or an nch open drain. in the nch open drain, the cmos port s pch is kept always turned off so that the port p1 cannot be a complete open drain. thus the absolute maximum rating of the input voltage falls within the range from - 0.3 v to vcc + 0.3 v . the port control register functions similarly to the above. also in the case in which port p1 can be used as a port when the bus width in the full external areas comprises 8 bits in either microprocessor mode or in memory expansion mode.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 312 direction register port latch input to respective peripheral functions analog signal pull-up selection data bus a b c p0 0 to p0 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 7 p5 0 to p5 2 p5 4 p5 5 p5 6 p5 7 p8 3 , p8 4 p8 6 p8 7 p10 0 to p10 3 p10 4 to p10 7 p11 4 p14 4 to p14 6 p15 2 , p15 3 p15 6 , p15 7 option port (a) hysteresis presence circuit (b) input to respective peripheral functions circuit (c) analog i/f (note) note: these ports exist in 144-pin version. : present, : not present programmable i/o ports figure 1.29.1. programmable i/o ports (1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 313 p1 0 to p1 4 option port (a) hysteresis presence circuit (b) input to respective peripheral functions p1 5 to p1 7 direction register port latch input to respective peripheral functions pull-up selection data bus a b port p1 control register : present, : not present programmable i/o ports with port control register figure 1.29.2. programmable i/o ports (2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 314 a b c p5 3 p6 0 , p6 1 p6 3 to p6 5 , p6 7 p8 2 p9 0 to p9 2 p9 3 to p9 6 p11 1 , p11 2 p11 3 p12 0 p13 5 , p13 6 p12 1 , p12 2 p12 3 to p12 7 p13 0 to p13 4 p13 7 p14 0 , p14 1 p15 0 , p15 1 p15 4 , p15 5 option port (a) hysteresis presence circuit (b) input to respective peripheral functions circuit (c) analog i/f p7 0 , p7 1 p7 2 to p7 7 p8 0, p8 1 p9 7 p11 0 p14 2 , p14 3 circuit (d) direction register port latch input to respective peripheral functions analog signal pull-up selection data bus function select register a (note 1) note 1: p5 3 is clock output select bit for bclk. note 2: p7 0 and p7 1 are n-channel open drain output. note 3: these ports exist in 144-pin version. d output from each peripheral function (note 1) (note 2) (note 3) : present, : not present programmable i/o ports with function select register figure 1.29.3. programmable i/o ports (3)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 315 nmi data bus input-only port function port pi direction register (note 1, 2, 3) bit name bit symbol symbol address when reset pdi(i=0 to 5) 03e2 16 , 03e3 16 , 03e6 16 , 03e7 16 , 03ea 16 , 03eb 16 00 16 pdi(i=6 to 11) 03c2 16 , 03c3 16 , 03c6 16 , 03c7 16 , 03ca 16 , 03cb 16 00 16 pdi(i=12 to 15) 03ce 16 , 03cf 16 , 03d2 16 , 03d3 16 00 16 rw pdi_0 pdi_1 pdi_2 port pi 0 direction register pdi_3 pdi_4 pdi_5 pdi_7 pdi_6 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) port pi 1 direction register port pi 2 direction register port pi 3 direction register port pi 4 direction register port pi 5 direction register port pi 6 direction register port pi 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) (note 4) note 1: set bit 2 of protect register (address 000a 16 ) to "1" before rewriting to the port p9 direction register. note 2: in memory expansion and microprocessor mode, the contents of corresponding port direction register of pins a 0 to a 22 , a 23 , d 0 to d 15 , ma0 to ma12, cs0 to cs3, wrl/wr/casl, wrh/bhe/cash, rd/dw, bclk/ale/clk out , hlda/ale, hold, ale/ras, and rdy are not changed. note 3: port 11 to 15 registers exist in 144-pin version. note 4: nothing is assigned in bit5 of port p8 direction register, bit7 to bit5 of port p11 direction register and bit7 of port p14 direction register. when write, set to "0". when read, its content is indeterminate. (note 4) (note 4) b7 b6 b5 b4 b3 b2 b1 b0 figure 1.29.4. programmable i/o ports (4) figure 1.29.5. direction register
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 316 function port pi register (note 1, 2, 3) bit name bit symbol symbol address when reset pi(i=0 to 5) 03e0 16 , 03e1 16 , 03e4 16 , 03e5 16 , 03e8 16 , 03e9 16 indeterminate pi(i=6 to 11) 03c0 16 , 03c1 16 , 03c4 16 , 03c5 16 , 03c8 16 , 03c9 16 indeterminate pi(i=12 to 15) 03cc 16 , 03cd 16 , 03d0 16 , 03d1 16 indeterminate rw pi_0 pi_1 pi_2 port pi 0 register pi_3 pi_4 pi_5 pi_7 pi_6 port pi 1 register port pi 2 register port pi 3 register port pi 4 register port pi 5 register port pi 6 register port pi 7 register : "l" level : "h" level 0 1 : "l" level : "h" level 0 1 : "l" level : "h" level 0 1 : "l" level : "h" level 0 1 : "l" level : "h" level 0 1 : "l" level : "h" level 0 1 (note 5) (note 6) : "l" level : "h" level 0 1 (note 6) : "l" level : "h" level 0 1 (note 6) (note 4) (note 4) note 1: data is input and output to and from each pin by reading and writing to and from each corresponding bit. note 2: in memory expansion and microprocessor mode, the contents of corresponding port direction register of pins a 0 to a 22 , a 23 , d 0 to d 15 , ma0 to ma12, cs0 to cs3, wrl/wr/casl, wrh/bhe/cash, rd/dw, bclk/ale/clk out , hlda/ale, hold, ale/ras, and rdy are not changed. note 3: port 11 to 15 direction registers exist in 144-pin version. note 4: port p7 0 and p7 1 output high impedance because of n-channel open drain output. note 5: port p8 5 is read only (there is not w). note 6: nothing is assigned in bit7 to bit5 of port p11 and bit7 of port p14. when write, set to "0". when read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 figure 1.29.6. port register
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 317 function function select register a0 bit name bit symbol symbol address when reset ps0 03b0 16 00 16 rw ps0_0 ps0_1 port p6 0 function select bit ps0_3 ps0_4 ps0_5 ps0_7 0 : i/o port 1 : uart0 output (rts 0 ) 0 : i/o port 1 : uart0 output (clk 0 output) 0 : i/o port 1 : uart0 output (t x d 0 /sda 0 ) 0 : i/o port 1 : function that was selected in bit4 of function select register b0 0 : i/o port 1 : uart1 output (clk 1 output) 0 : i/o port 1 : uart1 output (t x d 1 /sda 1 ) port p6 1 function select bit port p6 3 function select bit port p6 4 function select bit port p6 5 function select bit port p6 7 function select bit ps0_2 port p6 2 function select bit 0 : i/o port 1 : function that was selected in bit2 of function select register b0 ps0_6 port p6 6 function select bit 0 : i/o port 1 : function that was selected in bit6 of function select register b0 b7 b6 b5 b4 b3 b2 b1 b0 function function select register a1 bit name bit symbol symbol address when reset ps1 03b1 16 00 16 rw ps1_0 ps1_1 port p7 0 function select bit ps1_3 ps1_4 ps1_5 ps1_7 0 : i/o port 1 : function that was selected in bit0 of function select register b1 0 : i/o port 1 : function that was selected in bit1 of function select register b1 0 : i/o port 1 : function that was selected in bit3 of function select register b1 0 : i/o port 1 : function that was selected in bit4 of function select register b1 0 : i/o port 1 : function that was selected in bit5 of function select register b1 0 : i/o port 1 : intelligent i/o group 0 output (outc0 1 /isclk 0 ) port p7 1 function select bit port p7 3 function select bit port p7 4 function select bit port p7 5 function select bit port p7 7 function select bit ps1_6 0 : i/o port 1 : function that was selected in bit6 of function select register b1 port p7 6 function select bit ps1_2 port p7 2 function select bit 0 : i/o port 1 : function that was selected in bit2 of function select register b1 b7 b6 b5 b4 b3 b2 b1 b0 figure 1.29.7. function select register a (1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 318 function function select register a2 bit name bit symbol symbol address when reset ps2 03b4 16 00x00000 2 rw ps2_0 ps2_1 port p8 0 function select bit 0 : i/o port 1 : function that was selected in bit0 of function select register b2 0 : i/o port 1 : function that was selected in bit1 of function select register b2 noting is assigned. when write, set to "0". when read, their contents are indeterminate. port p8 1 function select bit ps2_2 port p8 2 function select bit 0 : i/o port 1 : function that was selected in bit2 of function select register b2 reserve bit must always be "0". reserve bit must always be "0". b7 b6 b5 b4 b3 b2 b1 b0 00 00 function function select register a3 (note) bit name bit symbol symbol address when reset ps3 03b5 16 00 16 rw ps3_0 ps3_1 port p9 0 function select bit ps3_3 ps3_4 ps3_5 ps3_7 0 : i/o port 1 : uart3 output (clk 3 ) 0 : i/o port 1 : function that was selected in bit1 of function select register b3 0 : i/o port 1 : uart3 output (rts 3 ) 0 : i/o port 1 : uart4 output (clk 4 ) 0 : i/o port 1 : function that was selected in bit7 of function select register b3 port p9 1 function select bit port p9 3 function select bit port p9 4 function select bit port p9 5 function select bit port p9 7 function select bit ps3_6 0 : i/o port 1 : uart4 output (t x d 4 /sda 4 ) port p9 6 function select bit ps3_2 port p9 2 function select bit 0 : i/o port 1 : function that was selected in bit2 of function select register b3 0 : i/o port 1 : uart4 output (rts 4 ) note :set bit 2 of protect register (address 000a 16 ) to "1" before rewriting to this register. b7 b6 b5 b4 b3 b2 b1 b0 figure 1.29.8. function select register a (2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 319 function function select register a5 bit name bit symbol symbol address when reset ps5 03b9 16 xxx0 0000 2 rw ps5_0 ps5_1 port p11 0 function select bit 0 : i/o port 1 : intelligent i/o group 1 output (outc1 0 / ist x d1/be1 out ) 0 : i/o port 1 : intelligent i/o group 1 output (outc1 1 / isclk 1 ) note: this register exists in 144-pin version. port p11 1 function select bit ps5_2 port p11 2 function select bit 0 : i/o port 1 : intelligent i/o group 1 output (outc1 2 ) ps5_3 port p11 3 function select bit 0 : i/o port 1 : intelligent i/o group 1 output (outc1 3 ) reserve bit must always be "0". noting is assigned. when write, set to "0". when read, their contents are indeterminate. (note) b7 b6 b5 b4 b3 b2 b1 b0 0 function function select register a6 bit name bit symbol symbol address when reset ps6 03bc 16 00 16 rw ps6_0 ps6_1 port p12 0 function select bit ps6_3 ps6_4 ps6_5 ps6_7 0 : i/o port 1 : intelligent i/o group 3 output (outc3 0 ) 0 : i/o port 1 : intelligent i/o group 3 output (outc3 1 ) 0 : i/o port 1 : intelligent i/o group 3 output (outc3 3 ) 0 : i/o port 1 : intelligent i/o group 3 output (outc3 4 ) 0 : i/o port 1 : intelligent i/o group 3 output (outc3 5 ) 0 : i/o port 1 : intelligent i/o group 3 output (outc3 7 ) port p12 1 function select bit port p12 3 function select bit port p12 4 function select bit port p12 5 function select bit port p12 7 function select bit ps6_6 0 : i/o port 1 : intelligent i/o group 3 output (outc3 6 ) port p12 6 function select bit ps6_2 port p12 2 function select bit 0 : i/o port 1 : intelligent i/o group 3 output (outc3 2 ) note: this register exists in 144-pin version. (note) b7 b6 b5 b4 b3 b2 b1 b0 figure 1.29.9. function select register a (3)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 320 function function select register a7 bit name bit symbol symbol address when reset ps7 03bd 16 00 16 rw ps7_0 ps7_1 port p13 0 function select bit ps7_3 ps7_4 ps7_5 ps7_7 0 : i/o port 1 : intelligent i/o group 2 output (outc2 4 ) 0 : i/o port 1 : intelligent i/o group 2 output (outc2 5 ) 0 : i/o port 1 : intelligent i/o group 2 output (outc2 3 ) 0 : i/o port 1 : intelligent i/o group 2 output (outc2 0 /ist x d 2 /ie out ) 0 : i/o port 1 : intelligent i/o group 2 output (outc2 2 ) 0 : i/o port 1 : intelligent i/o group 2 output (outc2 7 ) port p13 1 function select bit port p13 3 function select bit port p13 4 function select bit port p13 5 function select bit port p13 7 function select bit ps7_6 0 : i/o port 1 : intelligent i/o group 2 output (outc2 1 /isclk 2 ) port p13 6 function select bit ps7_2 port p13 2 function select bit 0 : i/o port 1 : intelligent i/o group 2 output (outc2 6 ) note: this register exists in 144-pin version. (note) b7 b6 b5 b4 b3 b2 b1 b0 function function select register a8 bit name bit symbol symbol address when reset ps8 03a0 16 x0000000 2 rw ps8_0 ps8_1 port p14 0 function select bit 0 : i/o port 1 : intelligent i/o group 1 output (outc1 4 ) 0 : i/o port 1 : intelligent i/o group 1 output (outc1 5 ) noting is assigned. when write, set to "0". when read, their contents are indeterminate. port p14 1 function select bit ps8_2 port p14 2 function select bit 0 : i/o port 1 : intelligent i/o group 1 output (outc1 6 ) 0 : i/o port 1 : intelligent i/o group 1 output (outc1 7 ) ps8_3 port p14 3 function select bit 0 00 reserve bit must always be "0". note: this register exists in 144-pin version. (note) b7 b6 b5 b4 b3 b2 b1 b0 figure 1.29.10. function select register a (4)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 321 function function select register a9 bit name bit symbol symbol address when reset ps9 03a1 16 00 16 rw ps9_0 ps9_1 port p15 0 function select bit ps9_4 ps9_5 0 : i/o port 1 : intelligent i/o group 0 output (outc0 0 / ist x d 0 /be0 out ) 0 : i/o port 1 : intelligent i/o group 0 output (outc0 1 / isclk 0 ) 0 : i/o port 1 : intelligent i/o group 0 output (outc0 4 ) 0 : i/o port 1 : intelligent i/o group 0 output (outc0 5 ) port p15 1 function select bit port p15 4 function select bit port p15 5 function select bit reserve bit must always be "0". reserve bit must always be "0". note: this register exists in 144-pin version. (note) b7 b6 b5 b4 b3 b2 b1 b0 0 00 0 figure 1.29.11. function select register a (5)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 322 function function select register b1 bit name bit symbol symbol address when reset psl1 03b3 16 00 16 rw psl1_0 psl1_1 port p7 0 peripheral function select bit psl1_3 psl1_4 psl1_5 0 : function that was selected in bit0 of function select register c 1 : timer output (ta0 out ) 0 : function that was selected in bit1 of function select register c 1 : uart2 output (st x d2) 0 : function that was selected in bit3 of function select register c 1 : three-phase pwm output (v) 0 : function that was selected in bit4 of function select register c 1 : three-phase pwm output (w) 0 : three-phase pwm output (w) 1 : intelligent i/o group 1 output (outc1 2 ) port p7 1 peripheral function select bit port p7 3 peripheral function select bit port p7 4 peripheral function select bit port p7 5 peripheral function select bit psl1_6 0 : function that was selected in bit6 of function select register c 1 : timer output (ta3 out ) port p7 6 peripheral function select bit psl1_2 port p7 2 peripheral function select bit 0 : function that was selected in bit2 of function select register c 1 : timer output (ta1 out ) reserve bit must always be "0". b7 b6 b5 b4 b3 b2 b1 b0 0 function function select register b0 bit name bit symbol symbol address when reset psl0 03b2 16 00 16 rw psl0_4 port p6 4 peripheral function select bit 0 : uart1 output (rts1) 1 : intelligent i/o group 2 output (outc2 1 /isclk2) psl0_6 port p6 6 peripheral function select bit 0 : uart1 output (scl1) 1 : uart1 output (st x d1) psl0_2 port p6 2 peripheral function select bit 0 : uart0 output (scl0) 1 : uart0 output (st x d0) reserve bit must always be "0". reserve bit must always be "0". reserve bit must always be "0". reserve bit must always be "0". b7 b6 b5 b4 b3 b2 b1 b0 0000 0 figure 1.29.12. function select register b (1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 323 function function select register b2 noting is assigned. when write, set to "0". when read, their contents are indeterminate. bit name bit symbol symbol address when reset psl2 03b6 16 00x00000 2 rw psl2_0 psl2_1 port p8 0 peripheral function select bit 0 : timer output (ta4 out ) 1 : three-phase pwm output (u) port p8 1 peripheral function select bit psl2_2 0 : intelligent i/o group 3 output (outc3 2 ) 1 : can output (can out ) port p8 2 peripheral function select bit b7 b6 b5 b4 b3 b2 b1 b0 0 : three-phase pwm output (u) 1 : intelligent i/o group 3 output (outc3 0 ) reserve bit must always be "0". reserve bit must always be "0". 0 000 function function select register b3 bit name bit symbol symbol address when reset psl3 03b7 16 00 16 rw psl3_1 psl3_3 psl3_4 psl3_5 psl3_7 0 : uart3 output (scl 3 ) 1 : uart3 output (st x d 3 ) 0 : input peripheral function enabled (expect da0 output) 1 : input peripheral function disabled (da0 output) 0 : input peripheral function enabled (expect da1 output) 1 : input peripheral function disabled (da1 output) 0 : input peripheral function enabled (expect anex0 output) 1 : input peripheral function disabled (anex0 output) 0 : uart4 output (scl 4 ) 1 : uart4 output (st x d 4 ) port p9 1 peripheral function select bit port p9 3 peripheral function select bit port p9 4 peripheral function select bit port p9 5 peripheral function select bit port p9 7 peripheral function select bit psl3_6 0 : input peripheral function enabled (expect anex1 output) 1 : input peripheral function disabled (anex1 output) port p9 6 peripheral function select bit psl3_2 port p9 2 peripheral function select bit 0 : uart3 output (t x d 3 /sda 3 ) 1 : intelligent i/o group 2 output (outc2 0 /ie out ) (note) (note) (note) (note) note: although da0, da1, anex0 and anex1 can be used when "0" is set in these bits, the power supply may be increased. b7 b6 b5 b4 b3 b2 b1 b0 reserve bit must always be "0". 0 figure 1.29.13. function select register b (2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 324 function function select register c bit name bit symbol symbol address when reset psc 03af 16 00x00000 2 rw psc_0 psc_3 psc_4 psc_7 0 : uart2 output (t x d 2 /sda 2 ) 1 : intelligent i/o group 2 output (outc2 0 / ist x d 2 /ie out ) 0 : uart2 output (rts 2 ) 1 : intelligent i/o group 1 output (outc1 0 / ist x d 1 /be1 out ) 0 : timer output (ta2 out ) 1 : intelligent i/o group 1 output (outc1 1 / isclk 1 ) 0 : enabled 1 : disabled port p7 0 peripheral function select bit port p7 3 peripheral function select bit port p7 4 peripheral function select bit key input interrupt disable bit psc_6 0 : intelligent i/o group 0 output (outc0 0 /ist x d 0 /be0 out ) 1 : can output (can out ) port p7 6 peripheral function select bit psc_2 port p7 2 peripheral function select bit 0 : uart2 output (clk 2 ) 1 : three-phase pwm output (v) noting is assigned. when write, set to "0". when read, its content is indeterminate. psc_1 port p7 1 peripheral function select bit 0 : uart2 output (scl 2 ) 1 : intelligent i/o group 2 output (outc2 2 ) (note) note: although da0, da1, anex0 and anex1 can be used when "0" is set in this bit, the power supply may be increased. b7 b6 b5 b4 b3 b2 b1 b0 figure 1.29.14. function select register c
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 325 function pull-up control register 0 bit name bit symbol symbol address when reset pur0 03f0 16 00000000 2 rw pu00 pu01 pu02 p0 0 to p0 3 pull-up pu03 pu04 pu05 pu07 pu06 0 : not pulled high 1 : pulled high p0 4 to p0 7 pull-up p1 0 to p1 3 pull-up p1 4 to p1 7 pull-up p2 0 to p2 3 pull-up p2 4 to p2 7 pull-up p3 0 to p3 3 pull-up p3 4 to p3 7 pull-up 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high note: since p0 to p5 operate as the bus in memory expansion mode and microprocessor mode, do not set the pull-up control register. however, it is possible to select pull-up resistance presence to the usable port as i/o port by setting. (note) b7 b6 b5 b4 b3 b2 b1 b0 function pull-up control register 1 bit name bit symbol symbol address when reset pur1 03f1 16 xxxx0000 2 rw pu10 pu11 pu12 p4 0 to p4 3 pull-up pu13 0 : not pulled high 1 : pulled high p4 4 to p4 7 pull-up p5 0 to p5 3 pull-up p5 4 to p5 7 pull-up 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high noting is assigned. when write, set to "0". when read, their contents are indeterminate. note: since p0 to p5 operate as the bus in memory expansion mode and microprocessor mode, do not set the pull-up control register. however, it is possible to select pull-up resistance presence to the usable port as i/o port by setting. (note) b7 b6 b5 b4 b3 b2 b1 b0 figure 1.29.15. pull-up control register (1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 326 function pull-up control register 3 bit name bit symbol symbol address when reset pur3 03db 16 00000000 2 rw pu30 pu31 pu32 p10 0 to p10 3 pull-up pu33 pu34 pu35 pu37 pu36 0 : not pulled high 1 : pulled high p10 4 to p10 7 pull-up p11 0 to p11 3 pull-up p11 4 pull-up p12 0 to p12 3 pull-up p12 4 to p12 7 pull-up p13 0 to p13 3 pull-up p13 4 to p13 7 pull-up 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high <144-pin version> b7 b6 b5 b4 b3 b2 b1 b0 function pull-up control register 2 bit name bit symbol symbol address when reset pur2 03da 16 00000000 2 rw pu20 pu21 pu22 p6 0 to p6 3 pull-up pu23 pu24 pu25 pu27 pu26 0 : not pulled high 1 : pulled high p6 4 to p6 7 pull-up p7 0 to p7 3 pull-up p7 4 to p7 7 pull-up p8 0 to p8 3 pull-up p8 4 to p8 7 pull-up p9 0 to p9 3 pull-up p9 4 to p9 7 pull-up 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high (note 2) (note 3) note 1: since p7 0 and p7 1 are n-channel open drain ports, pull-up is not available for them. note 2: except port p8 5 . (note 1) b7 b6 b5 b4 b3 b2 b1 b0 figure 1.29.16. pull-up control register (2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 327 function pull-up control register 4 bit name bit symbol symbol address when reset pur4 03dc 16 xxxx0000 2 rw pu40 pu41 pu42 p14 0 to p14 3 pull-up pu43 0 : not pulled high 1 : pulled high p14 4 to p14 6 pull-up p15 0 to p15 3 pull-up p15 4 to p15 7 pull-up 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high 0 : not pulled high 1 : pulled high noting is assigned. when write, set to "0". when read, their contents are indeterminate. note: this register exists in 144-pin version.. (note) b7 b6 b5 b4 b3 b2 b1 b0 figure 1.29.17. pull-up control register (3) function pull-up control register 3 bit name bit symbol symbol address when reset pur3 03db 16 00 16 rw pu30 pu31 p10 0 to p10 3 pull-up 0 : not pulled high 1 : pulled high p10 4 to p10 7 pull-up 0 : not pulled high 1 : pulled high reserve bit must always be "0". <100-pin version> b7 b6 b5 b4 b3 b2 b1 b0 00 0000
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 328 function port control register noting is assigned. when write, set to "0". when read, their contents are indeterminate. bit name bit symbol symbol address when reset pcr 03ff 16 xxxxxxx0 2 rw pcr0 port p1 control register 0 : function as common cmos port 1 : function as n-ch open drain port (note 2) note 1: since p1 operates as the data bus in memory expansion mode and microprocessor mode, do not set the port control register. however, it is possible to select cmos port or n-channel open drain pin to the usable port as i/o port by setting. note 2: this function is designed to permanently turn off the pch of the cmos port. it dose not make port p1 a full open drain. therefore, the absolute maximum input voltage rating is [-3 to v cc + 3.0v]. (note 1) b7 b6 b5 b4 b3 b2 b1 b0 figure 1.29.18. port control register and input function select register input function select register symbol address when reset ips 0178 16 00000x00 2 rw bit name function bit symbol b7 b0 ips0 ips1 group 0 input pin select bit 0 isrxd2/ie in function pin select bit ips5 ips6 0 : p6 4 1 : p13 6 assigns functions of inpc0 0 , inpc0 1 /isclk0 and inpc0 2 /isrxd0/be0 in to the following ports. 0 : p7 6, p7 7, p8 0 1 : p15 0, p15 1, p15 2 : p7 1 : p9 1 : p13 5 : must not be set b5 0 0 1 1 b4 0 1 0 1 assigns functions of inpc1 1 /isclk1 and inpc1 2 /isrxd1/be1 in to the following ports. 0 : p7 4, p7 5 1 : p11 1, p11 2 group 1 input pin select bit 1 ips2 0 : input peripheral function is enabled 1 : input peripheral function is disabled p15 input peripheral function select bit isclk2 function pin select bit ips4 ips3 0 : p7 7 1 : p8 3 can in function pin select bit (note) note: although ad input pin can be used when "0" is set in this bit, the power supply may be increased. reserve bit must always be "0".
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 329 pin name connection ports p0 to p15 (excluding p8 5 ) x out (note 2) av ss , v ref , byte av cc after setting for input mode, connect every pin to v ss via a resistance (pull-down); or after setting for output mode, leave these pins open. open connect to v cc connect to v ss note 1: ports p11 to p15 exist in 144-pin version. note 2: with external clock input to x in pin. nmi connect via resistance to v cc (pull-up) (note 1) pin name connection ports p6 to p15 (excluding p8 5 ) av ss , v ref av cc open connect to v cc connect to v ss note 1: ports p11 to p15 exist in 144-pin version. note 2: with external clock input to x in pin. hold, rdy, nmi connect via resistance to v cc (pull-up) bhe, ale, hlda, x out (note 2), bclk after setting for input mode, connect every pin to v ss via a resistance (pull-down); or after setting for output mode, leave these pins open. (note 1) port p0 to p15 (except for p8 5 ) (input mode) (input mode) (output mode) nmi x out av cc byte av ss v ref microcomputer v cc v ss in single-chip mode port p6 to p15 (except for p8 5 ) (input mode) (input mode) (output mode) nmi x out av cc av ss v ref open microcomputer v cc v ss in memory expansion mode or in microprocessor mode hold rdy ale bclk bhe hlda open open open note : ports p11 to p15 exist in 144-pin version. (note) table 1.29.1. example connection of unused pins in single-chip mode table 1.29.2. example connection of unused pins in memory expansion mode and microprocessor mode figure 1.29.19. example connection of unused pins
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 330 table 1.29.3. port p6 output control ps0 register psl0 register bit 0 0: p6 0 must set to "0" ________ 1: uart0 output (rts0) (note) bit 1 0: p6 1 must set to "0" 1: uart0 output (clk0) (note) bit 2 0: p6 2 0: uart0 output (scl0) 1: selected by psl0 register 1: uart0 output (stxd0) bit 3 0: p6 3 must set to "0" 1: uart0 output (txd0/sda0) (note) bit 4 0: p6 4 ________ 0: uart1 output (rts1) 1: selected by psl0 register 1: intelligent i/o group 2 (outc2 1 /isclk2) bit 5 0: p6 5 must set to "0" 1: uart1 output (clk1) (note) bit 6 0: p6 6 0: uart1 output (scl1) 1: selected by psl0 register 1: uart1 output (stxd1) bit 7 0: p6 7 must set to "0" 1: uart1 output (txd1/sda1) (note) ps0 register: function select register a0 psl0 register: function select register b0 note : select "0" in corresponding bit of psl0 register. table 1.29.4. port p7 output control ps1 register psl1 register psc register bit 0 0: p7 0 0: selected by psc register 0: uart2 output (txd2/sda2) 1: selected by psl1 register 1: timer output (ta0 out ) (note 1) 1: intelligent i/o group 2 (outc2 0 /istxd2/ie out ) bit 1 0: p7 1 0: selected by psc register 0: uart2 output (scl2) 1: selected by psl1 register 1: uart2 output (stxd2) (note 1) 1: intelligent i/o group 2 (outc2 2 ) bit 2 0: p7 2 0: selected by psc register 0: uart2 output (clk2) 1: selected by psl1 register 1: timer output (ta1 out ) (note 1) 1: three-phase pwm output (v) bit 3 0: p7 3 0: selected by psc register _______ 0: uart2 output (rts2) 1: selected by psl1 register __ 1: three-phase pwm output (v) (note 1) 1: intelligent i/o group 1 (outc1 0 /istxd1/be1 out ) bit 4 0: p7 4 0: selected by psc register 0: timer output (ta2 out ) 1: selected by psl1 register 1: three-phase pwm output (w) (note 1) 1: intelligent i/o group 1 (outc1 1 /isclk1) bit 5 0: p7 5 ___ 0: three-phase pwm output (w) (note 1) must set to "0" 1: selected by psl1 register 1: intelligent i/o group 1 (outc1 2 ) bit 6 0: p7 6 0: selected by psc register 0: intelligent i/o group 0 (outc0 0 /istxd0/be0 out ) 1: selected by psl1 register 1: timer output (ta3 out ) 1: can output (can out ) bit 7 0: p7 7 must set to "0" 0: key input interrupt signal enabled 1: intelligent i/o group 0 1: key input interrupt signal disabled (outc0 1 /isclk0) ps1 register: function select register a1 psl1 register: function select register b1 psc register: function select register c note 1: select "0" in corresponding bit of psc register. note 2: select "0" in corresponding bit of psl1 register.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 331 table 1.29.5. port p8 output control ps2 register psl2 register bit 0 0: p8 0 0: timer output (ta4 out ) 1: selected by psl2 register 1: three-phase pwm output (u) bit 1 0: p8 1 ____ 0: three-phase pwm output (u) 1: selected by psl2 register 1: intelligent i/o group 3(outc3 0 ) bit 2 0: p8 2 0: intelligent i/o group 3(outc3 2 ) 1: selected by psl2 register 1: can output (can out ) bit 3 to 7 must set to "0" ps2 register: function select register a2 psl2 register: function select register b2 table 1.29.6. port p9 output control ps3 register psl3 register bit 0 0: p9 0 must set to "0" 1: uart3 output (clk3) (note) bit 1 0: p9 1 0: uart3 output (scl3) 1: selected by psl3 register 1: uart3 output (stxd3) bit 2 0: p9 2 0: uart3 output (txd3/sda3) 1: selected by psl3 register 1: intelligent i/o group 2 (outc2 0 /ie out ) bit 3 0: p9 3 0: except da0 output ________ 1: uart3 output (rts3) (note) 1: da0 output bit 4 0: p9 4 0: except da1 output ________ 1: uart4 output (rts4) (note) 1: da1 output bit 5 0: p9 5 0: except anex0 1: uart4 output (clk4) (note) 1: anex0 bit 6 0: p9 6 0: except anex1 1: uart4 output (txd4/sda4) (note) 1: anex1 bit 7 0: p9 7 0: uart4 output (scl4) 1: selected by psl3 register 1: uart4 output (stxd4) ps3 register: function select register a3 psl3 register: function select register b3 note : select "0" in corresponding bit of psl3 register. table 1.29.7. port p11 output control ps5 register bit 0 0: p11 0 1: intelligent i/o group 1(outc1 0 /istxd1/be1 out ) bit 1 0: p11 1 1: intelligent i/o group 1(outc1 1 /isclk1) bit 2 0: p11 2 1: intelligent i/o group 1(outc1 2 ) bit 3 0: p11 3 1: intelligent i/o group 1(outc1 3 ) bit 4 to 7 must set to "0" ps5 register: function select register a5
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 332 table 1.29.8. port p12 output control ps6 register bit 0 0: p12 0 1: intelligent i/o group 3(outc3 0 ) bit 1 0: p12 1 1: intelligent i/o group 3(outc3 1 ) bit 2 0: p12 2 1: intelligent i/o group 3(outc3 2 ) bit 3 0: p12 3 1: intelligent i/o group 3(outc3 3 ) bit 4 0: p12 4 1: intelligent i/o group 3(outc3 4 ) bit 5 0: p12 5 1: intelligent i/o group 3(outc3 5 ) bit 6 0: p12 6 1: intelligent i/o group 3(outc3 6 ) bit 7 0: p12 7 1: intelligent i/o group 3(outc3 7 ) ps6 register: function select register a6 table 1.29.9. port p13 output control ps7 register bit 0 0: p13 0 1: intelligent i/o group 2(outc2 4 ) bit 1 0: p13 1 1: intelligent i/o group 2(outc2 5 ) bit 2 0: p13 2 1: intelligent i/o group 2(outc2 6 ) bit 3 0: p13 3 1: intelligent i/o group 2(outc2 3 ) bit 4 0: p13 4 1: intelligent i/o group 2(outc2 0 /istxd 2 /ie out ) bit 5 0: p13 5 1: intelligent i/o group 2(outc2 2 ) bit 6 0: p13 6 1: intelligent i/o group 2(outc2 1 /isclk 2 ) bit 7 0: p13 7 1: intelligent i/o group 2(outc2 7 ) ps7 register: function select register a7 table 1.29.10. port p14 output control ps8 register bit 0 0: p14 0 1: intelligent i/o group 1(outc1 4 ) bit 1 0: p14 1 1: intelligent i/o group 1(outc1 5 ) bit 2 0: p14 2 1: intelligent i/o group 1(outc1 6 ) bit 3 0: p14 3 1: intelligent i/o group 1(outc1 7 ) bit 4 to 7 must set to "0" ps8 register: function select register a8
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer programmable i/o port 333 table 1.29.11. port p15 output control ps9 register bit 0 0: p15 0 1: intelligent i/o group 0 (outc0 0 /istxd 0 /be out ) bit 1 0: p15 1 1: intelligent i/o group 0 (outc0 1 /isclk 0 ) bit 2 to 3 must set to "0" bit 4 0: p15 4 1: intelligent i/o group 0 (outc0 4 ) bit 5 0: p15 5 1: intelligent i/o group 0 (outc0 5 ) bit 6 to 7 must set to "0" ps9 register: function select register a9
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer vdc 334 vdc when power-supply voltage is 3.3v or under, set the internal vdc (voltage down converter) unused. follow the steps given below to disable the vdc. (1) set bit 3 of the protect register to "1". (2) set the vdc control register 0 to "0f 16 ". (3) set the vdc control register 0 to "8f 16 ". (4) set bit 3 of the protect register to "0". these steps must be performed after reset as immediately as possible with divide-by-8 clock. when the vdc select bit has been set to "11 2 " once, do not set any other values. figure 1.30.1 shows the vdc control register 0. vdc00 vdc01 vdc02 vdc03 vdc05 vdc07 vdc04 (note 2) function note 1: set bit 3 of the protect register (address 000a 16 ) to "1" before rewriting this register. rewriting this register should be performed only when the vdc is to be off. note 2: this bit enables the setting of bit 0 to bit 3. set bit 7 to "0" first, and then write values to bit 0 to bit 3. after that, write "1" to bit 7. the state changes at the time "1" is written to bit 7. vdc control register 0 (note 1) vdc select bit reserved bit vdc enable bit 1 1: vdc unused 0: vdc off 1: vdc on must set to "0" bit name bit symbol symbol address when reset vdc0 001b 16 00 16 rw b1b0 b2 vdc06 do not set any values other than "11". b3 1 1: vdc reference voltage off do not set any values other than "11". vdc reference voltage select bit b7 b6 b5 b4 b3 b2 b1 b0 figure 1.30.1. vdc control register
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer usage precaution 335 usage precaution timer a (timer mode) (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register while reloading gets ffff 16 . reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. timer a (event counter mode) (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register while reloading gets ffff 16 by underflow or 0000 16 by overflow. reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. (2) when stop counting in free run type, set timer again. (3) in the case of using as free-run type , the timer register contents may be unknown when counting begins. if the timer register is set before counting has started, then the starting value will be unknown. ? in the case where the up/down count will not be changed. enable the reload function and write to the timer register before counting begins. rewrite the value to the timer register immediately after counting has started. if counting up, rewrite 0000 16 to the timer register. if counting down, rewrite ffff 16 to the timer register. this will cause the same operation as free-run type mode. ? in the case where the up/down count has changed. first set to reload type operation. once the first counting pulse has occurred, the timer may be changed to free-run type . timer a (one-shot timer mode) (1) setting the count start flag to 0 while a count is in progress causes as follows: ? the counter stops counting and a content of reload register is reloaded. ? the tai out pin outputs l level. ? the interrupt request generated and the timer ai interrupt request bit goes to 1 . (2) the output from the one-shot timer synchronizes with the count source generated internally. there- fore, when an external trigger has been selected, a delay of one cycle of count source as maximum occurs between the trigger input to the tai in pin and the one-shot timer output. (3) the timer ai interrupt request bit goes to 1 if the timer's operation mode is set using any of the following procedures: ? selecting one-shot timer mode after reset. ? changing operation mode from timer mode to one-shot timer mode. ? changing operation mode from event counter mode to one-shot timer mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. (4) if a trigger occurs while a count is in progress, after the counter performs one down count following the reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. to generate a trigger while a count is in progress, generate the second trigger after an elapse longer than one cycle of the timer's count source after the previous trigger occurred.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer usage precaution 336 timer a (pulse width modulation mode) (1) the timer ai interrupt request bit becomes 1 if setting operation mode of the timer in compliance with any of the following procedures: ? selecting pwm mode after reset. ? changing operation mode from timer mode to pwm mode. ? changing operation mode from event counter mode to pwm mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. (2) setting the count start flag to 0 while pwm pulses are being output causes the counter to stop counting. if the tai out pin is outputting an h level in this instance, the output level goes to l , and the timer ai interrupt request bit goes to 1 . if the tai out pin is outputting an l level in this instance, the level does not change, and the timer ai interrupt request bit does not becomes 1 . timer b (timer mode, event counter mode) (1) reading the timer bi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer bi register while reloading gets ffff 16 . reading the timer bi register after setting a value in the timer bi register with a count halted but before the counter starts counting gets a proper value. timer b (pulse period/pulse width measurement mode) (1) if changing the measurement mode select bit is set after a count is started, the timer bi interrupt request bit goes to 1 . (2) when the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. at this time, timer bi interrupt request is not generated. (3) the value of the counter is indeterminate at the beginning of a count. therefore, the timer bi overflow flag may go to 1 and timer bi interrupt request may be generated during the interval between a count start and an effective edge input. stop mode and wait mode ____________ (1) when returning from stop mode by hardware reset, reset pin must be set to l level until main clock oscillation is stabilized. (2) when shifting to wait mode or stop mode, the program stops after reading from the wait instruc- tion and the instruction that sets all clock stop control bits to 1 in the instruction queue. therefore, insert a minimum of 4 nops after the wait instruction and the instruction that sets all clock stop control bits to 1 in order to flush the instruction queue.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer usage precaution 337 a-d converter (1) write to each bit (except bit 6) of a-d i (i=0,1) control register 0, to each bit of a-d i control register 1, and to each bit of a-d i control register 2 when a-d conversion is stopped (before a trigger occurs). in particular, when the vref connection bit is changed from 0 to 1 , start a-d conversion after an elapse of 1 s or longer. (2) when changing a-d operation mode, select analog input pin again. (3) using one-shot mode or single sweep mode read the correspondence a-d register after confirming a-d conversion is finished. (it is known by a- d conversion interrupt request bit.) (4) using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 use the undivided main clock as the internal cpu clock. (5) when f(x in ) is faster than 10 mhz, make the frequency 10 mhz or less by dividing. (6) output impedance of sensor at a-d conversion (reference value) to carry out a-d conversion properly, charging the internal capacitor c shown in figure 1.31.1 has to be completed within a specified period of time t. let output impedance of sensor equivalent circuit be r0, microcomputer s internal resistance be r, precision (error) of the a-d converter be x, and the a- d converter s resolution be y (y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). vc is generally v c = v in {1 C e} and when t = t, v c =v in C v in =v in (1 C ) e = C =ln hence, r0 = C C r with the model shown in figure 1.31.1 as an example, when the difference between v in and v c becomes 0.1lsb, we find impedance r0 when voltage between pins v c changes from 0 to v in -(0.1/1024) v in in time t. (0.1/1024) means that a-d precision drop due to insufficient capacitor charge is held to 0.1lsb at time of a-d conversion in the 10-bit mode. actual error however is the value of absolute precision added to 0.1lsb. when f(x in ) = 10 mhz, t = 0.3 s in the a-d conversion mode with sample & hold. output impedance r0 for sufficiently charging capacitor c within time t is determined as follows. t = 0.3 s, r = 7.8 k ? , c = 3 pf, x = 0.1, and y = 1024 . hence, r0 = CC 7.8 x10 3 3.0 x 10 3 c (r0 +r) t c (r0 + r) t C c (r0 + r) t C y x y x y x y x c ? ln t y x 3.0 x 10 C 12 ? ln 1024 0.1 0.3 x 10 -6
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer usage precaution 338 v c c (3.0pf) v in internal circuit of microprocesso r sensor-equivalent circuit r (7.8k ) r 0 ? thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the a-d con- verter turns out to be approximately 3.0 k ? . tables 1.31.1 and 1.31.2 show output impedance values based on the lsb values. figure 1.31.1 a circuit equivalent to the a-d conversion terminal (7) after a-d conversion is complete, if the cpu reads the a-d register at the same time as the a-d conversion result is being saved to a-d register, wrong a-d conversion value is saved into the a-d register. this happens when the internal cpu clock is selected from divided main clock or sub-clock. when using the one-shot or single sweep mode confirm that a-d conversion is complete before reading the a-d register. (note: when a-d conversion interrupt request bit is set, it shows that a-d conversion is completed.) when using the repeat mode or repeat sweep mode 0 or 1 use the undivided main clock as the internal cpu clock. interrupts (1) setting the stack pointer ? the value of the stack pointer is initialized to 000000 16 immediately after reset. accepting an interrupt before setting a value in the stack pointer may cause runaway. be sure to set a value in the stack pointer before accepting an interrupt. _______ when using the nmi interrupt, initialize the stack pointer at the beginning of a program. regard- _______ ing the first instruction immediately after reset, generating any interrupts including the nmi inter- rupt is prohibited. set an even address to the stack pointer so that operating efficiency is increased. _______ (2) the nmi interrupt _______ ? as for the nmi interrupt pin, an interrupt cannot be prohibited. connect it to the v cc pin via a resistance (pulled-up) if unused. _______ ? the nmi pin also serves as p8 5 , which is exclusively input. reading the contents of the p8 register allows reading the pin value. use the reading of this pin only for establishing the pin level _______ at the time when the nmi interrupt is input. _______ ? signal of "l" level width more than 1 clock of cpu operation clock (bclk) is necessary for nmi pin.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer usage precaution 339 tables 1.31.1. output impedance values based on the lsb values (10-bit mode) reference value tables 1.31.2. output impedance values based on the lsb values (8-bit mode) reference value f(x in ) (mhz) cycle (s) sampling time (s) r (k ? ) c (pf) resolution (lsb) r0max (k ? ) 10 0.1 0.3 (3 x cycle, sample & hold bit is enabled) 7.8 3.0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 3.0 4.5 5.3 5.9 6.4 6.8 7.2 7.5 7.8 8.1 0.4 0.9 1.3 1.7 2.0 2.2 2.4 2.6 2.8 10 0.1 0.2 (2 x cycle, sample & hold bit is disabled) 7.8 3.0 f(x in ) (mhz) cycle (s) sampling time (s) r (k ? ) c (pf) resolution (lsb) r0max (k ? ) 10 0.1 0.3 (3 x cycle, sample & hold bit is enabled) 7.8 3.0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 4.9 7.0 8.2 9.1 9.9 10.5 11.1 11.7 12.1 12.6 0.7 2.1 2.9 3.5 4.0 4.4 4.8 5.2 5.5 5.8 10 0.1 0.2 (2 x cycle, sample & hold bit is disabled) 7.8 3.0
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer usage precaution 340 (3) external interrupt ? edge sense either an l level or an h level of at least 250 ns width is necessary for the signal input to pins _______ _______ int 0 to int 5 regardless of the cpu operation clock. ? level sense either an l level or an h level of 1 cycle of bclk + at least 200 ns width is necessary for the _______ _______ signal input to pins int 0 to int 5 regardless of the cpu operation clock. (when x in =30mhz and no division mode, at least 233 ns width is necessary.) _______ _______ ? when the polarity of the int 0 to int 5 pins is changed, the interrupt request bit is sometimes set to "1". after changing the polarity, set the interrupt request bit to "0". figure 1.31.2 shows the ______ procedure for changing the int interrupt generate factor. set the polarity select bit clear the interrupt request bit to 0 set the interrupt priority level to level 1 to 7 (enable the accepting of inti interrupt request) set the interrupt priority level to level 0 (disable inti interrupt) ______ figure 1.31.2. switching condition of int interrupt request (4) rewrite the interrupt control register ? when a instruction to rewrite the interrupt control register is executed but the interrupt is dis- abled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. this will depend on the instructions. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset dmac (1) do not clear the dma request bit of the dmai request cause select register. in m32c/83, when a dma request is generated while the channel is disabled (note), the dma trans- fer is not executed and the dma request bit is cleared automatically. note :the dma is disabled or the transfer count register is "0". (2) when dma transfer is done by a software trigger, set dsr and drq of the dmai request cause select register to "1" simultaneously using the or instruction. e.g.) or.b #0a0h, dmisl ; dmisl is dmai request cause select register (3) when changing the dmai request cause select bit of the dmai request cause select register, set "1" to the dma request bit, simultaneously. in this case, disable the corresponding dma channel to disabled before changing the dmai request cause select bit. to enable dma at least 8+6xn cycles (n: enabled channel number) following the instruction to write to the dmai request cause select register are needed.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer usage precaution 341 example) when dma request cause is changed to timer a0 and using dma0 in single transfer after dma initial setting push.w r0 ; store r0 register stc dmd0, r0 ; read dma mode register 0 and.b #11111100b, r0l ; clear dma0 transfer mode select bit to "00" ldc r0, dmd0 ; dma0 disabled mov.b #10000011b, dm0sl ; select timer a0 ; (write "1" to dma request bit simultaneously) nop : ldc r0, dmd0 ; dma0 enabled pop.w r0 ; restore r0 register noise (1) a bypass capacitor should be inserted between vcc-vss line for reducing noise and latch-up connect a bypass capacitor (approx. 0.1 f) between the vcc and vss pins using short wiring and thicker circuit traces. precautions for using clk out pin when using the clock output function of p5 3 /clk out pin (f 8 , f 32 or fc output) in single chip mode, use port p5 7 as an input only port (port p5 7 direction register is "0"). although port p5 7 may be set as an output port (port p5 7 direction register is "1"), it will become high impedance and will not output "h" or "l" levels. __________ hold signal __________ when using the hold input while p4 0 to p4 7 and p5 0 to p5 2 are set as output ports in single-chip mode, you must first set all pins for p4 0 to p4 7 and p5 0 to p5 2 as input ports, then shift to microprocessor mode or memory expansion mode. reducing power consumption (1) when a-d conversion is not performed, select the vref not connected with the vref connect bit of a-d control register 1. when a-d conversion is performed, start the a-d conversion at least 1 s or longer after connecting vref. (2) when using an 4 (p10 4 ) to an 7 (p10 7 ), select the input disable of the key input interrupt signal with the key input interrupt disable bit of the function select register c . when selecting the input disable of the key input interrupt signal, the key input interrupt cannot be used. also, the port cannot be input even if the direction register of p10 4 to p10 7 is set to input (the input result becomes undefined). when the input disable of the key input interrupt signal is selected, use all an 4 to an 7 as a-d inputs. (3) when anex0 and anex1 are used, select the input peripheral function disable with port p9 5 and p9 6 input peripheral function select bit of the function select register b3. when the input peripheral function disable is selected, the port cannot be input even if the port direc- tion register is set to input (the input result becomes undefined). also, it is not possible to input a peripheral function except anex0 and anex1. at least 8 + 6 x n cycles (n: enabled channel number)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer usage precaution 342 (4) when d-a converter is not used, set output disabled with the d-a output enable bit of d-a control register and set the d-a register to "00 16 ". (5) when d-a conversion is used, select the input peripheral function disabled with port p9 3 and p9 4 input peripheral function select bit of the function select register b3. when the input peripheral function disabled is selected, the port cannot be input even if the port direction register is set to input (the input result becomes undefined). also, it is not possible to input a peripheral function. dram controller the dram self-refresh operates in stop mode, etc. when shifting to self-refresh, select dram is ignored by the dram space select bit. in the next instruc- tion, simultaneously set the dram space select bit and self-refresh on by self-refresh mode bit. also, insert two nops after the instruction that sets the self-refresh mode bit to "1". do not access external memory while operating in self-refresh. (all external memory space access is inhibited. ) when disabling self-refresh, simultaneously select dram is ignored by the dram space select bit and self-refresh off by self-refresh mode bit. in the next instruction, set the dram space select bit. do not access the dram space immediately after setting the dram space select bit. example) one wait is selected by the wait select bit and 4mb is selected by the dram space select bit shifting to self-refresh ??? mov.b #00000001b,dramcont ;dram is ignored, one wait is selected mov.b #10001011b,dramcont ;set self-refresh, select 4mb and one wait nop ;two nops are needed nop ; ??? disable self-refresh ??? mov.b #00000001b,dramcont ;disable self-refresh, dram ignored, one wait is ;selected mov.b #00001011b,dramcont ;select 4mb and one wait nop ;inhibit instruction to access dram area nop ??? setting the registers the registers shown in table 1.31.3 include indeterminate bit when read. set immidiate to these regis- ters. store the content of the frequently used register to ram, change the content of ram, then transfer to the register.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer usage precaution 343 table 1.31.3 the object registers register name symbol address watchdog timer start register wdts 000e 16 group0 receive input register g0ri 00ec 16 group1 receive input register g1ri 012c 16 group2 si/o transmit buffer register g2tb 016d 16 , 016c 16 uart4 bit rate generator u4brg 02f9 16 uart4 transfer buffer register u4tb 02fb 16 , 02fa 16 timer a1-1 register ta11 0303 16 , 0302 16 timer a2-1 register ta21 0305 16 , 0304 16 timer a4-1 register ta41 0307 16 , 0306 16 dead time timer dtt 030c 16 timer b2 interrupt occurrence frequency set counter ictb2 030d 16 uart3 bit rate generator u3brg 0329 16 uart3 transfer buffer register u3tb 032b 16 , 032a 16 uart2 bit rate generator u2brg 0339 16 uart2 transfer buffer register u2tb 033b 16 , 033a 16 up-down flag udf 0344 16 timer a0 register (note) ta0 0347 16 , 0346 16 timer a1 register (note) ta1 0349 16 , 0348 16 timer a2 register (note) ta2 034b 16 , 034a 16 timer a3 register (note) ta3 034d 16 , 034c 16 timer a4 register (note) ta4 034f 16 , 034e 16 uart0 bit rate generator u0brg 0369 16 uart0 transfer buffer register u0tb 036b 16 , 036a 16 uart1 bit rate generator u1brg 02e9 16 uart1 transfer buffer register u1tb 02eb 16 , 02ea 16 a-d0 control register 2 adcon2 0394 16 note: in one-shot timer mode and pulse width modulation mode. notes on the microprocessor mode and transition after shifting from the micropro- cessor mode to the memory expansion mode / single-chip mode in microprocessor mode, the sfr, internal ram, and external memory space can be accessed. for that reason, the internal rom area cannot be accessed. after the reset has been released and the operation of shifting from the microprocessor mode has started ( h applied to the cnv ss pin), the internal rom area cannot be accessed even if the cpu shifts to the memory expansion mode or single-chip mode. notes on cnvss pin reset at "h" level when the cnvss pin is reset at "h" level, the contents of internal rom cannot be read out.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer electrical characteristics 344 electrical characteristics table 1.32.1. absolute maximum ratings symbol parameter condition rated value unit v cc supply voltage v cc =av cc -0.3 to 6.0 v av cc analog supply voltage v cc =av cc -0.3 to 6.0 v v i input voltage -0.3 to vcc+0.3 v -0.3 to 6.0 v v o output voltage -0.3 to vcc+0.3 v -0.3 to 6.0 v pd power dissipation topr=25 c 500 mw topr operating ambient temperature -20 to 85/-40 to 85 (note 2) c tstg storage temperature -65 to 150 c note 1: ports p11 to p15 exist in 144-pin version. note 2: specify a product of -40 to 85 c to use it. ______________ reset, cnvss, byte, p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 - p6 7 , p7 2 -p7 7 , p8 0 -p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 - p14 6 , p15 0 -p15 7 (note1) , v ref , x in p7 0 , p7 1 p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 - p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note1) , v ref , x in p7 0 , p7 1
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer electrical characteristics 345 table 1.32.2. recommended operating conditions (referenced to v cc = 3.0v to 5.5v at topr = 20 to 85 o c / 40 to 85 o c (note3) unless otherwise specified) standard symbol parameter unit min. typ. max. v cc supply voltage(when vdc-on) 3.0 5.0 5.5 v supply voltage(when vdc-pass through) 3.0 3.3 3.6 v av cc analog supply voltage v cc v v ss supply voltage 0v av ss analog supply voltage 0 v v ih "h" input voltage 0.8vcc vcc v 0.8vcc 6.0 v 0.8vcc vcc v 0.5vcc vcc v v il "l" input voltage 0 0.2vcc v 0 0.2vcc v 0 0.16vcc v i oh(peak) "h" peak output -10.0 ma current i oh(avg) "h" average -5.0 ma output current i ol(peak) "l" peak output 10.0 ma current i ol(avg) "l" average 5.0 ma output current f(x in ) main clock input frequency vdc-on vcc=4.2 to 5.5v 0 30 mhz vcc=3.0 to 4.2v 0 20 mhz vdc-pass through vcc=3.0 to 3.6v 0 20 mhz f(x cin ) sub-clock oscillation frequency 32.768 khz p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 - p7 7 , p8 0 -p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 - p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note5) , x in , ____________ reset, cnvss, byte p7 0 , p7 1 p0 0 -p0 7 , p1 0 -p1 7 (during single-chip mode) p0 0 -p0 7 , p1 0 -p1 7 (during memory-expansion and microprocessor modes) p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 0 - p7 7 , p8 0 -p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 - p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note5) , x in , ____________ reset, cnvss, byte p0 0 -p0 7 , p1 0 -p1 7 (during single-chip mode) p0 0 -p0 7 , p1 0 -p1 7 (during memory-expansion and microprocessor modes) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 - p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 - p14 6 , p15 0 -p15 7 (note5) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 - p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 - p14 6 , p15 0 -p15 7 (note5) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 - p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 - p14 6 , p15 0 -p15 7 (note5) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 - p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 - p14 6 , p15 0 -p15 7 (note5) note 1: the mean output current is the mean value within 100ms. note 2: the total i ol (peak) for ports p0, p1, p2, p8 6 , p8 7 , p9, p10, p11, p14 and p15 must be 80ma max. the total i oh (peak) for ports p0, p1, p2, p8 6 , p8 7 , p9, p10, p11, p14 and p15 must be -80ma max. the total i ol (peak) for ports p3, p4, p5, p6, p7,p8 0 to p8 4 , p12 and p13 must be 80ma max. the total i oh (peak) for ports p3, p4, p5, p6, p7 2 to p7 7 , p8 0 to p8 4 , p12 and p13 must be -80ma max. note 3: specify a product of -40 to 85 c to use it. note 4: the specification of v ih and v il of p8 7 is not when using as x cin but when using programmable input port. note 5: port p11 to p15 exist in 144-pin version.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer electrical characteristics (vcc = 5v) 346 v cc = 5v table 1.32.3. electrical characteristics (referenced to v cc =5v, v ss =0v at topr=25 o c, f(x in )=30mh z unless otherwise specified) standard symbol parameter condition unit min. typ. max. v oh "h" output voltage i oh =-5ma 3.0 v v oh "h" output voltage i oh =-200 a 4.7 v v oh "h" output voltage x out high power i oh =-1ma 3.0 v low power i oh =-0.5ma 3.0 v "h" output voltage x cout no load applied 3.0 v v ol "l" output voltage i oh =5ma 2.0 v v ol "l" output voltage i oh =200 a 0.45 v v ol "l" output voltage x out high power i ol =1ma 2.0 v low power i ol =0.5ma 2.0 v "l" output voltage x cout no load applied 0 v v t+ -v t- hysteresis 0.2 1.0 v v t+ -v t- hysteresis 0.2 1.8 v i ih "h" input current v i =5v 5.0 a i il "l" input current v i =0v -5.0 a r pullup pull-up resistance v i =0v 30 50 167 k ? rf xin feedback resistance x in 1.5 m ? rf xcin feedback resistance x cin 10 m ? v ram ram retention voltage vdc-on 2.5 v i cc power supply f(x in )=30mhz, square wave, no division 38 54 ma current f(x cin )=32khz, with wait instruction executed 470 a when clock is stopped topr=25 o c 0.4 20 a note 1: port p11 to p15 exist in 144-pin version. p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note1) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note1) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note1) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note1) __________ _______ ________ hold, rdy, ta0 in -ta4 in , tb0 in -tb5 in , int0- ________ ________ ________ int5, ad trg , cts0-cts4, clk0-clk4, _______ ______ ______ ta0 out -ta4 out , nmi, ki0-ki3, rxd0-rxd4, scl0-scl4, sda0-sda4 ___________ reset p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 - p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note1) , ___________ x in , reset, cnvss, byte p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 - p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note1) , ___________ x in , reset, cnvss, byte p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note1) measuring condition: in sigle-chip mode, the out- put pins are open and other pins are vss.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer electrical characteristics (vcc = 5v) 347 v cc = 5v table 1.32.4. a-d conversion characteristics (referenced to v cc = av cc = v ref = 5v, vss = av ss = 0v at topr = 25 o c, f(x in ) = 30mh z unless otherwise specified) s standard min. typ. max. resolution integral nonlinearity error bits lsb v ref = v cc 3 10 symbol parameter measuring condition unit r ladder t conv ladder resistance conversion time (10bit) reference voltage analog input voltage v v ia v ref v 0 2 10 v cc v ref 40 3.3 conversion time (8bit) 2.8 t conv t samp sampling time 0.3 v ref = v cc offset error an 0 to an 7 an ex0 , an ex1 external op-amp connection mode lsb lsb 7 gain error 3 lsb min. typ. max. t su r o resolution absolute accuracy setup time output resistance reference power supply input current bits % ma i vref 1.0 1.5 8 3 symbol parameter measuring condition unit 20 10 4 s ( note ) standard s s 3 note: divide the frequency if f(x in ) exceeds 10 mhz, and make ? ad equal to or lower than 10 mhz. v ref = v cc = 5v k ? k ? inl dnl differential nonlinearity error lsb 1 table 1.32.5. d-a conversion characteristics (referenced to v cc = v ref = 5v, v ss = av ss = 0v at topr = 25 o c, f(x in ) = 30mh z unless otherwise specified) note: this applies when using one d-a converter, with the d-a register for the unused d-a converter set to 00 16 . the a-d converter's ladder resistance is not included. also, when the vref is unconnected at the a-d control register 1, i vref is sent.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 348 timing requirements (referenced to v cc = 5v, v ss = 0v at topr = 25 o c unless otherwise specified) table 1.32.6. external clock input (note) (note) (note) 26 26 0 0 30 0 25 max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h) t w(l) t f parameter symbol unit standard 5 33 13 13 5 min. data input setup time ns t su(db-bclk) t su(rdy-bclk ) parameter symbol unit max. standard ns rdy input setup time data input hold time ns t h(rd-db) t h(bclk -rdy) ns rdy input hold time ns hold input setup time t su(hold-bclk ) ns hold input hold time t h(bclk-hold ) data input access time (rd standard, no wait) ns t ac1(rd-db) ns ns t ac2(rd-db) t ac3(rd-db) data input access time (rd standard, with wait) data input access time (rd standard, when accessing multiplex bus area) ns t d(bclk-hlda ) hlda output delay time t ac1(rd C db) = f (bclk) x 2 C 35 10 9 [ns] t ac2(rd C db) = f (bclk) x 2 C 35 10 x m 9 [ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively) (note) data input access time (ad standard, cs standard, no wait) ns t ac1(ad-db) (note) ns t ac2(ad-db) data input access time (ad standard, cs standard, with wait) (note) ns t ac3(ad-db) data input access time (ad standard, cs standard, when accessing multiplex bus area) t ac1(ad C db) = f (bclk) C 35 10 9 [ns] t ac2(ad C db) = C 35 10 x n 9 [ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively) t ac3(rd C db) = f (bclk) x 2 C 35 10 x m 9 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) t ac3(ad C db) = f (bclk) x 2 C 35 10 x n 9 [ns] (n=5 and 7 when 2 wait and 3 wait, respectively) note: calculated according to the bclk frequency as follows: note that inserting wait or using lower operation frequency f(bclk) is needed when calculated value is negative. (note) ns t ac4(cas-db) data input access time (cas standard, dram access) (note) ns t ac4(ras-db) data input access time (ras standard, dram access) (note) ns t ac4(cad-db) data input access time (cad standard, dram access) t ac4(ras C db) = f (bclk) x 2 C 35 10 x m 9 [ns] (m=3 and 5 when 1 wait and 2 wait, respectively) t ac4(cas C db) = C 35 10 x n 9 [ns] (n=1 and 3 when 1 wait and 2 wait, respectively) t ac4(cad C db) = f (bclk) C 35 10 x l 9 [ns] (l=1 and 2 when 1 wait and 2 wait, respectively) f (bclk) f (bclk) x 2 ns 0 t h(cas -db) data input hold time table 1.32.7. memory expansion and microprocessor modes v cc = 5v
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 349 timing requirements (referenced to v cc = 5v, v ss = 0v at topr = 25 o c unless otherwise specified) table 1.32.8. timer a input (count input in event counter mode) table 1.32.9. timer a input (gating input in timer mode) table 1.32.10. timer a input (external trigger input in one-shot timer mode) table 1.32.11. timer a input (external trigger input in pulse width modulation mode) table 1.32.12. timer a input (up/down input in event counter mode) v cc = 5v standard max. ns tai in input low pulse width t w(tal) min. ns ns unit standard max. min. ns ns ns unit standard max. min. ns ns ns unit standard max. min. ns ns unit standard max. min. ns ns ns unit ns ns tai in input high pulse width t w(tah) parameter symbol tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width symbol parameter t c(ta) tai in input cycle time tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-tin) t h(tin-up) 40 100 40 400 200 200 200 100 100 100 100 2000 1000 1000 400 400
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 350 timing requirements (referenced to v cc = 5v, v ss = 0v at topr = 25 o c unless otherwise specified) table 1.32.13. timer b input (count input in event counter mode) table 1.28.14. timer b input (pulse period measurement mode) table 1.32.15. timer b input (pulse width measurement mode) table 1.32.16. a-d trigger input table 1.32.17. serial i/o _______ table 1.32.18. external interrupt inti inputs v cc = 5v ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 100 40 40 80 80 200 400 200 200 400 200 200 1000 125 250 250 200 100 100 0 30 90 80
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 351 switching characteristics (referenced to v cc = 5v, v ss = 0v at topr = 25 o c, cm15 = 1 unless otherwise specified) v cc = 5v figure 1.32.1 table 1.32.19. memory expansion mode and microprocessor mode (no wait) symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 18 ns t h(bclk-ad) address output hold time (bclk standard) -3 ns t h(bclk-cs) chip select output hold time (bclk standard) -3 ns t d(bclk-ale) ale signal output delay time 18 ns t h(bclk-ale) ale signal output hold time C 2 ns t d(bclk-rd) rd signal output delay time 18 ns t h(bclk-rd) rd signal output hold time -5 ns t d(bclk-wr) wr signal output delay time 18 ns t h(bclk-wr) wr signal output hold time -3 ns t h(wr-db) data output hold time (wr standard) (note) ns t d(db-wr) data output delay time (wr standard) ns (note) note: calculated according to the bclk frequency as follows: t d(db C wr) = f (bclk) 10 9 C 20 [ns] t d(bclk-cs) chip select output delay time 18 ns t h(rd-ad) address output hold time (rd standard) 0 ns t h(wr-ad) address output hold time (wr standard) (note) ns t h(rd-cs) chip select output hold time (rd standard) 0 ns t h(wr-cs) chip select output hold time (wr standard) (note) ns t h(wr C db) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C cs) = f (bclk) x 2 10 9 C 10 [ns] t w(wr) wr signal width ns (note) t w(wr) = f (bclk) x 2 10 9 C 15 [ ns ]
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 352 switching characteristics (referenced to v cc = 5v, v ss = 0v at topr = 25 o c unless otherwise specified) v cc = 5v figure 1.32.1 table 1.32.20. memory expansion mode and microprocessor mode (with wait, accessing external memory) symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 18 ns t h(bclk-ad) address output hold time (bclk standard) C 3 ns t h(bclk-cs) chip select output hold time (bclk standard) C 3 ns t d(bclk-ale) ale signal output delay time 18 ns t h(bclk-ale) ale signal output hold time C 2 ns t d(bclk-rd) rd signal output delay time 18 ns t h(bclk-rd) rd signal output hold time C 5 ns t d(bclk-wr) wr signal output delay time 18 ns t h(bclk-wr) wr signal output hold time C 3 ns t h(wr-db) data output hold time (wr standard) (note) ns t d(db-wr) data output delay time (wr standard) ns (note) note: calculated according to the bclk frequency as follows: [ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively) t d(bclk-cs) chip select output delay time 18 ns t h(rd-ad) address output hold time (rd standard) 0 ns t h(wr-ad) address output hold time (wr standard) (note) ns t h(rd-cs) chip select output hold time (rd standard) 0 ns t h(wr-cs) chip select output hold time (wr standard) (note) ns t d(db C wr) = f (bclk) 10 x n 9 C 20 t h(wr C db) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C cs) = f (bclk) x 2 10 9 C 10 [ns] t w(wr) wr signal width (note) ns [ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively) t w( wr) = 10 x n 9 C 15 f ( bclk ) x 2
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 353 switching characteristics (referenced to v cc = 5v, v ss = 0v at topr = 25 o c unless otherwise specified) v cc = 5v table 1.32.21. memory expansion mode and microprocessor mode (with wait, accessing external memory, multiplex bus area selected) figure 1.32.1 symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 18 ns t h(bclk-ad) address output hold time (bclk standard) -3 ns t h(bclk-cs) chip select output hold time (bclk standard) -3 ns t d(bclk-ale) ale signal output delay time (bclk standard) 18 ns t h(bclk-ale) ale signal output hold time (bclk standard) C 2 ns t d(bclk-rd) rd signal output delay time 18 ns t h(bclk-rd) rd signal output hold time -5 ns t d(bclk-wr) wr signal output delay time 18 ns t h(bclk-wr) wr signal output hold time -3 ns t h(wr-db) data output hold time (wr standard) (note) ns t d(db-wr) data output delay time (wr standard) ns (note) note: calculated according to the bclk frequency as follows: t d(db C wr) = 10 x m 9 C 25 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) t d(bclk-cs) chip select output delay time 18 ns t h(rd-ad) address output hold time (rd standard) (note) ns t h(wr-ad) address output hold time (wr standard) (note) ns t h(rd-cs) chip select output hold time (rd standard) ns t h(wr-cs) chip select output hold time (wr standard) (note) ns t h(rd C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(rd C cs) = f (bclk) x 2 10 9 C 10 [ns] t d(ad-ale) ale signal output delay time (address standard) ns t h(ale-ad) ale signal output hold time (address standard) ns t dz(rd-ad) address output flowting start time ns (note) (note) 8 t h(wr C cs) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C db) = f (bclk) x 2 10 9 C 10 [ns] t d(ad C ale) = f (bclk) x 2 10 9 C 20 [ns] t h(ale C ad) = f (bclk) x 2 10 9 C 10 [ns] f (bclk) x 2 (note)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 354 switching characteristics (referenced to v cc = 5v, v ss = 0v at topr = 25 o c unless otherwise specified) v cc = 5v table 1.32.22. memory expansion mode and microprocessor mode (with wait, accessing external memory, dram area selected) symbol standard measuring condition max. min. parameter unit t d(bclk-rad) row address output delay time 18 ns t h(bclk-rad) row address output hold time (bclk standard) -3 ns t d(bclk-ras) ras output delay time (bclk standard) -3 ns t su(db-cas) cas output setup time after db output 18 ns t h(bclk-db) db signal output hold time (bclk standard) (note) ns 18 t d(bclk-cas) cas output delay time (bclk standard) -3 ns t h(bclk-cas) cas output hold time (bclk standard) (note) ns t d(bclk-dw) dw output delay time (bclk standard) ns -7 note: calculated according to the bclk frequency as follows: t su(cas C ras) = f ( bclk ) x 2 10 9 C 13 [ ns ] t h(ras-rad) row address output hold time after ras output 18 ns t d(bclk-cad) string address output delay time -3 ns t h(bclk-cad) string address output hold time (bclk standard) (note) ns t h(bclk-ras) ras output hold time (bclk standard) ns t rp ras "h" hold time ns t h(ras C rad) = f (bclk) x 2 10 9 C 13 [ns] t rp = f (bclk) x 2 10 9 x 3 C 20 [ns] t su(cas-ras) cas output setup time before ras output (refresh) 18 ns (note) t su(db C cas) = f (bclk) 10 9 C 20 [ns] t h(bclk-dw) dw output hold time (bclk standard) ns -5 figure 1.32.1
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 355 figure 1.32.1. port p0 to p15 measurement circuit p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf p14 p13 p12 p15 p11
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 356 bclk ale -2ns.min rd 18ns.max -5ns.min hi-z db 0ns.min 0ns.min t d(bclk-ale) t h(bclk-ale) t su(db-bclk) t d(bclk-rd) 26ns.min *1 csi t d(bclk-cs) 18ns.max *1 adi t h(bclk-ad) -3ns.min t h(bclk-cs) -3ns.min bhe tcyc t d(bclk-ad) 0ns.min t ac1(ad-db) *2 t ac1(rd-db) =(tcyc/2-35)ns.max t ac1(ad-db) =(tcyc-35)ns.max wr,wrl, wrh 18ns.max -3ns.min bclk csi t d(bclk-cs) 18ns.max adi t d(bclk-ad) 18ns.max t d(bclk-ale) -3ns.min -3ns.min tcyc bhe dbi t d(bclk-wr) ale 18ns.max -2ns.min t h(wr-db) *3 t d(db-wr) =(tcyc-20)ns.min t h(wr-db) =(tcyc/2-10)ns.min t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min t w(wr) =(tcyc/2-15)ns.min vcc=5v t h(bclk-rd) t h(rd-db) t h(rd-ad) t h(rd-cs) t h(bclk-wr) t h(bclk-ale) t h(bclk-ad) t h(bclk-cs) t h(wr-cs) *3 t h(wr-ad) *3 t w(wr) *3 t ac1(rd-db) *2 18ns.max *1 read timing write timing ( written by 2 cycles in selecting no wait) *3:it depends on operation frequency. measuring conditions ? v cc =5v10% ? input timing voltage :determined with v ih =2.5v, v il =0.8v ? output timing voltage :determined with v oh =2.0v, v ol =0.8v memory expansion mode and microprocessor mode (without wait) *1:it is a guarantee value with being alone. 35ns.max garantees as t d(bclk-ad) +t su(db-bclk) . *2:it depends on operation frequency. 18ns.max t d(db-wr) *3 figure 1.32.2. v cc =5v timing diagram (1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 357 bclk ale 18ns.max -2ns.min rd 18ns.max -5ns.min hi-z db 0ns.min 0ns.min t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) 26ns.min*1 t ac2(rd-db)*2 csi t d(bclk-cs) 18ns.max*1 adi 18ns.max*1 t h(bclk-ad) -3ns.min t h(bclk-cs) -3ns.min bhe tcyc t d(bclk-ad) t ac2(ad-db)*2 t ac2(rd-db) =(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) t ac2(ad-db) =(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) wr,wrl, wrh 18ns.max -3ns.min bclk csi 18ns.max adi 18ns.max -3ns.min -3ns.min tcyc bhe dbi t d(bclk-wr) ale 18ns.max -2ns.min vcc=5v t h(bclk-rd) t h(rd-db) t su(db-bclk) t h(rd-cs) 0ns.min t d(bclk-cs) t d(bclk-ad) t d(bclk-ale) t h(bclk-ad) t h(bclk-cs) t h(wr-cs)*3 t d(db-wr)*3 t h(wr-db)*3 t h(wr-ad)*3 t d(db-wr) =(tcyc x n-20)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) t h(wr-db) =(tcyc/2-10)ns.min t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min t w(wr) =(tcyc/2 x n-15)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) *3:it depends on operation frequency. measuring conditions ? v cc =5v10% ? input timing voltage :determined with v ih =2.5v, v il =0.8v ? output timing voltage :determined with v oh =2.0v, v ol =0.8v *1:it is a guarantee value with being alone. 35ns.max garantees as t d(bclk-ad) +t su(db-bclk) . *2:it depends on operation frequency. t h(bclk-ale) read timing write timing ( written by 2 cycles in selecting no wait) memory expansion mode and microprocessor mode (with wait) t h(rd-ad) t w(wr)*3 t h(bclk-wr) figure 1.32.3. v cc =5v timing diagram (2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 358 bclk csi 18ns.max adi 18ns.max rd 18ns.max -5ns.min t h(bclk-ad) -3ns.min -3ns.min bhe adi /dbi 0ns.min 18ns.max -3ns.min bclk csi 18ns.max adi 18ns.max -3ns.min -3ns.min tcyc bhe adi /dbi data output wr,wrl, wrh address address data input 26ns.min t d(bclk-rd) t h(wr-cs) *2 address t d(ad-ale) *2 address t su(db-bclk) t ac3(rd-db) *1 t dz(rd-ad) 8ns.max ale -2ns.min t d(bclk-ale) 18ns.max t d(ad-ale) =(tcyc/2-20)ns.min t h(ale-ad) =(tcyc/2-10)ns.min, t h(rd-ad) =(tcyc/2-10)ns.min, t h(rd-cs) =(tcyc/2-10)ns.min t ac3(rd-db) =(tcyc/2 x m-35)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.) t ac3(ad-db) =(tcyc/2 x n-35)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.) ale 18ns.max -2ns.min t d(bclk-ale) t h(ale-ad) *2 t d(ad-ale) =(tcyc/2-20)ns.min t h(ale-ad) =(tcyc/2-10)ns.min, t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min, t h(wr-db) =(tcyc/2-10)ns.min t d(db-wr) =(tcyc/2 x m-25)ns.min (m=3 and 5 when 2 wait and 3 wait, respectively.) vcc=5v t d(bclk-cs) t d(ad-ale) *1 t h(ale-ad) *1 t h(bclk-rd) t h(rd-ad) *1 t h(rd-db) t d(bclk-ad) t h(bclk-cs) t h(rd-cs) *1 t d(bclk-wr) t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t h(bclk-ad) t h(bclk-cs) t h(wr-ad) *2 t d(db-wr) *2 t h(wr-db) *2 t h(bclk-ale) t h(bclk-ale) tcyc *2:it depends on operation frequency. measuring conditions ? v cc =5v10% ? input timing voltage :determined with v ih =2.5v, v il =0.8v ? output timing voltage :determined with v oh = 2.0v, v ol = 0.8v *1:it depends on operation frequency. read timing write timing (written by 2 cycles in selecting no wait) memory expansion mode and microprocessor mode (when accessing external memory area with wait, and select multiplexed bus) ) t ac3(ad-db) *1 figure 1.32.4. v cc =5v timing diagram (3)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 359 figure 1.32.5. v cc =5v timing diagram (4) bclk dw db mai t d(bclk-ras) + t su(db-bclk) t d(bclk-cas) + t su(db-bclk) t d(bclk-cad) + t su(db-bclk) t ac4(ras-db) =(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.) t ac4(cas-db) =(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.) t ac4(cad-db) =(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.) t h(ras-rad) =(tcyc/2-13)ns.min t rp =(tcyc/2 x 3-20)ns.min vcc=5v ras casl cash hi-z t ac4(cas-db)*2 18ns.max t h(bclk-cad) -3ns.min tcyc t d(bclk-rad) t ac4(ras-db)*2 row address string address t h(bclk-rad) -3ns.min 18ns.max*1 t d(bclk-cad) 18ns.max*1 t d(bclk-ras) 18ns.max*1 t d(bclk-cas) t h(ras-rad)*2 t rp*2 t ac4(cad-db)*2 t h(bclk-ras) -3ns.min t h(bclk-cas) -3ns.min 0ns.min t su(db-bclk) 26ns.min*1 t h(cas-db) *2:it depends on operation frequency. measuring conditions ? v cc =5v10% ? input timing voltage :determined with v ih =2.5v, v il =0.8v ? output timing voltage :determined with v oh =2.0v, v ol =0.8v read timing memory expansion mode and microprocessor mode (when accessing dram area) *1:it is a guarantee value with being alone. 35ns.max garantees as follows:
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 360 bclk dw db mai t h(ras-rad) =(tcyc/2-13)ns.min t rp =(tcyc/2 x 3-20)ns.min t su(db-cas) =(tcyc-20)ns.min vcc=5v ras casl cash hi-z t h(bclk-db) -7ns.min 18ns.max t h(bclk-cad) -3ns.min tcyc t d(bclk-rad) t h(bclk-rad) -3ns.min 18ns.max t d(bclk-cad) 18ns.max t d(bclk-ras) 18ns.max t d(bclk-cas) t h(ras-rad)*1 t rp*1 18ns.max t d(bclk-dw) t su(db-cas)*1 t h(bclk-ras) -3ns.min t h(bclk-cas) -3ns.min t h(bclk-dw) -5ns.min row address string address *1:it depends on operation frequency. measuring conditions ? v cc =5v10% ? input timing voltage :determined with v ih =2.5v, v il =0.8v ? output timing voltage :determined with v oh =2.0v, v ol =0.8v write timing memory expansion mode and microprocessor mode (when accessing dram area) figure 1.32.6. v cc =5v timing diagram (5)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 361 tcyc 18ns.max t d(bclk-ras) 18ns.max t d(bclk-cas) t h(bclk-ras) -3ns.min t h(bclk-cas) -3ns.min t su(cas-ras)*1 18ns.max t cyc t d(bclk-cas) t su(cas-ras)*1 t h(bclk-ras) -3ns.min t h(bclk-cas) -3ns.min 18ns.max t d(bclk-ras) bclk dw t su(cas-ras) =(tcyc/2-13)ns.min vcc=5v ras casl cash bclk dw t su(cas-ras) =(tcyc/2-13)ns.min ras casl cash *1:it depends on operation frequency. measuring conditions ? v cc =5v10% ? input timing voltage :determined with v ih =2.5v, v il =0.8v ? output timing voltage :determined with v oh =2.0v, v ol =0.8v refresh timing (cas before ras refresh) memory expansion mode and microprocessor mode *1:it depends on operation frequency. refresh timing (self-refresh) figure 1.32.7. v cc =5v timing diagram (6)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 362 figure 1.32.8. v cc =5v timing diagram (7) t su(d C c) tai in input tai out input during event counter mode tbi in input clki txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) t h(t in C up) t su(up C t in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) inti input ad trg input
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 363 figure 1.32.9. v cc =5v timing diagram (8) t h(bclk C hold) t su(hold C bclk) t d(bclk C hlda) t d(bclk C hlda) hi C z measuring conditions : ? v cc = 5v10% ? input timing voltage : determined with v ih =4.0v, v il =1.0v ? output timing voltage : determined with v oh =2.5v, v ol =2.5v memory expansion mode and microprocessor mode bclk hold input hlda output p0, p1, p2, p3, p4, p5 0 to p5 2 (valid with or without wait) (valid only with wait) rdy input t su(rdy C bclk) t h(bclk C rdy) bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus) regardless of the level of the byte pin input and the setting of the port p4 0 to p4 3 function select bit (pm06) of the processor mode register 0, all ports above become the high-impedance state. note:
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer electrical characteristics (vcc = 3v) 364 v cc = 3v electrical characteristics (vcc = 3v) table 1.32.23. electrical characteristics (referenced to v cc =3.3v, v ss =0v at topr=25 o c, f(x in )=20mh z unless otherwise specified) standard symbol parameter condition unit min. typ. max. v oh "h" output voltage i oh =-1ma 2.7 v v oh "h" output voltage x out high power i oh =-0.1ma 2.7 v low power i oh =-50 a 2.7 v "h" output voltage x cout no load applied 3.0 v v ol "l" output voltage i ol =1ma 0.5 v ol "l" output voltage x out high power i ol =0.1ma 0.5 v low power i ol =50 a 0.5 v "l" output voltage x cout no load applied 0 v v t+ -v t- hysteresis 0.2 1.0 v v t+ -v t- hysteresis 0.2 1.8 v i ih "h" input current v i =3v 4.0 a i il "l" input current v i =0v -4.0 a r pullup pull-up resistance v i =0v 66 120 500 k ? rf xin feedback resistance x in 3.0 m ? rf xcin feedback resistance x cin 20.0 m ? v ram ram retention voltage vdc-on 2.5 v vdc-pass through 2.0 v i cc power supply f(x in )=20mhz, square wave, no division 26 38 ma current f(x cin )=32khz, with wait, vdc-pass through 5.0 a f(x cin )=32khz, with wait, vdc-on 340 a when clock is stopped topr=25 o c 0.4 20 a note 1: port p11 to p15 exist in 144-pin version. p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note1) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note1) __________ _______ ________ hold, rdy, ta0 in -ta4 in , tb0 in -tb5 in , int0- ________ ________ ________ int5, ad trg , cts0-cts4, clk0-clk4, _______ ______ ______ ta0 out -ta4 out , nmi, ki0-ki3, rxd0-rxd4, scl0-scl4, sda0-sda4 ___________ reset p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note1) , ___________ x in , reset, cnvss, byte p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note1) , ___________ x in , reset, cnvss, byte p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 ? `p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 (note1) measuring condition: in sigle-chip mode, the output pins are open and other pins are vss.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer electrical characteristics (vcc = 3v) 365 table 1.32.24. a-d conversion characteristics (referenced to v cc = av cc = v ref = 3v, v ss = av ss = 0v at topr = 25 o c, f(x in ) = 20mh z unless otherwise specified) v cc = 3v table 1.32.25. d-a conversion characteristics (referenced to v cc = v ref = 3v, v ss = av ss = 0v, at topr = 25 o c, f(x in ) = 20mh z unless otherwise specified) note :this applies when using one d-a converter, with the d-a register for the unused d-a converter set to 00 16 . the a-d converter's ladder resistance is not included. also, the vref is unconnected at the a-d control register 1, iv ref is sent. standard min. typ. max t su r o resolution absolute accuracy setup time output resistance reference power supply input current bits % ma i vref 1.0 1.0 8 3 symbol parameter measuring condition unit 20 10 4 (note) standard min. typ. max resolution bits lsb v ref = v cc 2 10 symbol parameter measuring condition unit no s&h function(8-bit) s r ladder ladder resistance reference voltage analog input voltage v v ia v ref v 0 2.7 10 v cc v ref 40 conversion time (8bit) 9.8 t conv v ref = v cc s k ? k ? lsb 1 lsb 2 lsb 2 integral nonlinearity error differential nonlinearity error no s&h function(8-bit) no s&h function(8-bit) no s&h function(8-bit) offset error gain error isl dsl s&h: sample and hold note: divide the frequency if f(x in ) exceeds 10 mhz, and make ? ad equal to or lower than 10 mhz.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 366 timing requirements (referenced to v cc = 3v, v ss = 0v at topr = 25 o c unless otherwise specified) (note) (note) (note) 30 40 0 0 60 0 25 max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h) t w(l) t f parameter symbol unit standard 5 50 22 22 5 min. data input setup time ns t su(db-bclk) t su(rdy-bclk ) parameter symbol unit max. standard ns rdy input setup time data input hold time ns t h(rd-db) t h(bclk -rdy) ns rdy input hold time ns hold input setup time t su(hold-bclk ) ns hold input hold time t h(bclk-hold ) data input access time (rd standard, no wait) ns t ac1(rd-db) ns ns t ac2(rd-db) t ac3(rd-db) data input access time (rd standard, with wait) data input access time (rd standard, when accessing multiplex bus area) ns t d(bclk-hlda ) hlda output delay time t ac1(rd C db) = f (bclk) x 2 C 35 10 9 [ns] t ac2(rd C db) = f (bclk) x 2 C 35 10 x m 9 [ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively) (note) data input access time (ad standard, cs standard, no wait) ns t ac1(ad-db) (note) ns t ac2(ad-db) data input access time (ad standard, cs standard, with wait) (note) ns t ac3(ad-db) data input access time (ad standard, cs standard, when accessing multiplex bus area) t ac1(ad C db) = f (bclk) C 35 10 9 [ns] t ac2(ad C db) = C 35 10 x n 9 [ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively) t ac3(rd C db) = f (bclk) x 2 C 35 10 x m 9 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) t ac3(ad C db) = f (bclk) x 2 C 35 10 x n 9 [ns] (n=5 and 7 when 2 wait and 3 wait, respectively) note: calculated according to the bclk frequency as follows: note that inserting wait or using lower operation frequency f(bclk) is needed when calculated value is negative. (note) ns t ac4(cas-db) data input access time (cas standard, dram access) (note) ns t ac4(ras-db) data input access time (ras standard, dram access) (note) ns t ac4(cad-db) data input access time (cad standard, dram access) t ac4(ras C db) = f (bclk) x 2 C 35 10 x m 9 [ns] (m=3 and 5 when 1 wait and 2 wait, respectively) t ac4(cas C db) = C 35 10 x n 9 [ns] (n=1 and 3 when 1 wait and 2 wait, respectively) t ac4(cad C db) = f (bclk) C 35 10 x l 9 [ns] (l=1 and 2 when 1 wait and 2 wait, respectively) f (bclk) f (bclk) x 2 0 data input hold time ns t h(cas-db) v cc = 3v table 1.32.26. external clock input table 1.32.27. memory expansion and microprocessor modes
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 367 v cc = 3v timing requirements (referenced to v cc = 3v, v ss = 0v at topr = 25 o c unless otherwise specified) standard max. min. unit parameter symbol ns t w(tal) tai in input low pulse width 40 ns t c(ta) tai in input cycle time 100 ns t w(tah) tai in input high pulse width 40 standard max. min. unit parameter symbol ns t c(ta) tai in input cycle time 400 ns t w(tah) tai in input high pulse width 200 ns t w(tal) tai in input low pulse width 200 standard max. min. unit parameter symbol ns t c(ta) tai in input cycle time 200 ns t w(tah) tai in input high pulse width 100 ns t w(tal) tai in input low pulse width 100 standard max. min. unit parameter symbol ns t w(tah) tai in input high pulse width 100 ns t w(tal) tai in input low pulse width 100 standard max. min. unit parameter symbol ns t c(up) tai out input cycle time 2000 ns t w(uph) tai out input high pulse width 1000 ns t w(upl) tai out input low pulse width 1000 ns t su(up-t in ) tai out input setup time 400 ns t h(t in- up) tai out input hold time 400 table 1.32.29. timer a input (gating input in timer mode) table 1.32.30. timer a input (external trigger input in one-shot timer mode) table 1.32.31. timer a input (external trigger input in pulse width modulation mode) table 1.32.32. timer a input (up/down input in event counter mode) table 1.32.28. timer a input (counter input in event counter mode)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 368 timing requirements (referenced to v cc = 3v, v ss = 0v at topr = 25 o c unless otherwise specified) v cc = 3v standard max. min. parameter symbol unit ns t c(tb) tbi in input cycle time (counted on one edge) 100 ns t w(tbh) tbi in input high pulse width (counted on one edge) 40 ns t w(tbl) tbi in input low pulse width (counted on one edge) 40 t w(tbh) ns tbi in input high pulse width (counted on both edges) 80 t w(tbl) ns tbi in input low pulse width (counted on both edges) 80 t c(tb) ns tbi in input cycle time (counted on both edges) 200 standard max. min. parameter symbol unit ns t c(tb) tbi in input cycle time 400 ns t w(tbh) tbi in input high pulse width 200 t w(tbl) ns tbi in input low pulse width 200 standard max. min. parameter symbol unit ns t c(tb) tbi in input cycle time 400 ns t w(tbh) tbi in input high pulse width 200 t w(tbl) ns tbi in input low pulse width 200 standard max. min. parameter symbol unit ns t c(ad) ad trg input cycle time (trigger able minimum) 1000 ns t w(adl) ad trg input low pulse width 125 standard max. min. parameter symbol unit ns t w(inh) inti input high pulse width 250 ns t w(inl) inti input low pulse width 250 standard max. min. parameter symbol unit ns t c(ck) clki input cycle time 200 ns t w(ckh) clki input high pulse width 100 ns t w(ckl) clki input low pulse width 100 t h(c-q) ns txdi hold time 0 t su(d-c) ns rxdi input setup time 30 t h(c-d) ns rxdi input hold time 90 t d(c-q) ns txdi output delay time 80 table 1.32.33. timer b input (counter input in event counter mode) table 1.32.34. timer b input (pulse period measurement mode) table 1.32.35. timer b input (pulse width measurement mode) table 1.32.36. a-d trigger input table 1.32.37. serial i/o _______ table 1.32.38. external interrupt inti inputs
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 369 symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 18 ns t h(bclk-ad) address output hold time (bclk standard) 0 ns t h(bclk-cs) chip select output hold time (bclk standard) 0 ns t d(bclk-ale) ale signal output delay time 18 ns t h(bclk-ale) ale signal output hold time C 2 ns t d(bclk-rd) rd signal output delay time 18 ns t h(bclk-rd) rd signal output hold time C 3 ns t d(bclk-wr) wr signal output delay time 18 ns t h(bclk-wr) wr signal output hold time 0 ns (note) ns t d(db-wr) data output delay time (wr standard) ns (note) note: calculated according to the bclk frequency as follows: t d(db C wr) = f (bclk) 10 9 C 20 [ns] t d(bclk-cs) chip select output delay time 18 ns t h(rd-ad) address output hold time (rd standard) 0 ns t h(wr-ad) address output hold time (wr standard) (note) ns t h(rd-cs) chip select output hold time (rd standard) 0 ns t h(wr-cs) chip select output hold time (wr standard) (note) ns t h(wr C db) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C cs) = f (bclk) x 2 10 9 C 10 [ns] t w(wr) write pulse width t w(wr) = f (bclk) x2 10 9 C 15 [ns] t h(wr-db) data output hold time (wr standard) ns (note) switching characteristics (referenced to v cc = 3v, v ss = 0v at topr = 25 o c, cm15="1" unless otherwise specified) v cc = 3v figure 1.32.1 table 1.32.39. memory expansion and microprocessor modes (with no wait)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 370 switching characteristics (referenced to v cc = 3v, v ss = 0v at topr = 25 o c unless otherwise specified) v cc = 3v figure 1.32.1 table 1.32.40. memory expansion and microprocessor modes (with wait, accessing external memory) symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 18 ns t h(bclk-ad) address output hold time (bclk standard) 0 ns t h(bclk-cs) chip select output hold time (bclk standard) 0 ns t d(bclk-ale) ale signal output delay time 18 ns t h(bclk-ale) ale signal output hold time C 2 ns t d(bclk-rd) rd signal output delay time 18 ns t h(bclk-rd) rd signal output hold time C 3 ns t d(bclk-wr) wr signal output delay time 18 ns t h(bclk-wr) wr signal output hold time 0 ns t h(wr-db) data output hold time (wr standard) (note) ns t d(db-wr) data output delay time (wr standard) ns (note) note: calculated according to the bclk frequency as follows: [ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively) t d(bclk-cs) chip select output delay time 18 ns t h(rd-ad) address output hold time (rd standard) 0 ns t h(wr-ad) address output hold time (wr standard) (note) ns t h(rd-cs) chip select output hold time (rd standard) 0 ns t h(wr-cs) chip select output hold time (wr standard) (note) ns t d(db C wr) = f (bclk) 10 x n 9 C 20 t h(wr C db) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C cs) = f (bclk) x 2 10 9 C 10 [ns] t w(wr) write pulse width [ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively) t w( wr) = 10 x n 9 C 15 (note) ns f ( bclk ) x 2
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 371 v cc = 3v switching characteristics (referenced to v cc = 3v, v ss = 0v at topr = 25 o c unless otherwise specified) table 1.32.41. memory expansion and microprocessor modes (with wait, accessing external memory, multiplex bus area selected) symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 18 ns t h(bclk-ad) address output hold time (bclk standard) 0 ns t h(bclk-cs) chip select output hold time (bclk standard) 0 ns t d(bclk-ale) ale signal output delay time (bclk standard) 18 ns t h(bclk-ale) ale signal output hold time (bclk standard) C 2ns t d(bclk-rd) rd signal output delay time 18 ns t h(bclk-rd) rd signal output hold time ns t d(bclk-wr) wr signal output delay time 18 ns t h(bclk-wr) wr signal output hold time 0 ns t h(wr-db) data output hold time (wr standard) (note) ns t d(db-wr) data output delay time (wr standard) ns (note) note: calculated according to the bclk frequency as follows: t d(db C wr) = 10 x m 9 C 25 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) t d(bclk-cs) chip select output delay time 18 ns t h(rd-ad) address output hold time (rd standard) (note) ns t h(wr-ad) address output hold time (wr standard) (note) ns t h(rd-cs) chip select output hold time (rd standard) ns t h(wr-cs) chip select output hold time (wr standard) (note) ns t h(rd C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(rd C cs) = f (bclk) x 2 10 9 C 10 [ns] t d(ad-ale) ale signal output delay time (address standard) ns t h(ale-ad) ale signal output hold time (address standard) ns t dz(rd-ad) address output flowting start time ns (note) (note) 8 t h(wr C cs) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C db) = f (bclk) x 2 10 9 C 10 [ns] t d(ad C ale) = f (bclk) x 2 10 9 C 20 [ns] t h(ale C ad) = f (bclk) x 2 10 9 C 10 [ns] f (bclk) x 2 (note) C 3 figure 1.32.1
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 372 v cc = 3v switching characteristics (referenced to v cc = 3v, v ss = 0v at topr = 25 o c unless otherwise specified) table 1.32.42. memory expansion and microprocessor modes (with wait, accessing external memory, dram area selected) symbol standard measuring condition max. min. parameter unit t d(bclk-rad) row address output delay time 18 ns t h(bclk-rad) row address output hold time (bclk standard) 0 ns t d(bclk-ras) ras output delay time (bclk standard) 0 ns t su(db-cas) cas after db output setup time 18 ns t h(bclk-db) db signal output hold time (bclk standard) (note) ns 18 t d(bclk-cas) cas output delay time (bclk standard) C 3 ns t h(bclk-cas) cas output hold time (bclk standard) (note) ns t d(bclk-dw) data output delay time (bclk standard) ns C 7 note: calculated according to the bclk frequency as follows: t su(cas C ras) = f ( bclk ) x 2 10 9 C 13 [ ns ] t h(ras-rad) row address output hold time after ras output 18 ns t d(bclk-cad) string address output delay time 0 ns t h(bclk-cad) string address output hold time (bclk standard) (note) ns t h(bclk-ras) ras output hold time (bclk standard) ns t rp ras "h" hold time ns t h(ras C rad) = f (bclk) x 2 10 9 C 13 [ns] t rp = f (bclk) x 2 10 x 3 9 C 20 [ns] t su(cas-ras) cas output setup time before ras output (refresh) 18 ns (note) t su(db C cas) = f (bclk) 10 9 C 20 [ns] t h(bclk-dw) data output hold time (bclk standard) ns 0 figure 1.32.1
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 373 figure 1.32.10. v cc =3v timing diagram (1) bclk ale -2ns.min rd 18ns.max -3ns.min hi-z db 0ns.min 0ns.min t d(bclk-ale) t h(bclk-ale) t su(db-bclk) t d(bclk-rd) 30ns.min *1 csi t d(bclk-cs) 18ns.max *1 adi t h(bclk-ad) 0ns.min t h(bclk-cs) 0ns.min bhe tcyc t d(bclk-ad) 0ns.min t ac2(ad-db) *2 t ac2(rd-db) =(tcyc/2-35)ns.max t ac2(ad-db) =(tcyc-35)ns.max wr,wrl, wrh 18ns.max 0ns.min bclk csi t d(bclk-cs) 18ns.max adi t d(bclk-ad) 18ns.max t d(bclk-ale) 0ns.min 0ns.min tcyc bhe t d(db-wr) *3 dbi t d(bclk-wr) ale -2ns.min t h(wr-db) *3 t d(db-wr) =(tcyc-20)ns.min t h(wr-db) =(tcyc/2-10)ns.min t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min t w(wr) =(tcyc/2-15)ns.min vcc=3v t h(bclk-rd) t h(rd-db) t h(rd-ad) t h(rd-cs) t h(bclk-wr) t h(bclk-ale) t h(bclk-ad) t h(bclk-cs) t h(wr-cs) *3 t h(wr-ad) *3 t ac2(rd-db) *2 18ns.max *1 read timing write timing *3:it depends on operation frequency. measuring conditions ? v cc =3v10% ? input timing voltage :determined with v ih =1.5v, v il =0.5v ? output timing voltage :determined with v oh =1.5v, v ol =1.5v memory expansion mode and microprocessor mode (without wait) *1:it is a guarantee value with being alone. 35ns.max garantees as t d(bclk-ad) +t su(db-bclk) . *2:it depends on operation frequency. 18ns.max t w(wr)*3 18ns.max
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 374 figure 1.32.11. v cc =3v timing diagram (2) bclk ale 18ns.max -2ns.min rd 18ns.max -3ns.min hi-z db 0ns.min 0ns.min t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) 30ns.min *1 t ac2(rd-db) *2 csi t d(bclk-cs) 18ns.max *1 adi 18ns.max *1 t h(bclk-ad) 0ns.min t h(bclk-cs) 0ns.min bhe tcyc t d(bclk-ad) t ac2(ad-db) *2 t ac2(rd-db) =(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) t ac2(ad-db) =(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) wr,wrl, wrh 18ns.max 0ns.min bclk csi 18ns.max adi 18ns.max 0ns.min 0ns.min tcyc bhe dbi t d(bclk-wr) ale 18ns.max -2ns.min vcc=3v t h(bclk-rd) t h(rd-db) t h(rd-ad) t su(db-bclk) t h(rd-cs) 0ns.min t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t d(bclk-ale) t h(bclk-ad) t h(bclk-cs) t h(wr-cs) *3 t d(db-wr) *3 t h(wr-db) *3 t h(wr-ad) *3 t d(db-wr) =(tcyc x n-20)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) t h(wr-db) =(tcyc/2-10)ns.min t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min t w(wr) =(tcyc/2 x n-15)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) *3:it depends on operation frequency. measuring conditions ? v cc =3v10% ? input timing voltage :determined with v ih =1.5v, v il =0.5v ? output timing voltage :determined with v oh =1.5v, v ol =1.5v *1:it is a guarantee value with being alone. 35ns.max garantees as t d(bclk-ad) +t su(db-bclk) . *2:it depends on operation frequency. t h(bclk-ale) read timing write timing memory expansion mode and microprocessor mode (with wait) t w(wr) *3
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 375 figure 1.32.12. v cc =3v timing diagram (3) bclk csi 18ns.max adi 18ns.max rd 18ns.max -3ns.min t h(bclk-ad) 0ns.min 0ns.min bhe adi /dbi 0ns.min 18ns.max 0ns.min bclk csi 18ns.max adi 18ns.max 0ns.min 0ns.min tcyc bhe adi /dbi data output wr,wrl, wrh address address data input 30ns.min t d(bclk-rd) t h(wr-cs) *2 address t d(ad-ale) *2 address t su(db-bclk) t ac3(rd-db) *1 t dz(rd-ad) 8ns.max ale -2ns.min t d(bclk-ale) 18ns.max t d(ad-ale) =(tcyc/2-20)ns.min t h(ale-ad) =(tcyc/2-10)ns.min, t h(rd-ad) =(tcyc/2-10)ns.min, t h(rd-cs) =(tcyc/2-10)ns.min t ac3(rd-db) =(tcyc/2 x m-35)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.) t ac3(ad-db) =(tcyc/2 x n-35)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.) ale -2ns.min t d(bclk-ale) t h(ale-ad) *2 t d(ad-ale) =(tcyc/2-20)ns.min t h(ale-ad) =(tcyc/2-10)ns.min, t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min, t h(wr-db) =(tcyc/2-10)ns.min t d(db-wr) =(tcyc/2 x m-25)ns.min (m=3 and 5 when 2 wait and 3 wait, respectively.) vcc=3v t d(bclk-cs) t d(ad-ale) *1 t h(ale-ad) *1 t h(bclk-rd) t h(rd-ad) *1 t h(rd-db) t d(bclk-ad) t h(bclk-cs) t h(rd-cs) *1 t d(bclk-wr) t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t h(bclk-ad) t h(bclk-cs) t h(wr-ad) *2 t d(db-wr) *2 t h(wr-db) *2 t h(bclk-ale) t h(bclk-ale) tcyc *2:it depends on operation frequency. measuring conditions ? v cc =3v10% ? input timing voltage :determined with v ih =1.5v, v il =0.5v ? output timing voltage :determined with v oh =1.5v, v ol =1.5v *1:it depends on operation frequency. read timing write timing memory expansion mode and microprocessor mode (when accessing external memory area with wait, and select multiplexed bus) 18ns.max t ac3(ad-db) *1
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 376 figure 1.32.13. v cc =3v timing diagram (4) bclk dw db mai t d(bclk-ras) + t su(db-bclk) t d(bclk-cas) + t su(db-bclk) t d(bclk-cad) + t su(db-bclk) t ac4(ras-db) =(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.) t ac4(cas-db) =(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.) t ac4(cad-db) =(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.) t h(ras-rad) =(tcyc/2-13)ns.min t rp =(tcyc/2 x 3-20)ns.min vcc=3v ras casl cash hi-z t ac4(cas-db)*2 18ns.max*1 t h(bclk-cad) 0ns.min tcyc t d(bclk-rad) t ac4(ras-db)*2 row address string address t h(bclk-rad) 0ns.min 18ns.max*1 t d(bclk-cad) 18ns.max*1 t d(bclk-ras) 18ns.max*1 t d(bclk-cas) t h(ras-rad)*2 t rp*2 t ac4(cad-db)*2 t h(bclk-ras) 0ns.min t h(bclk-cas) 0ns.min 0ns.min t su(db-bclk) 30ns.min*1 t h(cas-db) *2:it depends on operation frequency. measuring conditions ? v cc =3v10% ? input timing voltage :determined with v ih =1.5v, v il =0.5v ? output timing voltage :determined with v oh =1.5v, v ol =1.5v read timing memory expansion mode and microprocessor mode (when accessing dram area with 2 wait) *1:it is a guarantee value with being alone. 35ns.max garantees as follows:
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 377 figure 1.32.14. v cc =3v timing diagram (5) bclk dw db mai t h(ras-rad) =(tcyc/2-13)ns.min t rp =(tcyc/2 x 3-20)ns.min t su(db-cas) =(tcyc-20)ns.min vcc=3v ras casl cash hi-z t h(bclk-db) -7ns.min 18ns.max t h(bclk-cad) 0ns.min tcyc t d(bclk-rad) t h(bclk-rad) 0ns.min 18ns.max t d(bclk-cad) 18ns.max t d(bclk-ras) 18ns.max t d(bclk-cas) t rp*1 18ns.max t d(bclk-dw) t su(db-cas)*1 t h(bclk-ras) 0ns.min t h(bclk-cas) -3ns.min t h(bclk-dw) 0ns.min row address string address *1:it depends on operation frequency. measuring conditions ? v cc =3v10% ? input timing voltage :determined with v ih =1.5v, v il =0.5v ? output timing voltage :determined with v oh =1.5v, v ol =1.5v write timing memory expansion mode and microprocessor mode (when accessing dram area with 2 wait) t h(ras-rad)*1
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 378 figure 1.32.15. v cc =3v timing diagram (6) tcyc 18ns.max t d(bclk-ras) 18ns.max t d(bclk-cas) t h(bclk-ras) 0ns.min t h(bclk-cas) 0ns.min t su(cas-ras)*1 18ns.max t cyc t d(bclk-cas) t su(cas-ras)*1 t h(bclk-ras) 0ns.min t h(bclk-cas) 0ns.min 18ns.max t d(bclk-ras) bclk dw t su(cas-ras) =(tcyc/2-13)ns.min vcc=3v ras casl cash bclk dw t su(cas-ras) =(tcyc/2-13)ns.min ras casl cash *1:it depends on operation frequency. measuring conditions ? v cc =3v10% ? input timing voltage :determined with v ih =1.5v, v il =0.5v ? output timing voltage :determined with v oh =1.5v, v ol =1.5v refresh timing (cas before ras refresh) memory expansion mode and microprocessor mode *1:it depends on operation frequency. refresh timing (self-refresh)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 379 figure 1.32.16. v cc =3v timing diagram (7) t su(d C c) tai in input tai out input during event counter mode tbi in input clki txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) t h(t in C up) t su(up C t in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) inti input ad trg input
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 380 figure 1.32.17. v cc =3v timing diagram (8) measuring conditions : ? v cc =3v10% ? input timing voltage : determined with v ih =2.4v, v il =0.6v ? output timing voltage : determined with v oh =1.5v, v ol =1.5v memory expansion mode and microprocessor mode bclk hold input hlda output p0, p1, p2, p3, p4, p5 0 to p5 2 (valid with or without wait) (valid only with wait) rdy input t su(rdy C bclk) t h(bclk C rdy) bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus) hi C z t h(bclk C hold) t su(hold C bclk) t d(bclk C hlda) t d(bclk C hlda)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description (flash memory version) 381 item power supply voltage program/erase voltage flash memory operation mode erase block division program method erase method program/erase control method protect method number of commands program/erase count rom code protect performance f(x in )=30mhz, without wait, 4.2v to 5.5v f(x in )=20mhz, without wait, 3.0v to 3.6v 4.2v to 5.5 v : f( bclk )=12.5mhz, with one wait : f( bclk )=6.25mhz, without wait three modes (parallel i/o, standard serial i/o, cpu rewrite) see figure 1.33.3 one division (8 kbytes) in units of pages (in units of 256 bytes) collective erase/block erase program/erase control by software command protected for each block by lock bit 8 commands 100 times parallel i/o and standard serial modes are supported. note: the boot rom area contains a standard serial i/o mode control program which is stored in it when shipped from the factory. this area can be erased and programmed in only parallel i/o mode. user rom area boot rom area data holding 10 years (note 1) outline performance table 1.33.1 shows the outline performance of the m32c/83 (flash memory version). table 1.33.1. outline performance of the m32c/83 (flash memory version) the following shows mitsubishi plans to develop a line of m32c/83 products (flash memory version). (1) rom capacity (2) package 100p6s-a ... plastic molded qfp 100p6q-a ... plastic molded qfp 144p6q-a ... plastic molded qfp figure 1.33.1. rom expansion rom size (bytes) flash memory version external rom 256k 128k 512k m30835fjgp m30833fjfp m30833fjgp
description (flash memory version) under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer 382 ** : under development 31 kbytes 512 kbytes 100p6s-a 100p6q-a ** ** ** ram capacity rom capacity package type remarks type no as of nov., 2001 144p6q-a m30835fjgp m30833fjgp m30833fjfp package type: fp : package 100p6s-a gp : package 100p6q-a, 144p6q-a rom no. omitted for external rom version and blank flash memory version rom capacity: j : 512k bytes memory type: m : mask rom version s : external rom version f : flash memory version type no. m 3 0 8 3 5 f j C x x x f p m32c/83 group m16c family shows ram capacity, pin count, etc (the value itself has no specific meaning) the following lists the m32c/83 products to be supported in the future. table 1.33.2. product list figure 1.33.2. type no., memory size, and package
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer description (flash memory version) 383 user rom area boot rom area note 1: the boot rom area can be rewritten in only parallel input/ output mode. (access to any other areas is inhibited.) note 2: to specify a block, use the maximum address in the block that is an even address. 8k bytes 0ffe000 16 0ffffff 16 0ff0000 16 block 3 : 32k bytes 0ff8000 16 block 2 : 8k bytes 0ffa000 16 block 1 : 8k bytes block 0 : 16k bytes 0ffc000 16 0ffffff 16 0fd0000 16 block 5 : 64k bytes 0fc0000 16 block 6 : 64k bytes 0fe0000 16 block 4 : 64k bytes block 8 : 64k bytes block 9 : 64k bytes block 7 : 64k bytes block 10 : 64k bytes 0fb0000 16 0fa0000 16 0f90000 16 0f80000 16 flash memory the m32c/83 (flash memory version) contains the flash memory that can be rewritten with a single voltage of 5 v. for this flash memory, three flash memory modes are available in which to read, program, and erase: parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a programmer and a cpu rewrite mode in which the flash memory can be manipulated by the central pro- cessing unit (cpu). each mode is detailed in the pages to follow. the flash memory is divided into several blocks as shown in figure 1.33.3, so that memory can be erased one block at a time. each block has a lock bit to enable or disable execution of an erase or program operation, allowing for data in each block to be protected. in addition to the ordinary user rom area to store a microcomputer operation control program, the flash memory has a boot rom area that is used to store a program to control rewriting in cpu rewrite and standard serial i/o modes. this boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the user s application system. this boot rom area can be rewritten in only parallel i/o mode. figure 1.33.3. block diagram of flash memory version
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 384 cpu rewrite mode in cpu rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the central processing unit (cpu). in cpu rewrite mode, only the user rom area shown in figure 1.33.3 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block erase commands are issued for only the user rom area and each block area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite control program must be transferred to any area other than the internal flash memory before it can be executed. microcomputer mode and boot mode the control program for cpu rewrite mode must be written into the user rom or boot rom area in parallel i/o mode beforehand. (if the control program is written into the boot rom area, the standard serial i/o mode becomes unusable.) see figure 1.33.3 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnv ss pin low. in this case, the cpu starts operating using the control program in the user rom area. when the microcomputer is reset by pulling the p5 5 pin low, the cnv ss pin high, and the p5 0 pin high, the cpu starts operating using the control program in the boot rom area. this mode is called the boot mode. the control program in the boot rom area can also be used to rewrite the user rom area. block address block addresses refer to the maximum even address of each block. these addresses are used in the block erase command, lock bit program command, and read lock status command. outline performance of cpu rewrite mode in the cpu rewrite mode, the cpu erases, programs and reads the internal flash memory as instructed by software commands. operations must be executed from a memory other than the internal flash memory, such as the internal ram. when the cpu rewrite mode select bit (bit 1 at address 0377 16 ) is set to 1 , transition to cpu rewrite mode occurs and software commands can be accepted. in the cpu rewrite mode, write to and read from software commands and data into even-numbered ad- dress ( 0 for byte address a0) in 16-bit units. always write 8-bit software commands into even-numbered address. commands are ignored with odd-numbered addresses. use software commands to control program and erase operations. whether a program or erase operation has terminated normally or in error can be verified by reading the status register. figure 1.34.1 shows the flash memory control register 0.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 385 flash memory control register 0 symbol address when reset fmr0 0057 16 xx000001 2 w r b7 b6 b5 b4 b3 b2 b1 b0 fmr00 bit symbol bit name function rw 0: busy (being written or erased) 1: ready cpu rewrite mode select bit (note 1) 0: normal mode (software commands invalid) 1: cpu rewrite mode (software commands acceptable) fmr01 0: boot rom area is accessed 1: user rom area is accessed lock bit disable bit (note 2) 0: block lock by lock bit data is enabled 1: block lock by lock bit data is disabled flash memory reset bit (note 3) 0: normal operation 1: reset user rom area select bit ( note 4) (effective in only boot mode) fmr02 fmr03 fmr05 0 note 1: for this bit to be set to 1 , the user needs to write a 0 and then a 1 to it in succession. when it is not this procedure, it is not enacted in 1 . this is necessary to ensure that no interrupt or dma transfer will be executed during the interval. use the control program except in the internal flash memory for write to this bit. also write to this bit when nmi pin is "h" level. note 2: for this bit to be set to 1 , the user needs to write a 0 and then a 1 to it in succession when the cpu rewrite mode select bit = 1 . when it is not this procedure, it is not enacted in 1 . this is necessary to ensure that no interrupt or dma transfer will be executed during the interval. note 3: effective only when the cpu rewrite mode select bit = 1. set this bit to 0 subsequently after setting it to 1 (reset). note 4: use the control program except in the internal flash memory for write to this bit. aa aa a aa a aa aa a a aa aa a a aa a ry/by signal status bit reserved bit must always be set to 0 noting is assigned. when write, set to "0". when read, their contents are indeterminate. figure 1.34.1. flash memory control register flash memory control register (address 0057 16 ) _____ bit 0 of the flash memory control register 0 is the ry/by signal status bit used exclusively to read the operating status of the flash memory. during programming and erase operations, it is 0 . otherwise, it is 1 . bit 1 of the flash memory control register 0 is the cpu rewrite mode select bit. the cpu rewrite mode is entered by setting this bit to 1 , so that software commands become acceptable. in cpu rewrite mode, the cpu becomes unable to access the internal flash memory directly. therefore, write bit 1 in an area other than the internal flash memory. to set this bit to 1 , it is necessary to write 0 and then write 1 in succession when nmi pin is "h" level. the bit can be set to 0 by only writing a 0 .
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 386 bit 2 of the flash memory control register 0 is a lock bit disable bit. by setting this bit to 1 , it is possible to disable erase and write protect (block lock) effectuated by the lock bit data. the lock bit disable select bit only disables the lock bit function; it does not change the lock data bit value. however, if an erase operation is performed when this bit = 1 , the lock bit data that is 0 (locked) is set to 1 (unlocked) after erasure. to set this bit to 1 , it is necessary to write 0 and then write 1 in succession. this bit can be manipulated only when the cpu rewrite mode select bit = 1 . bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of the internal flash memory. this bit is used when exiting cpu rewrite mode and when flash memory access has failed. when the cpu rewrite mode select bit is 1 , writing 1 for this bit resets the control circuit. to release the reset, it is necessary to set this bit to 0 . bit 5 of the flash memory control register 0 is a user rom area select bit which is effective in only boot mode. if this bit is set to 1 in boot mode, the area to be accessed is switched from the boot rom area to the user rom area. when the cpu rewrite mode needs to be used in boot mode, set this bit to 1 . note that if the microcomputer is booted from the user rom area, it is always the user rom area that can be accessed and this bit has no effect. when in boot mode, the function of this bit is effective regardless of whether the cpu rewrite mode is on or off. use the control program except in the internal flash memory to rewrite this bit. figure 1.34.2 shows a flowchart for setting/releasing the cpu rewrite mode. always perform operation as indicated in these flowcharts.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 387 end start execute read array command or reset flash memory by setting flash memory reset bit (by writing 1 and then 0 in succession) (note 3) single-chip mode, memory expansion mode, or boot mode set processor mode register (note 1) using software command execute erase, program, or other operation (set lock bit disable bit as required) jump to transferred control program in ram (subsequent operations are executed by control program in this ram) transfer cpu rewrite mode control program to internal ram note 1: during cpu rewrite mode, set the main clock frequency as shown below using the main clock division register (address 000c 16 ): 6.25 mhz or less when wait bit (bit 2 at address 0005 16 ) = 0 (without internal access wait state) 12.5 mhz or less when wait bit (bit 2 at address 0005 16 ) = 1 (with internal access wait state) note 2: for cpu rewrite mode select bit to be set to 1 , the user needs to write a 0 and then a 1 to it in succession. when it is not this procedure, it is not enacted in 1 . this is necessary to ensure that no interrupt or dma transfer will be executed during the interval. use the program except in the internal flash memory for write to this bit. also write to this bit when nmi pin is "h" level. note 3: before exiting the cpu rewrite mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory. note 4: 1 can be set. however, when this bit is 1 , user rom area is accessed. (boot mode only) write 0 to user rom area select bit (note 4) write 0 to cpu rewrite mode select bit (boot mode only) set user rom area select bit to 1 set cpu rewrite mode select bit to 1 (by writing 0 and then 1 in succession)(note 2) *1 *1 program in rom program in ram figure 1.34.2. cpu rewrite mode set/reset flowchart
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 388 precautions on cpu rewrite mode described below are the precautions to be observed when rewriting the flash memory in cpu rewrite mode. (1) operation speed during cpu rewrite mode, set the main clock frequency as shown below using the main clock division register (address 000c 16 ): 6.25 mhz or less when wait bit (bit 2 at address 0005 16 ) = 0 (without internal access wait state) 12.5 mhz or less when wait bit (bit 2 at address 0005 16 ) = 1 (with internal access wait state) (2) instructions inhibited against use the instructions listed below cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory: und instruction, into instruction, jmps instruction, jsrs instruction, and brk instruction (3) interrupts inhibited against use the address match interrupt cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory. if interrupts have their vector in the variable vector table, they can be _______ used by transferring the vector into the ram area. the nmi and watchdog timer interrupts each can be used to change the cpu rewrite mode select bit forcibly to normal mode (fmr01="0") upon occur- _______ rence of the interrupt. since the rewrite operation is halted when the nmi and watchdog timer inter- rupts occur, set the cpu rewite mode select bit to "1" and the erase/program operation needs to be performed over again. (4) reset reset input is always accepted. (5) access disable write cpu rewrite mode select bit and user rom area select bit in an area other than the internal flash memory. (6) how to access for cpu rewrite mode select bit and lock bit disable bit to be set to 1 , the user needs to write a 0 and then a 1 to it in succession. when it is not this procedure, it is not enacted in 1 . this is neces- sary to ensure that no interrupt or dma transfer will be executed during the interval. write to the cpu rewrite mode select bit when nmi pin is "h" level. (7)writing in the user rom area if power is lost while rewriting blocks that contain the flash rewrite program with the cpu rewrite mode, those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be rewritten after that. therefore, it is recommended to use the standard serial i/o mode or parallel i/o mode to rewrite these blocks. (8)using the lock bit to use the cpu rewrite mode, use a boot program that can set and cancel the lock command.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 389 command page program clear status register read array read status register x x x x (note 3) first bus cycle second bus cycle third bus cycle ff 16 70 16 50 16 41 16 write write write write xsrd read write lock bit program x 77 16 write ba d0 16 write erase all unlock block x a7 16 write x d0 16 write wa1 wd1 write (note 2) wa0 (note 3) wd0 (note 3) block erase x 20 16 write d0 16 write ba (note 4) read lock bit status x 71 16 write ba d 6 read (note 5) mode address mode address mode address data (d 0 to d 7 ) data (d 0 to d 7 ) data (d 0 to d 7 ) (note 6) note 1: when a software command is input, the high-order byte of data (d 8 to d 15 ) is ignored. note 2: srd = status register data note 3: wa = write address, wd = write data wa and wd must be set sequentially from 00 16 to fe 16 (byte address; however, an even address). the page size is 256 bytes. note 4: ba = block address (enter the maximum address of each block that is an even address.) note 5: d 6 corresponds to the block lock status. block not locked when d 6 = 1, block locked when d 6 = 0. note 6: x denotes a given address in the user rom area (that is an even address). software commands table 1.34.1 lists the software commands available with the m16c/62a (flash memory version). after setting the cpu rewrite mode select bit to 1, write a software command to specify an erase or program operation. note that when entering a software command, the upper byte (d 8 to d 15 ) is ignored. the content of each software command is explained below. table 1.34.1. list of software commands (cpu rewrite mode) read array command (ff 16 ) the read array mode is entered by writing the command code ff 16 in the first bus cycle. when an even address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (d 0 C d 15 ), 16 bits at a time. the read array mode is retained intact until another command is written. read status register command (70 16 ) when the command code 70 16 is written in the first bus cycle, the content of the status register is read out at the data bus (d 0 C d 7 ) by a read in the second bus cycle. the status register is explained in the next section. clear status register command (50 16 ) this command is used to clear the bits sr3 to 5 of the status register after they have been set. these bits indicate that operation has ended in an error. to use this command, write the command code 50 16 in the first bus cycle.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 390 n = fe 16 start write 41 16 n = 0 write address n and data n check full status page program completed n = n + 2 no yes no yes ry/by signal status bit = 1? page program command (41 16 ) page program allows for high-speed programming in units of 256 bytes. page program operation starts when the command code 41 16 is written in the first bus cycle. in the second bus cycle through the 129th bus cycle, the write data is sequentially written 16 bits at a time. at this time, the addresses a 0 -a 7 need to be incremented by 2 from 00 16 to fe 16 . when the system finishes loading the data, it starts an auto write operation (data program and verify operation). whether the auto write operation is completed can be confirmed by reading the status register or the flash memory control register 0. at the same time the auto write operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. the status register bit 7 (sr7) is set to 0 at the same time the auto write operation starts and is returned to 1 upon completion of the auto write operation. in this case, the read status register mode remains active until the read array command (ff 16 ) or read lock bit status command (71 16 ) is written or the flash memory is reset using its reset bit. ____ the ry/by signal status bit of the flash memory control register 0 is 0 during auto write operation and 1 when the auto write operation is completed as is the status register bit 7. after the auto write operation is completed, the status register can be read out to know the result of the auto write operation. for details, refer to the section where the status register is detailed. figure 1.34.3 shows an example of a page program flowchart. each block of the flash memory can be write protected by using a lock bit. for details, refer to the section where the data protect function is detailed. additional writes to the already programmed pages are prohibited. figure 1.34.3. page program flowchart
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 391 write 20 16 write d0 16 block address check full status check block erase completed start no yes ry/by signal status bit = 1? block erase command (20 16 /d0 16 ) by writing the command code 20 16 in the first bus cycle and the confirmation command code d0 16 in the second bus cycle that follows to the block address of a flash memory block, the system initiates an auto erase (erase and erase verify) operation. whether the auto erase operation is completed can be confirmed by reading the status register or the flash memory control register 0. at the same time the auto erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. the status register bit 7 (sr7) is set to 0 at the same time the auto erase operation starts and is returned to 1 upon completion of the auto erase operation. in this case, the read status register mode remains active until the read array command (ff 16 ) or read lock bit status command (71 16 ) is written or the flash memory is reset using its reset bit. ____ the ry/by signal status bit of the flash memory control register 0 is 0 during auto erase operation and 1 when the auto erase operation is completed as is the status register bit 7. after the auto erase operation is completed, the status register can be read out to know the result of the auto erase operation. for details, refer to the section where the status register is detailed. figure 1.34.4 shows an example of a block erase flowchart. each block of the flash memory can be protected against erasure by using a lock bit. for details, refer to the section where the data protect function is detailed. figure 1.34.4. block erase flowchart
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 392 write 77 16 write d0 16 block address sr4 = 0? no lock bit program completed lock bit program in error yes start ry/by signal status bit = 1? no yes erase all unlock blocks command (a7 16 /d0 16 ) by writing the command code a7 16 in the first bus cycle and the confirmation command code d0 16 in the second bus cycle that follows, the system starts erasing blocks successively. whether the erase all unlock blocks command is terminated can be confirmed by reading the status register or the flash memory control register 0, in the same way as for block erase. also, the status register can be read out to know the result of the auto erase operation. when the lock bit disable bit of the flash memory control register 0 = 1, all blocks are erased no matter how the lock bit is set. on the other hand, when the lock bit disable bit = 0, the function of the lock bit is effective and only nonlocked blocks (where lock bit data = 1) are erased. lock bit program command (77 16 /d0 16 ) by writing the command code 77 16 in the first bus cycle and the confirmation command code d0 16 in the second bus cycle that follows to the block address of a flash memory block, the system sets the lock bit for the specified block to 0 (locked). figure 1.34.5 shows an example of a lock bit program flowchart. the status of the lock bit (lock bit data) can be read out by a read lock bit status command. whether the lock bit program command is terminated can be confirmed by reading the status register or the flash memory control register 0, in the same way as for page program. for details about the function of the lock bit and how to reset the lock bit, refer to the section where the data protect function is detailed. figure 1.34.5. lock bit program flowchart
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 393 write 71 16 enter block address d 6 = 0? no blocks locked blocks not locked yes start read lock bit status command (71 16 ) by writing the command code 71 16 in the first bus cycle and then the block address of a flash memory block in the second bus cycle that follows, the system reads out the status of the lock bit of the specified block on to the data (d6). figure 1.34.6 shows an example of a read lock bit program flowchart. figure 1.34.6. read lock bit status flowchart
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 394 data protect function (block lock) each block in figure 1.33.3 has a nonvolatile lock bit to specify that the block be protected (locked) against erase/write. the lock bit program command is used to set the lock bit to 0 (locked). the lock bit of each block can be read out using the read lock bit status command. whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash memory control register 0 s lock bit disable bit is set. (1) when the lock bit disable bit = 0, a specified block can be locked or unlocked by the lock bit status (lock bit data). blocks whose lock bit data = 0 are locked, so they are disabled against erase/write. on the other hand, the blocks whose lock bit data = 1 are not locked, so they are enabled for erase/ write. (2) when the lock bit disable bit = 1, all blocks are nonlocked regardless of the lock bit data, so they are enabled for erase/write. in this case, the lock bit data that is 0 (locked) is set to 1 (nonlocked) after erasure, so that the lock bit-actuated lock is removed. status register the status register indicates the operating status of the flash memory and whether an erase or program operation has terminated normally or in an error. the content of this register can be read out by only writing the read status register command (70 16 ). table 1.34.2 details the status register. the status register is cleared by writing the clear status register command (50 16 ). after a reset, the status register is set to 80 16 . each bit in this register is explained below. write state machine (wsm) status (sr7) after power-on, the write state machine (wsm) status is set to 1. the write state machine (wsm) status indicates the operating status of the device, as for output on the ____ ry/by pin. this status bit is set to 0 during auto write or auto erase operation and is set to 1 upon completion of these operations. erase status (sr5) the erase status informs the operating status of auto erase operation to the cpu. when an erase error occurs, it is set to 1. the erase status is reset to 0 when cleared.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 395 each bit of srd sr4 (bit4) sr5 (bit5) sr7 (bit7) sr6 (bit6) status name definition sr1 (bit1) sr2 (bit2) sr3 (bit3) sr0 (bit0) "1" "0" program status erase status write state machine (wsm) status reserved reserved reserved block status after program reserved ready busy terminated in error terminated in error terminated in error terminated normally terminated normally terminated normally - - - - - - - - program status (sr4) the program status informs the operating status of auto write operation to the cpu. when a write error occurs, it is set to 1. the program status is reset to 0 when cleared. when an erase command is in error (which occurs if the command entered after the block erase command (20 16 ) is not the confirmation command (d0 16 ), both the program status and erase status (sr5) are set to 1. when the program status or erase status = 1, the following commands entered by command write are not accepted. also, in one of the following cases, both sr4 and sr5 are set to 1 (command sequence error): (1) when the valid command is not entered correctly (2) when the data entered in the second bus cycle of lock bit program (77 16 /d0 16 ), block erase (20 16 /d0 16 ), or erase all unlock blocks (a7 16 /d0 16 ) is not the d0 16 or ff 16 . however, if ff 16 is entered, read array is assumed and the command that has been set up in the first bus cycle is canceled. block status after program (sr3) if excessive data is written (phenomenon whereby the memory cell becomes depressed which results in data not being read correctly), 1 is set for the program status after-program at the end of the page write operation. in other words, when writing ends successfully, 80 16 is output; when writing fails, 90 16 is output; and when excessive data is written, 88 16 is output. table 1.34.2. definition of each bit in status register
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 396 read status register sr4=1 and sr5 =1 ? no command sequence error yes sr5=0? yes block erase error no sr4=0? yes program error (page or lock bit) no sr3=0? yes program error (block) no end (block erase, program) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should a block erase error occur, the block in error cannot be used. execute the read lock bit status command (71 16 ) to see if the block is locked. after removing lock, execute write operation in the same way. if the error still occurs, the page in error cannot be used. after erasing the block in error, execute write operation one more time. if the same error still occurs, the block in error cannot be used. note: when one of sr5 to sr3 is set to 1, none of the page program, block erase, erase all unlock blocks and lock bit program commands is accepted. execute the clear status register command (50 16 ) before executing these commands. full status check by performing full status check, it is possible to know the execution results of erase and program operations. figure 1.34.7 shows a full status check flowchart and the action to be taken when each error occurs. figure 1.34.7. full status check flowchart and remedial procedure for errors
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer functions to inhibit rewriting flash memory (flash memory version) 397 symbol address when reset romcp 0ffffff 16 ff 16 rom code protect level 2 set bit (note 1, 2) 00: protect enabled 01: protect enabled 10: protect enabled 11: protect disabled rom code protect control address bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 00: protect removed 01: protect set bit effective 10: protect set bit effective 11: protect set bit effective 00: protect enabled 01: protect enabled 10: protect enabled 11: protect disabled rom code protect reset bit (note 3) rom code protect level 1 set bit (note 1) romcp2 romcr romcp1 b3 b2 b5 b4 b7 b6 note 1: when rom code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel input/output mode. note 2: when rom code protect level 2 is turned on, rom code readout by a shipment inspection lsi tester, etc. also is inhibited. note 3: the rom code protect reset bits can be used to turn off rom code protect level 1 and rom code protect level 2. however, since these bits cannot be changed in parallel input/ output mode, they need to be rewritten in serial input/output or some other mode. reserved bit always set this bit to 1. 1 1 functions to inhibit rewriting flash memory version to prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a rom code protect function for use in parallel i/o mode and an id code check function for use in standard serial i/o mode. rom code protect function the rom code protect function reading out or modifying the contents of the flash memory version by using the rom code protect control address (0ffffff 16 ) during parallel i/o mode. figure 1.34.8 shows the rom code protect control address (0ffffff 16 ). (this address exists in the user rom area.) if one of the pair of rom code protect bits is set to 0, rom code protect is turned on, so that the contents of the flash memory version are protected against readout and modification. rom code protect is imple- mented in two levels. if level 2 is selected, the flash memory is protected even against readout by a shipment inspection lsi tester, etc. when an attempt is made to select both level 1 and level 2, level 2 is selected by default. if both of the two rom code protect reset bits are set to 00, rom code protect is turned off, so that the contents of the flash memory version can be read out or modified. once rom code protect is turned on, the contents of the rom code protect reset bits cannot be modified in parallel i/o mode. use the serial i/ o or some other mode to rewrite the contents of the rom code protect reset bits. figure 1.34.8. rom code protect control address
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer functions to inhibit rewriting flash memory (flash memory version) 398 reset vector watchdog timer vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 nmi vector 0fffffc 16 to 0ffffff 16 0fffff8 16 to 0fffffb 16 0fffff4 16 to 0fffff7 16 0fffff0 16 to 0fffff3 16 0ffffec 16 to 0ffffef 16 0ffffe8 16 to 0ffffeb 16 0ffffe4 16 to 0ffffe7 16 0ffffe0 16 to 0ffffe3 16 0ffffdc 16 to 0ffffdf 16 4 bytes address id code check function use this function in standard serial i/o mode. when the contents of the flash memory are not blank, the id code sent from the peripheral unit is compared with the id code written in the flash memory to see if they match. if the id codes do not match, the commands sent from the peripheral unit are not accepted. the id code consists of 8-bit data, the areas of which, beginning with the first byte, are 0ffffdf 16 , 0ffffe3 16 , 0ffffeb 16 , 0ffffef 16 , 0fffff3 16 , 0fffff7 16 , and 0fffffb 16 . write a program which has had the id code preset at these addresses to the flash memory. figure 1.34.9. id code store addresses
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix parallel i/o mode (flash memory version) 399 parallel i/o mode in this mode, the m32c/83 (flash memory version) operates in a manner similar to the flash memory m5m29fb/t800 from mitsubishi. since there are some differences with regard to the functions not avail- able with the microcomputer and matters related to memory capacity, the m32c/83 cannot be programed by a programer for the flash memory. use an exclusive programer supporting m32c/83 (flash memory version). refer to the instruction manual of each programer maker for the details of use. user rom and boot rom areas in parallel i/o mode, the user rom and boot rom areas shown in figure 1.33.3 can be rewritten. both areas of flash memory can be operated on in the same way. program and block erase operations can be performed in the user rom area. the user rom area and its blocks are shown in figure 1.33.3. the boot rom area is 8 kbytes in size. in parallel i/o mode, it is located at addresses 0ffe000 16 through 0ffffff 16 . make sure program and block erase operations are always performed within this address range. (access to any location outside this address range is prohibited.) in the boot rom area, an erase block operation is applied to only one 8 kbyte block. the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the mitsubishi factory. therefore, using the device in standard serial input/output mode, you do not need to write to the boot rom area.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode (flash memory version) 400 standard serial i/o mode the standard serial i/o mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. this i/o is serial. there are actually two standard serial i/o modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. both modes require a purpose-specific peripheral unit. the standard serial i/o mode is different from the parallel i/o mode in that the cpu controls flash memory rewrite (uses the cpu's rewrite mode), rewrite data input and so forth. it is started when the reset is re- _____ ________ leased, which is done when the p5 0 (ce) pin is "h" level, the p5 5 (epm) pin "l" level and the cnvss pin "h" level. (in the ordinary command mode, set cnvss pin to "l" level.) this control program is written in the boot rom area when the product is shipped from mitsubishi. accord- ingly, make note of the fact that the standard serial i/o mode cannot be used if the boot rom area is rewritten in the parallel i/o mode. figures 1.35.1 to 1.35.3 show the pin connections for the standard serial i/o mode. serial data i/o uses uart1 and transfers the data serially in 8-bit units. standard serial i/o switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of clk 1 pin when the reset is released. to use standard serial i/o mode 1 (clock synchronized), set the clk 1 pin to "h" level and the txd 1 pin to "l" level, and release the reset. the clk 1 pin is connected to vcc via pull-up resistance and the txd 1 is connected to vss via pull-down resistance. the operation uses the four uart1 pins clk 1 , rxd 1 , txd 1 and rts 1 (busy). the clk 1 pin is the transfer clock input pin through which an external transfer clock is input. the txd 1 pin is for cmos output. the rts 1 (busy) pin outputs an "l" level when ready for reception and an "h" level when reception starts. to use standard serial i/o mode 2 (clock asynchronized), set the clk 1 pin to "l" level and release the reset. the operation uses the two uart1 pins rxd 1 and txd 1 . in the standard serial i/o mode, only the user rom area indicated in figure 1.35.20 can be rewritten. the boot rom cannot. in the standard serial i/o mode, a 7-byte id code is used. when there is data in the flash memory, com- mands sent from the peripheral unit (programmer) are not accepted unless the id code matches.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode (flash memory version) 401 pin description v cc ,v ss apply 4.2v to 5.5v to vcc pin and 0 v to vss pin. cnv ss connect to vcc pin. reset reset input pin. while reset is "l" level, a 20 cycle or longer clock must be input to xin pin. x in connect a ceramic resonator or crystal oscillator between x in and x out pins. to input an externally generated clock, input it to x in pin and open x out pin. x out byte connect this pin to vcc or vss. av cc , av ss v ref connect avss to vss and avcc to vcc, respectively. enter the reference voltage for a-d converter from this pin. p0 0 to p0 7 input "h" or "l" level signal or open. p1 0 to p1 7 input "h" or "l" level signal or open. p2 0 to p2 7 input "h" or "l" level signal or open. p3 0 to p3 7 input "h" or "l" level signal or open. p4 0 to p4 7 input "h" or "l" level signal or open. p5 1 to p5 4, p5 6, p5 7 input "h" or "l" level signal or open. p5 0 input "h" level signal. p5 5 input "l" level signal. p6 0 to p6 3 input "h" or "l" level signal or open. p6 4 p6 5 p6 6 serial data input pin p6 7 p7 0 to p7 7 input "h" or "l" level signal or open. p8 0 to p8 4 , p8 6 , p8 7 input "h" or "l" level signal or open. p9 0 to p9 7 input "h" or "l" level signal or open. p10 0 to p10 7 input "h" or "l" level signal or open. name power input cnv ss reset input clock input clock output byte analog power supply input reference voltage input input port p0 input port p1 input port p2 input port p3 input port p4 input port p5 ce input epm input input port p6 busy output sclk input rxd input txd output input port p7 input port p8 input port p9 input port p10 i/o i i i o i i i i i i i i i i i o i i o i i i i p8 5 nmi input i connect this pin to vcc. i standard serial mode 1: busy signal output pin standard serial mode 2: monitors the program operation check standard serial mode 1: serial clock input pin standard serial mode 2: input "l" level signal. p11 0 to p11 4 input "h" or "l" level signal or open. (note) input port p11 i p12 0 to p12 7 input "h" or "l" level signal or open. (note) input port p12 i p13 0 to p13 7 input "h" or "l" level signal or open. (note) input port p13 i p14 0 to p14 6 input "h" or "l" level signal or open. (note) input port p14 i p15 0 to p15 7 input "h" or "l" level signal or open. (note) input port p15 i serial data output pin. when using standard serial mode 1, an "l" level must be input to txd pin while the reset pin is l . for this reason, this pin should be pulled down. after being reset, this pin functions as a data output pin. thus adjust pull-down resistance value with the system not to affect data transfer. note: port p11 to p15 exist in 144-pin version. pin functions (flash memory standard serial i/o mode)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode (flash memory version) 402 1 2 3 4 5 67 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 vcc vss txd rxd sclk cnvss ce epm busy reset signal value cnvss vcc epm vss reset vss >> vcc ce vcc mode setting connect oscillation circuit m32c/83(100-pin) group flash memory version (100p6s) figure 1.35.1. pin connections for standard serial i/o mode (1)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode (flash memory version) 403 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 cnv ss reset v ss v cc ce busy epm sclk r x d t x d connect oscillation circuit signal value cnvss vcc epm vss reset vss >> vcc ce vcc mode setting m32c/83(100-pin) group flash memory version (100p6q) figure 1.35.2. pin connections for standard serial i/o mode (2)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode (flash memory version) 404 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 78 12 34 7 689101112131415161718192021222324252627282930 5 31 32 33 34 35 36 cnv ss reset epm ce v cc v ss txd rxd sclk busy m32c/83(144-pin) group flash memory version (144p6q) signal value cnvss vcc epm vss reset vss >> vcc ce vcc mode setting connect oscillation circuit figure 1.35.3. pin connections for standard serial i/o mode (3)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 405 overview of standard serial i/o mode 1 (clock synchronized) in standard serial i/o mode 1, software commands, addresses and data are input and output between the mcu and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial i/o (uart1). standard serial i/o mode 1 is engaged by releasing the reset with the p6 5 (clk1) pin "h" level. in reception, software commands, addresses and program data are synchronized with the rise of the trans- fer clock that is input to the clk1 pin, and are then input to the mcu via the rxd1 pin. in transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the txd1 pin. the txd1 pin is for cmos output. transfer is in 8-bit units with lsb first. when busy, such as during transmission, reception, erasing or program execution, the rts1 (busy) pin is "h" level. accordingly, always start the next transfer after the rst1 (busy) pin is "l" level. also, data and status registers in memory can be read after inputting software commands. status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. here following are explained software commands, status registers, etc.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 406 control command 2nd byte 3rd byte 4th byte 5th byte 6th byte 1 page read 2 page program 3 block erase 4 erase all unlocked blocks 5 read status register 6 clear status register 7 read lock bit status 8 lock bit program 9 lock bit enable 10 lock bit disable 11 code processing function 12 download function 13 version data output function 14 boot rom area output function 15 read check data address (middle) address (middle) address (middle) d0 16 srd output address (middle) address (middle) address (low) size (low) version data output address (middle) check data (low) address (high) address (high) address (high) srd1 output address (high) address (high) address (middle) size (high) version data output address (high) check data (high) data output data input d0 16 lock bit data output d0 16 address (high) check- sum version data output data output data output data input id size data input version data output data output data output data input id1 to required number of times version data output data output data output to 259th byte data input to 259th byte to id7 version data output to 9th byte data output to 259th byte ff 16 41 16 20 16 a7 16 70 16 50 16 71 16 77 16 7a 16 75 16 f5 16 fa 16 fb 16 fc 16 fd 16 when id is not verified not acceptable not acceptable not acceptable not acceptable acceptable not acceptable not acceptable not acceptable not acceptable not acceptable acceptable not acceptable acceptable not acceptable not acceptable 1st byte transfer software commands table 1.35.1 lists software commands. in the standard serial i/o mode 1, erase operations, programs and reading are controlled by transferring software commands via the rxd 1 pin. software commands are explained here below. table 1.35.1. software commands (standard serial i/o mode 1) note 1: shading indicates transfer from flash memory microcomputer to peripheral unit. all other data is trans- ferred from the peripheral unit to the flash memory microcomputer. note 2: srd refers to status register data. srd1 refers to status register data1 . note 3: all commands can be accepted when the flash memory is totally blank.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 407 data0 data255 clk1 rxd1 txd1 rts1(busy) a 8 to a 15 a 16 to a 23 ff 16 (m32c reception data) (m32c transmit data) page read command this command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page read command as explained here following. (1) transfer the ff 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 C d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first in sync with the rise of the clock. figure 1.35.4. timing for page read page program command this command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page program command as explained here following. (1) transfer the 41 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, as write data (d 0 C d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 is input sequentially from the smallest address first, that page is automatically written. when reception setup for the next 256 bytes ends, the rts1 (busy) signal changes from the h to the l level. the result of the page program can be known by reading the status register. for more information, see the section on the status register. each block can be write-protected with the lock bit. for more information, see the section on the data protection function. additional writing is not allowed with already programmed pages.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 408 clk1 rxd1 txd1 rts1(busy) a 8 to a 15 a 16 to a 23 41 16 data0 data255 (m32c reception data) (m32c transmit data) a 8 to a 15 a 16 to a 23 20 16 d0 16 clk1 rxd1 txd1 rts1(busy) (m32c reception data) (m32c transmit data) figure 1.35.5. timing for the page program block erase command this command erases the data in the specified block. execute the block erase command as explained here following. (1) transfer the 20 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) transfer the verify command code d0 16 with the 4th byte. with the verify command code, the erase operation will start for the specified block in the flash memory. write the highest address of the specified block for addresses a 16 to a 23 . when block erasing ends, the rts1 (busy) signal changes from the h to the l level. after block erase ends, the result of the block erase operation can be known by reading the status register. for more information, see the section on the status register. each block can be erase-protected with the lock bit. for more information, see the section on the data protection function. figure 1.35.6. timing for block erasing
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 409 clk1 rxd1 txd1 rts1(busy) a7 16 d0 16 (m32c reception data) (m32c transmit data) erase all unlocked blocks command this command erases the content of all blocks. execute the erase all unlocked blocks command as explained here following. (1) transfer the a7 16 command code with the 1st byte. (2) transfer the verify command code d0 16 with the 2nd byte. with the verify command code, the erase operation will start and continue for all blocks in the flash memory. when block erasing ends, the rts1 (busy) signal changes from the h to the l level. the result of the erase operation can be known by reading the status register. each block can be erase-protected with the lock bit. for more information, see the section on the data protection function. figure 1.35.7. timing for erasing all unlocked blocks read status register command this command reads status information. when the 70 16 command code is sent with the 1st byte, the contents of the status register (srd) specified with the 2nd byte and the contents of status register 1 (srd1) specified with the 3rd byte are read. figure 1.35.8. timing for reading the status register srd output srd1 output clk1 rxd1 txd1 rts1(busy) 70 16 (m32c reception data) (m32c transmit data)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 410 clk1 rxd1 txd1 rts1(busy) a 8 to a 15 a 16 to a 23 71 16 dq6 (m32c reception data) (m32c transmit data) clk1 rxd1 txd1 rts1(busy) 50 16 (m32c reception data) (m32c transmit data) clear status register command this command clears the bits (sr3 C sr5) which are set when the status register operation ends in error. when the 50 16 command code is sent with the 1st byte, the aforementioned bits are cleared. when the clear status register operation ends, the rts 1 (busy) signal changes from the h to the l level. figure 1.35.9. timing for clearing the status register read lock bit status command this command reads the lock bit status of the specified block. execute the read lock bit status com- mand as explained here following. (1) transfer the 71 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) the lock bit data of the specified block is output with the 4th byte. the 6th bit (d6) of output data is the lock bit data. write the highest address of the specified block for addresses a 8 to a 23 . figure 1.35.10. timing for reading lock bit status
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 411 clk1 rxd1 txd1 rts1(busy) a 8 to a 15 a 16 to a 23 77 16 d0 16 (m32c reception data) (m32c transmit data) lock bit program command this command writes 0 (lock) for the lock bit of the specified block. execute the lock bit program command as explained here following. (1) transfer the 77 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) transfer the verify command code d0 16 with the 4th byte. with the verify command code, 0 is written for the lock bit of the specified block. write the highest address of the specified block for addresses a 8 to a 23 . when writing ends, the rts 1 (busy) signal changes from the h to the l level. lock bit status can be read with the read lock bit status command. for information on the lock bit function, reset proce- dure and so on, see the section on the data protection function. figure 1.35.11. timing for the lock bit program lock bit enable command this command enables the lock bit in blocks whose bit was disabled with the lock bit disable com- mand. the command code 7a 16 is sent with the 1st byte of the serial transmission. this command only enables the lock bit function; it does not set the lock bit itself. figure 1.35.12. timing for enabling the lock bit 7a 16 clk1 rxd1 txd1 rts1(busy) (m32c reception data) (m32c transmit data)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 412 id size id1 id7 clk1 rxd1 txd1 rts1(busy) f5 16 df 16 ff 16 0f 16 (m32c reception data) (m32c transmit data) 75 16 clk1 rxd1 txd1 rts1(busy) (m32c reception data) (m32c transmit data) lock bit disable command this command disables the lock bit. the command code 75 16 is sent with the 1st byte of the serial transmission. this command only disables the lock bit function; it does not set the lock bit itself. however, if an erase command is executed after executing the lock bit disable command, 0 (locked) lock bit data is set to 1 (unlocked) after the erase operation ends. in any case, after the reset is cancelled, the lock bit is enabled. figure 1.35.13. timing for disabling the lock bit id check this command checks the id code. execute the boot id check command as explained here following. (1) transfer the f5 16 command code with the 1st byte. (2) transfer addresses a 0 to a 7 , a 8 to a 15 and a 16 to a 23 of the 1st byte of the id code with the 2nd, 3rd and 4th bytes respectively. (3) transfer the number of data sets of the id code with the 5th byte. (4) the id code is sent with the 6th byte onward, starting with the 1st byte of the code. figure 1.35.14. timing for the id check
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 413 fa 16 program data data size (high) data size (low) check sum clk1 rxd1 txd1 rts1(busy) (m32c reception data) (m32c transmit data) program data download command this command downloads a program to the ram for execution. execute the download command as explained here following. (1) transfer the fa 16 command code with the 1st byte. (2) transfer the program size with the 2nd and 3rd bytes. (3) transfer the check sum with the 4th byte. the check sum is added to all data sent with the 5th byte onward. (4) the program to execute is sent with the 5th byte onward. when all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal ram. figure 1.35.15. timing for download version information output command this command outputs the version information of the control program stored in the boot area. execute the version information output command as explained here following. (1) transfer the fb 16 command code with the 1st byte. (2) the version information will be output from the 2nd byte onward. this data is composed of 8 ascii code characters. figure 1.35.16. timing for version information output fb 16 'x' 'v' 'e' 'r' clk1 rxd1 txd1 rts1(busy) (m32c reception data) (m32c transmit data)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 414 boot rom area output command this command outputs the control program stored in the boot rom area in one page blocks (256 bytes). execute the boot rom area output command as explained here following. (1) transfer the fc 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 C d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first, in sync with the rise of the clock. data0 data255 clk1 rxd1 txd1 rts1(busy) a 8 to a 15 a 16 to a 23 fc 16 (m32c reception data) (m32c transmit data) figure 1.35.17. timing for boot rom area output read check data this command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) transfer the "fd 16 " command code with the 1st byte. (2) the check data (low) is received with the 2nd byte and the check data (high) with the 3rd. to use this read check data command, first execute the command and then initialize the check data. next, execute the page program command the required number of times. after that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. the check data is the result of crc operation of write data.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 415 check data (low) clk1 rxd1 txd1 rts1(busy) fd 16 (m32c reception data) (m32c transmit data) check data (high) id code when the flash memory is not blank, the id code sent from the peripheral units and the id code written in the flash memory are compared to see if they match. if the codes do not match, the command sent from the peripheral units is not accepted. an id code contains 8 bits of data. area is, from the 1st byte, addresses 0ffffdf 16 , 0ffffe3 16 , 0ffffeb 16 , 0ffffef 16 , 0fffff3 16 , 0fffff7 16 and 0fffffb 16 . write a program into the flash memory, which already has the id code set for these addresses. figure 1.35.19. id code storage addresses reset vector watchdog timer vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 nmi vector 0fffffc 16 to 0ffffff 16 0fffff8 16 to 0fffffb 16 0fffff4 16 to 0fffff7 16 0fffff0 16 to 0fffff3 16 0ffffec 16 to 0ffffef 16 0ffffe8 16 to 0ffffeb 16 0ffffe4 16 to 0ffffe7 16 0ffffe0 16 to 0ffffe3 16 0ffffdc 16 to 0ffffdf 16 4 bytes address figure 1.35.18. timing for the read check data
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 416 user rom area 0ff0000 16 block 3 : 32k bytes 0ff8000 16 block 2 : 8k bytes 0ffa000 16 block 1 : 8k bytes block 0 : 16k bytes 0ffc000 16 0ffffff 16 0fd0000 16 block 5 : 64k bytes 0fc0000 16 block 6 : 64k bytes 0fe0000 16 block 4 : 64k bytes block 8 : 64k bytes block 9 : 64k bytes block 7 : 64k bytes block 10 : 64k bytes 0fb0000 16 0fa0000 16 0f90000 16 0f80000 16 data protection (block lock) each of the blocks in figure 1.35.20 have a nonvolatile lock bit that specifies protection (block lock) against erasing/writing. a block is locked (writing 0 for the lock bit) with the lock bit program command. also, the lock bit of any block can be read with the read lock bit status command. block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock bit disable and lock enable bit commands. (1) after the reset has been cancelled and the lock bit enable command executed, the specified block can be locked/unlocked using the lock bit (lock bit data). blocks with a 0 lock bit data are locked and cannot be erased or written in. on the other hand, blocks with a 1 lock bit data are unlocked and can be erased or written in. (2) after the lock bit enable command has been executed, all blocks are unlocked regardless of lock bit data status and can be erased or written in. in this case, lock bit data that was 0 before the block was erased is set to 1 (unlocked) after erasing, therefore the block is actually unlocked with the lock bit. figure 1.35.20. blocks in the user area
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 417 srd bits sr0 (bit0) sr1 (bit1) sr2 (bit2) sr3 (bit3) sr4 (bit4) sr5 (bit5) sr6 (bit6) sr7 (bit7) status name reserved reserved reserved block status after program program status erase status reserved write state machine (wsm) status definition "1" "0" - - - terminated in error terminated in error terminated in error - ready - - - terminated normally terminated normally terminated normally busy - status register (srd) the status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. it can be read by writing the read status register command (70 16 ). also, the status register is cleared by writing the clear status register command (50 16 ). table 1.35.2 gives the definition of each status register bit. after clearing the reset, the status register outputs 80 16 . table 1.35.2. status register (srd) program status after program (sr3) if excessive data is written (phenomenon whereby the memory cell becomes depressed which results in data not being read correctly), 1 is set for the program status after-program at the end of the page write operation. in other words, when writing ends successfully, 80 16 is output; when writing fails, 90 16 is output; and when excessive data is written, 88 16 is output. if 1 is written for any of the sr5, sr4 or sr3 bits, the page program, block erase, erase all unlocked blocks and lock bit program commands are not accepted. before executing these commands, execute the clear status register command (50 16 ) and clear the status register. program status (sr4) the program status reports the operating status of the auto write operation. if a write error occurs, it is set to 1 . when the program status is cleared, it is set to 0 . erase status (sr5) the erase status reports the operating status of the auto erase operation. if an erase error occurs, it is set to 1 . when the erase status is cleared, it is set to 0 . write state machine (wsm) status (sr7) the write state machine (wsm) status indicates the operating status of the flash memory. when power is turned on, 1 (ready) is set for it. the bit is set to 0 (busy) during an auto write or auto erase operation, but it is set back to 1 when the operation ends.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 418 srd1 bits sr8 (bit0) sr9 (bit1) sr10 (bit2) sr11 (bit3) sr12 (bit4) sr13 (bit5) sr14 (bit6) sr15 (bit7) status name reserved data receive time out id check completed bits checksum match bit reserved reserved boot update completed bit definition "1" "0" - time out 00 01 10 11 match - - update completed - normal operation mismatch - - not update not verified verification mismatch reserved verified status register 1 (srd1) status register 1 indicates the status of serial communications, results from id checks and results from check sum comparisons. it can be read after the srd by writing the read status register command (70 16 ). also, status register 1 is cleared by writing the clear status register command (50 16 ). table 1.35.3 gives the definition of each status register 1 bit. 00 16 is output when power is turned on and the flag status is maintained even after the reset. table 1.35.3. status register 1 (srd1) data reception time out (sr9) this flag indicates when a time out error is generated during data reception. if this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. id check completed bits (sr11 and sr10) these flags indicate the result of id checks. some commands cannot be accepted without an id check. check sum consistency bit (sr12) this flag indicates whether the check sum matches or not when a program, is downloaded for execu- tion using the download function. boot update completed bit (sr15) this flag indicates whether the control program was downloaded to the ram or not, using the down- load function.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 419 clock input (1) control pins and external circuitry will vary according to peripheral unit (programmer). for more information, see the peripheral unit (programmer) manual. (2) in this example, the microprocessor mode and standard serial i/o mode are switched via a switch. busy output rts1(busy) clk1 data input r x d1 data output t x d1 cnvss p5 0 (ce) p5 5 (epm) nmi m32c/83 flash memory version read status register sr4=1 and sr5 =1 ? no command sequence error yes sr5=0? yes block erase error no sr4=0? yes program error (page or lock bit) no sr3=0? yes program error (block) no end (block erase, program) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should a block erase error occur, the block in error cannot be used. execute the read lock bit status command (71 16 ) to see if the block is locked. after removing lock, execute write operation in the same way. if the error still occurs, the page in error cannot be used. after erasing the block in error, execute write operation one more time. if the same error still occurs, the block in error cannot be used. note: when one of sr5 to sr3 is set to 1, none of the page program, block erase, erase all unlock blocks and lock bit program commands is accepted. execute the clear status register command (50 16 ) before executing these commands. full status check results from executed erase and program operations can be known by running a full status check. figure 1.35.21 shows a flowchart of the full status check and explains how to remedy errors which occur. figure 1.35.21. full status check flowchart and remedial procedure for errors example circuit application for the standard serial i/o mode 1 the below figure shows a circuit application for the standard serial i/o mode 1. control pins will vary according to peripheral unit (programmer), therefore see the peripheral unit (programmer) manual for more information. figure 1.35.22. example circuit application for the standard serial i/o mode 1
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 420 overview of standard serial i/o mode 2 (clock asynchronized) in standard serial i/o mode 2, software commands, addresses and data are input and output between the mcu and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial i/o (uart1). standard serial i/o mode 2 is engaged by releasing the reset with the p6 5 (clk 1 ) pin "l" level. the txd 1 pin is for cmos output. data transfer is in 8-bit units with lsb first, 1 stop bit and parity off. after the reset is released, connections can be established at 9,600 bps when initial communications (fig- ure 1.35.23) are made with a peripheral unit. however, this requires a main clock with a minimum 2 mhz input oscillation frequency. baud rate can be changed from 9,600 bps to 19,200, 38,400, 57,600 or 115,200 bps by executing software commands. however, communication errors may occur because of the oscilla- tion frequency of the main clock. if errors occur, change the main clock's oscillation frequency and the baud rate. after executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. data and status registers in memory can be read after transmitting software commands. status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. here following are explained initial communications with peripheral units, how frequency is identified and software commands. initial communications with peripheral units after the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation fre- quency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (figure 1.35.23). (1) transmit "00 16 " from a peripheral unit 16 times. (the mcu with internal flash memory sets the bit rate generator so that "00 16 " can be successfully received.) (2) the mcu with internal flash memory outputs the "b0 16 " check code and initial communications end successfully * 1 . initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. also, the baud rate at the end of initial communications is 9,600 bps. *1. if the peripheral unit cannot receive "b0 16 " successfully, change the oscillation frequency of the main clock. mcu with internal flash memory peripheral unit (1) transfer "00 16 " 16 times at least 15ms transfer interval 1st 2nd 15 th 16th (2) transfer check code "b0 16 " "00 16 " "00 16 " "00 16 " "b0 16 " "00 16 " reset the bit rate generator setting completes (9600bps) figure 1.35.23. peripheral unit and initial communication
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 421 operation frequency (mh z ) baud rate 9,600bps baud rate 19,200bps baud rate 38,400bps baud rate 57,600bps 30mhz 20mhz 16mh z 12mh z 11mh z 10mh z 8mh z 7.3728mh z 6mh z 5mh z 4.5mh z 4.194304mh z 4mh z 3.58mh z 3mh z 2mh z : communications possible C : communications not possible C C C C C C C C C baud rate 115,200bps C C C C C C C C C C C C C C C how frequency is identified when "00 16 " data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 30 mhz). the highest speed is taken from the first 8 transmissions and the lowest from the last 8. these values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. baud rate cannot be attained with some operating frequencies. table 1.35.4 gives the operation fre- quency and the baud rate that can be attained for. table 1.35.4 operation frequency and the baud rate
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 422 control command 2nd byte 3rd byte 4th byte 5th byte 6th byte 1 page read 2 page program 3 block erase 4 erase all unlocked blocks 5 read status register 6 clear status register 7 read lock bit status 8 lock bit program 9 lock bit enable 10 lock bit disable 11 code processing function 12 download function 13 version data output function 14 boot rom area output function 15 read check data 16 baud rate 9600 17 baud rate 19200 18 baud rate 38400 19 baud rate 57600 20 baud rate 115200 address (middle) address (middle) address (middle) d0 16 srd output address (middle) address (middle) address (low) size (low) version data output address (middle) check data (low) b0 16 b1 16 b2 16 b3 16 b4 16 address (high) address (high) address (high) srd1 output address (high) address (high) address (middle) size (high) version data output address (high) check data (high) data output data input d0 16 lock bit data output d0 16 address (high) check- sum version data output data output data output data input id size data input version data output data output data output data input id1 to required number of times version data output data output data output to 259th byte data input to 259th byte to id7 version data output to 9th byte data output to 259th byte ff 16 41 16 20 16 a7 16 70 16 50 16 71 16 77 16 7a 16 75 16 f5 16 fa 16 fb 16 fc 16 fd 16 b0 16 b1 16 b2 16 b3 16 b4 16 when id is not verified not acceptable not acceptable not acceptable not acceptable acceptable not acceptable not acceptable not acceptable not acceptable not acceptable acceptable not acceptable acceptable not acceptable not acceptable acceptable acceptable acceptable acceptable acceptable 1st byte transfer software commands table 1.35.5 lists software commands. in the standard serial i/o mode 2, erase operations, programs and reading are controlled by transferring software commands via the rxd 1 pin. standard serial i/o mode 2 adds five transmission speed commands - 9,600, 19,200, 38,400, 57,600 and 115,200 bps - to the soft- ware commands of standard serial i/o mode 1. software commands are explained here below. table 1.35.5. software commands (standard serial i/o mode 2) note 1: shading indicates transfer from flash memory microcomputer to peripheral unit. all other data is trans- ferred from the peripheral unit to the flash memory microcomputer. note 2: srd refers to status register data. srd1 refers to status register data 1. note 3: all commands can be accepted when the flash memory is totally blank.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 423 data0 data255 rxd1 txd1 a 8 to a 15 a 16 to a 23 ff 16 (m32c reception data) (m32c transmit data) page read command this command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page read command as explained here following. (1) transfer the ff 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 C d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first in sync with the rise of the clock. figure 1.35.24. timing for page read page program command this command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page program command as explained here following. (1) transfer the 41 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, as write data (d 0 C d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 is input sequentially from the smallest address first, that page is automatically written. the result of the page program can be known by reading the status register. for more information, see the section on the status register. each block can be write-protected with the lock bit. for more information, see the section on the data protection function. additional writing is not allowed with already programmed pages. figure 1.35.25. timing for the page program rxd1 txd1 a 8 to a 15 a 16 to a 23 41 16 data0 data255 (m32c reception data) (m32c transmit data)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 424 a 8 to a 15 a 16 to a 23 20 16 d0 16 rxd1 txd1 (m32c reception data) (m32c transmit data) rxd1 txd1 a7 16 d0 16 (m32c reception data) (m32c transmit data) block erase command this command erases the data in the specified block. execute the block erase command as explained here following. (1) transfer the 20 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) transfer the verify command code d0 16 with the 4th byte. with the verify command code, the erase operation will start for the specified block in the flash memory. write the highest address of the specified block for addresses a 16 to a 23 . after block erase ends, the result of the block erase operation can be known by reading the status register. for more information, see the section on the status register. each block can be erase-protected with the lock bit. for more information, see the section on the data protection function. figure 1.35.26. timing for block erasing erase all unlocked blocks command this command erases the content of all blocks. execute the erase all unlocked blocks command as explained here following. (1) transfer the a7 16 command code with the 1st byte. (2) transfer the verify command code d0 16 with the 2nd byte. with the verify command code, the erase operation will start and continue for all blocks in the flash memory. the result of the erase operation can be known by reading the status register. each block can be erase- protected with the lock bit. for more information, see the section on the data protection function. figure 1.35.27. timing for erasing all unlocked blocks
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 425 srd output srd1 output rxd1 txd1 70 16 (m32c reception data) (m32c transmit data) rxd1 txd1 50 16 (m32c reception data) (m32c transmit data) read status register command this command reads status information. when the 70 16 command code is sent with the 1st byte, the contents of the status register (srd) specified with the 2nd byte and the contents of status register 1 (srd1) specified with the 3rd byte are read. figure 1.35.28. timing for reading the status register clear status register command this command clears the bits (sr3 C sr5) which are set when the status register operation ends in error. when the 50 16 command code is sent with the 1st byte, the aforementioned bits are cleared. figure 1.35.29. timing for clearing the status register read lock bit status command this command reads the lock bit status of the specified block. execute the read lock bit status com- mand as explained here following. (1) transfer the 71 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) the lock bit data of the specified block is output with the 4th byte. the 6th bit (d6) of output data is the lock bit data. write the highest address of the specified block for addresses a 8 to a 23 . rxd1 txd1 a 8 to a 15 a 16 to a 23 71 16 dq6 (m32c reception data) (m32c transmit data) figure 1.35.30. timing for reading lock bit status
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 426 7a 16 rxd1 txd1 (m32c reception data) (m32c transmit data) rxd1 txd1 a 8 to a 15 a 16 to a 23 77 16 d0 16 (m32c reception data) (m32c transmit data) lock bit program command this command writes 0 (lock) for the lock bit of the specified block. execute the lock bit program command as explained here following. (1) transfer the 77 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) transfer the verify command code d0 16 with the 4th byte. with the verify command code, 0 is written for the lock bit of the specified block. write the highest address of the specified block for addresses a 8 to a 23 . lock bit status can be read with the read lock bit status command. for information on the lock bit function, reset procedure and so on, see the section on the data protection function. figure 1.35.31. timing for the lock bit program lock bit enable command this command enables the lock bit in blocks whose bit was disabled with the lock bit disable com- mand. the command code 7a 16 is sent with the 1st byte of the serial transmission. this command only enables the lock bit function; it does not set the lock bit itself. figure 1.35.32. timing for enabling the lock bit
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 427 75 16 rxd1 txd1 (m32c reception data) (m32c transmit data) lock bit disable command this command disables the lock bit. the command code 75 16 is sent with the 1st byte of the serial transmission. this command only disables the lock bit function; it does not set the lock bit itself. however, if an erase command is executed after executing the lock bit disable command, 0 (locked) lock bit data is set to 1 (unlocked) after the erase operation ends. in any case, after the reset is cancelled, the lock bit is enabled. figure 1.35.33. timing for disabling the lock bit id check this command checks the id code. execute the boot id check command as explained here following. (1) transfer the f5 16 command code with the 1st byte. (2) transfer addresses a 0 to a 7 , a 8 to a 15 and a 16 to a 23 of the 1st byte of the id code with the 2nd, 3rd and 4th bytes respectively. (3) transfer the number of data sets of the id code with the 5th byte. (4) the id code is sent with the 6th byte onward, starting with the 1st byte of the code. figure 1.35.34. timing for the id check id size id1 id7 rxd1 txd1 f5 16 df 16 ff 16 0f 16 (m32c reception data) (m32c transmit data )
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 428 fb 16 'x' 'v' 'e' 'r' rxd1 txd1 (m32c reception data) (m32c transmit data) fa 16 program data data size (high) data size (low) check sum rxd1 txd1 (m32c reception data) (m32c transmit data) program data download command this command downloads a program to the ram for execution. execute the download command as explained here following. (1) transfer the fa 16 command code with the 1st byte. (2) transfer the program size with the 2nd and 3rd bytes. (3) transfer the check sum with the 4th byte. the check sum is added to all data sent with the 5th byte onward. (4) the program to execute is sent with the 5th byte onward. when all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal ram. figure 1.35.35. timing for download version information output command this command outputs the version information of the control program stored in the boot area. execute the version information output command as explained here following. (1) transfer the fb 16 command code with the 1st byte. (2) the version information will be output from the 2nd byte onward. this data is composed of 8 ascii code characters. figure 1.35.36. timing for version information output
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 429 boot rom area output command this command outputs the control program stored in the boot rom area in one page blocks (256 bytes). execute the boot rom area output command as explained here following. (1) transfer the fc 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 C d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first, in sync with the rise of the clock. data0 data255 clk1 rxd1 txd1 rts1(busy) a 8 to a 15 a 16 to a 23 fc 16 (m32c reception data) (m32c transmit data) figure 1.35.37. timing for boot rom area output read check data this command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) transfer the "fd 16 " command code with the 1st byte. (2) the check data (low) is received with the 2nd byte and the check data (high) with the 3rd. to use this read check data command, first execute the command and then initialize the check data. next, execute the page program command the required number of times. after that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. the check data is the result of crc operation of write data. figure 1.35.38. timing for the read check data check data (low) rxd1 txd1 fd 16 (m32c reception data) (m32c transmit data) check data (high)
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 430 rxd1 txd1 b1 16 (m32c reception data) (m32c transmit data) b1 16 rxd1 txd1 b2 16 (m32c reception data) (m32c transmit data) b2 16 rxd1 txd1 b0 16 (m32c reception data) (m32c transmit data) b0 16 baud rate 9600 this command changes baud rate to 9,600 bps. execute it as follows. (1) transfer the "b0 16 " command code with the 1st byte. (2) after the "b0 16 " check code is output with the 2nd byte, change the baud rate to 9,600 bps. figure 1.35.39. timing of baud rate 9600 baud rate 19200 this command changes baud rate to 19,200 bps. execute it as follows. (1) transfer the "b1 16 " command code with the 1st byte. (2) after the "b1 16 " check code is output with the 2nd byte, change the baud rate to 19,200 bps. figure 1.35.41. timing of baud rate 38400 figure 1.35.40. timing of baud rate 19200 baud rate 38400 this command changes baud rate to 38,400 bps. execute it as follows. (1) transfer the "b2 16 " command code with the 1st byte. (2) after the "b2 16 " check code is output with the 2nd byte, change the baud rate to 38,400 bps.
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 431 rxd1 txd1 b3 16 (m32c reception data) (m32c transmit data) b3 16 baud rate 57600 this command changes baud rate to 57,600 bps. execute it as follows. (1) transfer the "b3 16 " command code with the 1st byte. (2) after the "b3 16 " check code is output with the 2nd byte, change the baud rate to 57,600 bps. figure 1.35.42. timing of baud rate 57600 baud rate 115200 this command changes baud rate to 115,200 bps. execute it as follows. (1) transfer the "b4 16 " command code with the 1st byte. (2) after the "b4 16 " check code is output with the 2nd byte, change the baud rate to 19,200 bps. figure 1.35.43. timing of baud rate 115200 id code when the flash memory is not blank, the id code sent from the peripheral units and the id code written in the flash memory are compared to see if they match. if the codes do not match, the command sent from the peripheral units is not accepted. an id code contains 8 bits of data. area is, from the 1st byte, addresses 0ffffdf 16 , 0ffffe3 16 , 0ffffeb 16 , 0ffffef 16 , 0fffff3 16 , 0fffff7 16 and 0fffffb 16 . write a program into the flash memory, which already has the id code set for these addresses. rxd1 txd1 b4 16 (m32c reception data) (m32c transmit data) b4 16
under development rev.b2 for proof reading mitsubishi microcomputers m32c/83 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 432 monitor output data input data output rts1(busy) clk1 r x d1 t x d1 cnvss p5 0 (ce) p5 5 (epm) nmi m32c/80 flash memory version in this example, the microprocessor mode and standard serial i/o mode are switched via a switch. reset vector watchdog timer vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 nmi vector 0fffffc 16 to 0ffffff 16 0fffff8 16 to 0fffffb 16 0fffff4 16 to 0fffff7 16 0fffff0 16 to 0fffff3 16 0ffffec 16 to 0ffffef 16 0ffffe8 16 to 0ffffeb 16 0ffffe4 16 to 0ffffe7 16 0ffffe0 16 to 0ffffe3 16 0ffffdc 16 to 0ffffdf 16 4 bytes address figure 1.35.44. id code storage addresses example circuit application for the standard serial i/o mode 2 the below figure shows a circuit application for the standard serial i/o mode 2. figure 1.35.45. example circuit application for the standard serial i/o mode 2
revision history m32c/83 group data sheet rev. date description page errror correct ( 1 / 7 ) b1 1/8/2001 100-pin version is added. flash memory version is added. others 2,3 tables 1.1.1 and 1.1.2 interrupt: 12 internal/external sources (intelligent i/o and can module) delate supply voltage 3.0 to 3.6v (f(x in )=20mhz without wait) add 3 a-d converter 10 bits (8 channels) x 2 circuits, max 26 inputs 10 bits x 2 circuits, standard 10 inputs, max 26 inputs 7 table 1.1.3 pin 26 can in addition 10-12 figures 1.1.4, 1.1.5, table 1.1.7 can in is added to pin 17(gp) and pin 19(fp) 11 figure 1.1.5 pin 97 an0 0 an 0 12 pin 32 (fp) vcc delate pin 34 (fp) vss delate 13 vcc position to pin 64(fp) pin 62 vss position to pin 66(fp) pin 64 rxd4/scl4/stxd4 position to pin 98 (fp) pin 100 14 table 1.1.5 an2 0 to an2 7 an0 0 to an0 7 an3 0 to an3 7 an2 0 to an2 7 17 table1.1.12 p12 0 to p12 7 isclk description delate an1 0 to an1 7 an15 0 to an15 7 18 figure 1.1.6 system clock oscillation circuit pll oscillation stop detect addition 28, 29 figure 1.4.3 (122), (167) group0 receive buffer register, group1 receive buffer register (123), (168) group0 transmit buffer/receive data register, group1 transmit buffer/receive data register 46 note 1: addresses 03c9 16 , 03cb 16 to 03d3 16 addresses 03a0 16 , 03a1 16 , 03b9 16 , 03bc 16 , 03bd 16 , 03c9 16 , 03cb 16 to 03d3 16 48 figure 1.6.1 note 2 addition. displase after the former note 2 70 figure 1.8.6 when reset of pll control register 0 0x11 0100 0011 0100 72 figure 1.8.8 count value set bit division rate select bit count start bit operation enable bit count stop/start divider stops/starts note 2 delate 76 line 10 addition stop mode is canceled before setting this bit to "1". 77 line 8 1:sub clock is selected 1: clock from ring oscillator is selected 135 figure 1.14.2 values that can be set pulse width modulation mode (8-bit pwm) 00 16 to ff 16 (high-order and low-order address) 00 16 to fe 16 (high-order address) 00 16 to ff 16 (low- order address) 230 line 5, bit 1 trmactive trmdata 266 table1.23.11 waveform generate control register 1when clock synchronous serial i/o - 280 table1.23.17 note 1: when the transfer clock and transfer data are trans- mission, transfer clock is set to at least 6 divisions of b1 30/8/ 2001
revision history m32c/83 group data sheet rev. date description page errror correct ( 2 / 7 ) the base timer clock. except this, transfer clock is set to at least 20 divisions of the base timer clock. note 2 addition 285 figure 1.23.37 delay timing of base timer 284 table1.24.1 a-d conversion start condition ? timer b2 interrupt ? timer b2 interrupt occurrences frequency counter overflow b2 feb/1/ 2002 2, 3, 4 table 1.1.1, 1.1.2 clock generating circuit 4 built-in...circuit 3 built-in clock generation circuits pll freq. synthe. delete power consumption 29ma 26ma 44ma 38ma 6,10, fig 1.1.3-1.1.5 note: p7 0 and p7 1 are n-channel...output.-> add 11 18 fig 1.1.6 system clock generator pll delete oscillation stop detection ring oscillator 24 7th line since the value.....due to the interruption. -> add 27 fig 1.4.3 (1) (2) processor mode register 1 xx00 x000 -> x000 00xx (3) system clock control register 0 80 -> 0000 x000 (10) oscillation stop detect register xxxx 0000 -> 00 (17) vdc control register 1 add (21) dram refresh interval set register xxxx ?000 -> ?? (46) can interrupt 1 control register add (47) can interrupt 2 control register add 28 fig 1.4.3 (2) (70) can interrupt 0 control register add 28-31 fig 1.4.3(2) (97)-(104), fig 1.4.3(3) (142)-(149), fig 1.4.3(4) (187)-(194), fig 1.4.3(5) (222)-(229) group 0 -3 time measurement/ waveform generation register 0-7 00 -> ?? 29, 30 fig 1.4.3(3) (124), fig 1.4.3(4) (169) group 0,1 si/o communication buffer register group 0,1 si/o receive buffer register fig 1.4.3(3) (125), fig 1.4.3(4) (170) group 0,1 receive data register group 0,1 transmit buffer/receive data register (129) group 0 si/o comm cont register x000 xxx -> 000 x011 (186) group 1 si/o expansion trans cont register 0000 00xx -> 0000 0xxx 31 fig 1.4.3(5) (238)-(241) group 3 waveform generate mask register 4-7 00 -> ?? 32 fig 1.4.3(6) (270)-(308) note added (270)-(302) reset value changed 33 fig 1.4.3(7) (309)-(338) note added (314)-(318),(321),(323),(329),(331),(336) reset values changed (337) can0 clock control register can0 sleep control register 36 fig 1.4.3(10) (461) a-d control register 2 x000 xxx0 -> x000 0000
revision history m32c/83 group data sheet rev. date description page errror correct ( 3 / 7 ) 38 address 007f 16 can interrupt 1 control register added address 0081 16 can interrupt 2 control register added address 009d 16 can interrupt 0 control register added 61 (10) software wait, 11th line sfr area is accessed.....with 2 waits .add 67 fig 1.8.2 system clock control register 0 when reset: 08 16 0000 x000 2 note 3: when selecting fc,.....as input port. delete 79 fig 1.8.9 note 7: when using pll.....cannot be used. delete 90 fig 1.9.3, symbol can0ici caniic 110 table 1.11.1, dma request factors intelligent i/o interrupt -> add 128 fig 1.12.4, the number of cycles change 133 fig 1.14.3, timer ai mode register, mr0 port output.....registers a and b. port output.....registers a, b and c. 137, table 1.14.1, 1.14.2, 1.14,4, 1.14,5 138, tai out pin function function select register c -> add 142, 144 137 fig 1.14.7 timer ai mode register bit 2 (mr0) function select register c -> add location of note 3 (b7, b6): 11 10 139 fig 1.14.8 timer ai mode register bit 2 (mr0) function select register c -> add 143, fig 1.14.11, 1.14.12 timer ai mode register 145 bit 2 (mr0) function select register c -> add location of note 3 (b7, b6): 11 10 159 fig 1.16.5 timer ai mode register bit 2 (mr0) function select register c -> add 161 fig 1.16.6 reload register reload register n = 1 to 255 172 fig 1.17.4 uarti transmit/receive control register 0 note 2 function select register c -> add 173 fig 1.17.5 uarti transmit/receive control register 1 function of bit 7: error signal output enable bit set to 0 199 fig 1.22.1 clock control register sleep control register time stamp count register time stamp register 200 fig 1.22.3 bit 4 0: forced reset 0: reset requested bit 10 time stamp count reset bit time stamp counter reset bit 201 5th line: in no case will the can module be ..... in no case will the can be..... bit 3: basiccan mode bit bit 3: basiccan mode select bit 202 bit 8,9: timestamp prescaler bits bit 8, 9: timestamp prescaler select bits bit 11, 1st line: receive error counter receive error counter register transmit error counter transmit error counter register 209 fig 1.22.8 bit 4: reserved bit sampling number 210 6. can0 configuration register explanation of bit 4 -> add
revision history m32c/83 group data sheet rev. date description page errror correct ( 4 / 7 ) 211 note:1 setting the c0ctlr0 register s reset0 bit to 1 resets the can protocol control unit, with the c0tsr register thereby initialized to 0000 16 . also, setting the tsreset (timestamp count reset) bit to 1 initializes the c0tsr register to 0000 16 on-the- fly ( while the can protocol control unit remains operating). note 1: setting the c0ctlr0 register s reset0 and reset1 bits to 1 resets the can, and the c0tsr register is thereby initialized to 0000 16 . also, setting the tsreset (timestamp counter reset) bit to 1 ini- tializes the c0tsr register to 0000 16 on-the-fly ( while the can remains operating; can0 status register s state_reset bit is 0 ). 212 tq period = (c0brp+1) tq period = (c0brp+1)/cpu clock 220 fig 1.22.19 b0 b2 b2 b1 226 fig 1.22.25 bit 0 note 2 -> add bit 1, when transmit, trmdata when transmit, trmactive bit 3 note 2 -> add bit 6, 7, transmit request flag transmit request bit 229 fig 1.22.26, explanation of function change 230, fig 1.22.27, 1.22.28, 1.22.29 231, explanation of function message slot j (j=0 to 15) -> change 232 233 fig 1.22.30, can0 message slot butter i data m symbol c0slot0_m (m=0 to 3) c0slot0_n (n=m+6, m=0 to 3) c0slot0_m (m=4 to 7) c0slot0_n (n=m+6, m=4 to 7) c0slot1_m (m=0 to 3) c0slot1_n (n=m+6, m=0 to 3) c0slot1_m (m=4 to 7) c0slot1_n (n=m+6, m=4 to 7) 235 table 1.23.1 group 2, wg register - -> 8chs group 3 comm shift register 16bits x 2chs -> - 240 fig 1.23.5, group i base timer cont reg 0 bit 2 to bit 6, explanations on f pll delete 245 table 1.23.2, count reset condition, group 2, 3 (3) reset request ..... circuit (3) reset request ..... circuit (group 2 only) 245 fig 1.23.10 f pll delete 246 fig 1.23.11 newly added 248 fig 1.23.13, the values when reset: 00 16 0000 16 249 table 1.23.3, select function, digital filter function strips off pulses less than 3 cycles long from f 1 pulses will pass when they match either f 1 or the base and the base timerclock. timerclock 3 times. 250 fig 1.23.14, (c) change 252 fig 1.23.16, reset values for both registers 0000 16 -> xxxx 16 256 fig 1.23.20, when wg register is xxxb 16 when wg register is xxxa 16 270 table 1.23.12 transmission start condition ? write data to transmit buffer register ? write data to transmit buffer interrupt request generation timing ? when transmitting - when si/o transmit buffer register is..... - when transmit buffer is ..... ? when receiving when....to si/o communication buffer register when.....to si/o receive buffer register
revision history m32c/83 group data sheet rev. date description page errror correct ( 5 / 7 ) 270 select function this.....txd pin output and rxd pin input. this.....istxd pin output and isrxd pin input. 271 table 1.23.13, transfer clock input ? selects i/o with function..... ? select i/o port with function..... 271 fig 1.23.31 write to communication buffer write to receive buffer (input to inpc 2 /isrxd 0 pin) (input to inpci 2 /isrxdi pin (i=0, 1)) 272 table 1.23.14 transmission start condition ? write data to transmit buffer register ? write data to transmit buffer interrupt request generation timing ? when transmitting - when si/o transmit buffer register is..... - when transmit buffer is ..... ? when receiving when....to si/o communication buffer register when.....to si/o receive buffer register error detection ? overrun error: .....before contents of receive buffer register.... .....before contents o si/o receive buffer register..... 273 fig 1.23.32 write to communication buffer write to receive buffer 273 fig 1.23.33 (input to inpc 2 /isrxd 0 pin) (input to inpci 2 /isrxdi pin (i=0, 1)) 279 table 1.23.17 transmission start condition ? write data to transmit buffer register ? write data to si/o transmit buffer register reception start condition ? write data to transmit buffer register ? write data to si/o transmit buffer register interrupt request generation timing ? when receiving when....to si/o communication buffer register when.....to si/o receive buffer register select function this.....txd pin output and rxd pin input. this.....istxd pin output and isrxd pin input. 286 fig 1.24.4, a-d control register 2 when reset: x000 xxx0 2 x000 0000 2 287, fig 1.24.5, note 4 and fig 1.24.6, note 3 288 ..... by a-d sweep pin select bits..... .....by analog input port select bits..... 292 (e) replace function of input pin 2nd line: .....of a-d0 and a-d2. .....of a-d0 and a-d1. 293 (f) , at the end of 2nd line as an0.....respectively. -> add (g) 3rd line: ....., input via an0 0 to an0 7 is..... , input via an 0 to an 7 is..... 294 table 1.24.9 p0 0 analog input p9 5 analog input p0 1 analog input p9 6 analog input 312 fig 1.29.1, p0 0 to p0 7 , p2 0 to p2 7 : -
revision history m32c/83 group data sheet rev. date description page errror correct ( 6 / 7 ) 313 fig 1.29.2 delete direction register port latch pull-up selection data bus port p1 control register direction register port latch pull-up selection data bus port p1 control register circuit (c) delete p1 5 to p1 7 , circuit (b): - 314 fig 1.29.3 add direction register pull-up selection function select register a (note 1) d output from each peripheral function direction register pull-up selection function select register a (note 1) d output from each peripheral function p12 1 , p12 2 , circuit (b): - 326 fig 1.29.16, pull-up register 2, note 1 delete 331 table 1.29.5 _____ bit 0, 1: three-phase pwm output (u) 1: three-phase pwm output (u) bit 1, 0: three-phase pwm output (u) _____ 0: three-phase pwm output (u) 331 table 1.29.6, ps4 ps3 psl4 psl3 bit 1, uart0 uart3 bit 2, uart4 uart3 bit 3, uart1 uart3 bit 4, 5 uart1 uart4 a4 a3 b4 b3 334 vdc add 337 a-d converter 1st line: a-d a-d i (i=0,1) 1st line: a-d a-d i 2nd line: .....and to bit 0 of a-d control register 2... .....and to each bit of a-d i control register 2..... 340 (3) external interrupt ? level sense, 2nd line: (when x in =20mhz and..) (when x in =30mhz and .....) 3rd line: (....., at least 250 ns.....) (....., at least 233 ns.....) ? when the polarity of int 0 to int 5 pins is..... _______ _______ ? when the polarity of int 0 and int 5 pins is..... 341 reducing power consumption, (2) 1st line, last line: an0 4 , an0 7 an 4 , an 7 343 table 1.30.3 g0cr 00ef 16 g0ri 00ec 16 g1ri 012f 16 g1ri 012c 16 u0brg 0361 16 u0brg 0369 16 u0tb 0363 16 , 0362 16 u0tb 036b 16 , 036a 16 u1brg 0369 16 u1brg 02e9 16 u1tb 036b 16 , 036a 16 u1tb 02eb 16 , 02ea 16 343 notes on cnvss pin reset at h level add
revision history m32c/83 group data sheet rev. date description page errror correct ( 7 / 7 ) 344- electric characteristics add 380 385 fig 1.34.1, address 0377 16 address 0057 16 _____ bit 0: ry/by status bit _____ ry/by signal status bit 385 flash memory control register (address 0057 16 ) _____ 1st line: .....the ry/by status flag..... _____ .....the ry/by signal status bit..... 390 13th line of page program command (41 16 ) and _____ fig 1.34.3: ry/by status flag _____ ry/by signal status bit 391 11th line of block erase command (20 16 /d0 16 ) _____ and fig 1.34.4: ry/by status flag _____ ry/by signal status bit 392 _____ fig 1.34.5: ry/by status flag _____ ry/by signal status bit 400 3rd paragraph, 1st line ....., set the clk 1 pin to h level and.... ....., set the clk 1 pin to h level and the txd1 pin to l level, and..... 400 3rd paragraph, 2nd line the clk 1 pin is connected to vcc.....resistance. add 401 p6 7 when using standard.....transfer. add 419 fig 1.35.22, data output pulled down 421 how frequency is identified, 2nd line: (2 - 20mhz) (2 - 30mhz)
keep safety first in your circuit designs! notes regarding these materials mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http:// www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. please contact mitsubishi electric corporation or an authorized mitsubishi semicon ductor product distributor for further details on these materials or the products con tained therein.
mitsubishi semiconductors m32c/83 group data sheet rev. b2 february first edition 2002 editioned by committee of editing of mitsubishi semiconductor data sheet published by mitsubishi electric corp., kitaitami works this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?2002 mitsubishi electric corporation

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